CN101894866B - Impact ionization type field effect transistor of concave channel and manufacturing method thereof - Google Patents

Abstract

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a collision ionization type field effect transistor of a recessed channel and a manufacturing method thereof. The semiconductor substrate, a drain region with a first doping type, which is positioned at the bottom of the substrate, a groove structure positioned in the substrate, a grid electrode covered in the groove and a grid dielectric layer positioned between the grid electrode and the semiconductor substrate; a source region with the second doping type and positioned at two sides of the groove and the top of the substrate, and an insulating medium layer positioned between the groove and the source region. The use of the recessed channel structure and the impact ionization working principle enables the transistor to inhibit the sub-threshold swing amplitude and simultaneously improve the driving current, so that the switching speed and the response frequency of the device are improved, and the off-state power consumption of the device is reduced. The field effect transistor is very suitable for manufacturing integrated circuit chips, in particular high-speed and high-power chips.

Description

Impact ionization field effect transistor with recessed channel and manufacturing method thereof

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a power semiconductor field effect transistor and a manufacturing method thereof, in particular to an impact ionization field effect transistor with a recessed channel and a manufacturing method thereof.

Background technique

Power semiconductor devices are the internal driving force of the continuous development of power-electronic systems, especially in terms of energy saving, dynamic control, noise reduction, etc., and have irreplaceable effects. Power semiconductors are mainly used to control the energy transfer between the energy source and the load, and have the characteristics of high precision, fast speed and low power consumption. In the past 20 years, power devices and their packaging technology have developed rapidly, especially power MOS transistors, which have replaced traditional bipolar transistors in many application fields due to their superior characteristics such as high input impedance and short turn-off time. Today's power MOS transistors mainly include trench MOS transistors (UMOSFETs) and insulated gate bipolar transistors (IGBTs).

The basic structure of an n-type UMOSFET is shown in FIG. There is a gate oxide layer 104 between it and the substrate. When the n-type UMOSFET is working, a positive voltage U _GS is applied between the gate and the source, and the gate is insulated, so no gate current will flow. But the positive voltage of the gate will push away the holes in the p+ region, and attract the minority carriers (electrons) in the p+ region to the surface of the p+ region at the gate. When U _GS is greater than U _T (turn-on voltage or threshold voltage), the electron concentration on the surface of the p+ region at the gate will exceed the hole concentration, making the P-type semiconductor invert into N-type and become an inversion layer, which forms The N channel makes the PN junction disappear, and the drain and source are turned on. The gate controls the current flow between the source and drain. Because the UMOSFET uses a vertical channel, the sidewall of the channel can be used as a gate, and its occupied area is smaller than that of a planar diffused MOSFET, which can further increase the area of the device, effectively reduce the on-resistance, and reduce the driving voltage.

IGBT is a composite full-control voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS transistor. The basic structure of an N-channel enhancement IGBT is shown in Figure 1b. The n-type source regions 114a and 114b are respectively formed in the p-type base regions (sub-channel regions) 113a and 113b, and the gate stack region includes gate oxide Layer 115 and gate electrode 116, the channel is formed close to the boundary of the gate region, the n-type drift region 112 is formed on the n-type drain region 111, and the p+ region 110 on the other side of the drain region 111 is called the drain implantation region, which It is the unique functional area of IGBT. Together with the drain area and the sub-channel area, it forms a PNP bipolar transistor, which acts as an emitter, injects holes into the drain area, and conducts conduction modulation to reduce the on-state voltage of the device. The switching function of the IGBT is to form a channel by adding a positive gate voltage, providing a base current to the PNP transistor, and turning the IGBT on; otherwise, adding a reverse gate voltage to eliminate the channel, cutting off the base current, and turning the IGBT off . IGBT has both the advantages of high input impedance of MOSFET and low conduction voltage drop of GTR (Giant Transistor, power transistor), which is very suitable for the conversion system with a DC voltage of 600V and above, such as AC motors, frequency converters, Switching power supply, lighting circuit, traction drive, etc.

However, since both UMOSFET and IGBT adopt a gate-controlled n-p-n or p-n-p structure, their minimum subthreshold swing (SS) is limited to 60mv/dec, which limits the switching speed of the transistor. On some chips with higher integration density, reducing the size of the device means a larger SS value, while for high-speed chips, a smaller SS value is required, and a smaller SS value can reduce chip power consumption while increasing the device frequency .

Contents of the invention

The purpose of the present invention is to propose a novel power semiconductor device structure to reduce the SS value of the device, thereby reducing power consumption of the chip while increasing the frequency of the device.

The impact ionization field effect transistor proposed by the present invention includes:

a semiconductor substrate;

a drain region with a first doping type located at the bottom of the semiconductor substrate;

a groove structure within the semiconductor substrate;

a gate covering within the groove;

a gate dielectric layer located between the gate and the semiconductor substrate;

a source region with a second doping type on the top of the substrate located on both sides of the groove;

an insulating dielectric layer between the groove and the source region.

Further, the semiconductor substrate is single crystal silicon, polycrystalline silicon or silicon on insulator (SOI). The gate is made of metal gate materials such as TiN, TaN, RuO ₂ , Ru, WSi, etc. or doped polysilicon. The gate dielectric layer is made of SiO ₂ , high-k material or a mixture thereof. The insulating dielectric layer is SiO ₂ , Si ₃ N ₄ or a mixture thereof.

Furthermore, the first doping type is n-type, and the second doping type is p-type; or, the first doping type is p-type, and the second doping type For n type.

The impact ionization field effect transistor proposed in the present invention uses a recessed channel, which can realize a longer channel in a smaller area, so its leakage current is smaller than that of the traditional type of field effect transistor, and similar to double The structure of the gate also improves the driving current of the device. At the same time, the use of the working principle of impact ionization suppresses the subthreshold swing of the device, thereby increasing the switching speed of the device. Therefore, the structure of the power semiconductor device proposed by the present invention can reduce the SS value of the device, thereby reducing power consumption of the chip while increasing the frequency of the device.

Simultaneously, the present invention also proposes the manufacturing method of above-mentioned impact ionization type field-effect transistor, and concrete steps are:

providing a semiconductor substrate;

performing ion implantation to form regions of the first doping type;

forming a first insulating film on the semiconductor substrate;

Depositing and forming the first layer of photoresist;

After the mask is exposed, etch the first insulating film until the silicon substrate is exposed;

Etching the silicon substrate to form an opening structure;

Stripping off the remaining first layer of photoresist;

forming a second insulating film covering the opening;

depositing a third insulating film, and etching the third insulating film to form a side wall structure;

Etching the second insulating film to expose the silicon substrate;

Etch the exposed silicon substrate using anisotropic etching technology along the formed sidewall structure;

Continue to etch the exposed semiconductor substrate using isotropic etching technology to form the groove structure of the device;

Use diluted hydrofluoric acid to clean the surface of the groove and remove the first layer of insulating film;

sequentially forming a fourth insulating film and a first conductive film in the groove;

Depositing a second layer of photoresist;

Mask exposure etching to form the gate structure of the device;

Stripping off the remaining second layer of photoresist;

Depositing a fifth insulating film, and etching to form a through hole;

Depositing a second conductive film and etching to form a metal electrode;

performing ion implantation to form regions of the second doping type;

depositing a sixth insulating film, and etching to form a through hole;

Deposit the third conductive film, and etch to form metal electrodes.

Further, the semiconductor substrate is single crystal silicon, polycrystalline silicon or silicon on insulator (SOI). The first, third, fifth and sixth insulating films are SiO ₂ , Si ₃ N ₄ or a mixture thereof. The second and fourth insulating films are SiO ₂ , high-k materials or a mixture thereof. The first conductive thin film is metal gate material such as TiN, TaN, RuO ₂ , Ru, WSi, etc. or doped polysilicon. The second and third conductive films are metal aluminum, metal tungsten or other metal conductive materials.

Furthermore, the first doping type is n-type, and the second doping type is p-type; or, the first doping type is p-type, and the second doping type For n type.

Description of drawings

Fig. 1a is a cross-sectional view of a UMOSFET structure in the prior art.

Fig. 1b is a cross-sectional view of an IGBT structure in the prior art.

FIG. 2 is a cross-sectional view of an embodiment of an impact ionization field effect transistor disclosed in the present invention.

3a to 3h are process flow charts of an embodiment of manufacturing the impact ionization field effect transistor shown in FIG. 2 .

Detailed ways

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for convenience of illustration, and the shown sizes do not represent actual sizes. The referenced figures are schematic illustrations of idealized embodiments of the invention, and the illustrated embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated in the figures but are to include resulting shapes, such as manufacturing-induced deviations. For example, the curves obtained by etching are usually curved or rounded, but in the embodiment of the present invention, they are all represented by rectangles. The representation in the figure is schematic, but this should not be considered as limiting the scope of the present invention. Also in the following description, the terms wafer and substrate used may be understood to include the semiconductor wafer being processed, possibly including other thin film layers prepared thereon.

Fig. 2 is an embodiment of an impact ionization field effect transistor disclosed by the present invention, which is a cross-sectional view along the channel length direction of the device. The field effect transistor includes a substrate region 201, source regions 202a and 202b, a drain region 213 and a gate stack region. The doping type of the source region 202a, 202b is generally opposite to that of the drain region 213 and the substrate region 201. The impurity concentrations of the source regions 202a, 202b and the drain region 213 are heavily doped, while the impurity concentration of the substrate region 201 is lightly doped. The gate stack region is composed of a high-k material layer 208 and a conductive layer 209, and the conductive layer 209 is metal gate material or doped polysilicon. High-k material layers 205a, 205b and silicon nitride layers 206a, 206b are located between the gate and source regions 202a, 202b. The insulating medium 210, 214 is the passivation layer of the field effect transistor, which isolates the transistor from other devices and protects the transistor from the external environment. The conductors 211a, 211b, 212, and 215 are metal materials, serving as metal electrodes of the field effect transistor.

When an appropriate bias voltage is applied to the gate, the surface of the substrate near the bottom of the gate will accumulate minority carriers (such as holes) to form an inversion layer 21 , thereby forming a conductive channel. The regions 22a, 22b between the source regions 202a, 202b and the inversion layer and the region 23 between the inversion layer 21 and the drain region 213 are used as acceleration paths for carriers sufficient to generate impact ionization events, and the height of the acceleration barrier is Controlled by the voltage applied to the gate. When the gate voltage is sufficient to form the inversion layer 21, there is an enhanced electric field across the regions 22a, 22b, 23, causing the regions 22a, 22b, 23 to punch through. And even a very high gate voltage will not cause the region 24 between the source region and the drain region to achieve punch-through.

The impact ionization field effect transistor disclosed in the present invention can be manufactured by many methods. The following description is an example of the manufacturing method of the impact ionization field effect transistor as shown in FIG. 2 disclosed in the present invention. 3a to 3h describe the process of manufacturing an impact ionization field effect transistor as shown in FIG. 2 .

Although these drawings do not completely reflect actual dimensions accurately, they still completely reflect the mutual positions between regions and constituent elements, especially the upper-lower and adjacent relationships among constituent elements.

First, a lightly doped n-type silicon substrate 301 is provided, followed by p-type ion implantation to form a doped region 302, as shown in FIG. 3a.

Next, a silicon dioxide film 303 is formed by oxidation, and a photoresist layer 304 is formed by deposition, followed by masking, exposure, and etching to form an opening structure as shown in FIG. 3b.

Next, the remaining photoresist layer 304 is stripped, and a high-k material layer 305 and a silicon nitride material layer 306 are sequentially deposited to form, and the silicon nitride material is etched to form a sidewall structure, as shown in FIG. 3c.

Next, etch the high-k material layer 305 to expose the silicon substrate, and use a combination of isotropic and anisotropic etching methods to etch the silicon substrate to form the recessed channel region 307 of the device, and then use thinning The hydrofluoric acid cleans the channel region to form the structure shown in Figure 3d.

Next, the remaining silicon dioxide film 303 is stripped off, and a high-k material layer 308, a conductive layer 309, and a photoresist layer are sequentially deposited, and then masked, exposed, and etched to form a high-k material layer 308 and a conductive layer 309 The gate structure of the device is finally stripped of the remaining photoresist layer, as shown in Figure 3e. The conductor layer 309 may be a metal gate material such as TiN, TaN, RuO ₂ , Ru, WSi, etc. or a doped polysilicon material.

Next, an insulating film 310 is deposited and formed, which may be silicon oxide or silicon nitride. Then deposit a layer of photoresist, then form a through hole by masking, exposing, and etching, and peel off the photoresist, then deposit a layer of metal, which can be aluminum or tungsten, and then etch to form the source Pole electrodes 311a, 311b and gate electrode 312, as shown in FIG. 3f.

Next, n-type ion implantation is performed to form the drain region 313 of the device, as shown in FIG. 3g.

Finally, an insulating film 314 is deposited and formed, which may be silicon oxide or silicon nitride, and a layer of photoresist is deposited, followed by masking, exposure, and etching to form a through-hole structure. After stripping off the remaining photoresist, metal aluminum or tungsten is deposited and etched to form a drain electrode 315, as shown in FIG. 3h.

As mentioned above, many widely different embodiments can be constructed without departing from the spirit and scope of the present invention. It should be understood that the invention is not limited to the specific examples described in the specification, except as defined in the claims.

Claims (6)

1. collision ionization type field effect transistor is characterized in that comprising:

A Semiconductor substrate;

Be positioned at the drain region with first kind of doping type of said Semiconductor substrate bottom;

Be positioned at the groove structure of said Semiconductor substrate;

Cover the grid within the said groove;

Gate dielectric layer between said grid and Semiconductor substrate;

Be positioned at said groove both sides, the source region with second kind of doping type of substrate top;

Insulating medium layer between said groove and said source region.

2. collision ionization type field effect transistor according to claim 1 is characterized in that, said Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon on the insulator.

3. collision ionization type field effect transistor according to claim 1 is characterized in that, said grid is TiN, TaN, RuO ₂, Ru or WSi metal gate material, perhaps polysilicon for mixing.

4. collision ionization type field effect transistor according to claim 1 is characterized in that, said gate dielectric layer is SiO ₂Or high k material, perhaps be the mixture between them.

5. collision ionization type field effect transistor according to claim 1 is characterized in that, said insulating medium layer is SiO ₂Or Si ₃N _4,It perhaps is the mixture between them.

6. collision ionization type field effect transistor according to claim 1 is characterized in that, said first kind of doping type is the n type, and said second kind of doping type is the p type; Be the p type for said first kind of doping type perhaps, said second kind of doping type is the n type.

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