CN101894866B - Collision ionization type field effect transistor of sinking channel and manufacture method thereof - Google Patents
Collision ionization type field effect transistor of sinking channel and manufacture method thereof Download PDFInfo
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- CN101894866B CN101894866B CN2010102205421A CN201010220542A CN101894866B CN 101894866 B CN101894866 B CN 101894866B CN 2010102205421 A CN2010102205421 A CN 2010102205421A CN 201010220542 A CN201010220542 A CN 201010220542A CN 101894866 B CN101894866 B CN 101894866B
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Abstract
The invention belongs to the technical field of power semiconductor devices, and in particular relates to a collision ionization type field effect transistor of a sinking channel and a manufacture method thereof. The collision ionization type field effect transistor comprises a semiconductor substrate, a drain region positioned at the bottom of the substrate and provided with a first doping type, a groove structure positioned in the substrate, a grid electrode covering in the groove, a dielectric layer positioned between the grid electrode and the semiconductor substrate, a source region positioned at both sides of the groove and the top of the substrate and provided with a second doping type, and an insulation dielectric layer positioned between the groove and the source region. The use of the sinking type channel structure and the collision ionization working principle ensures that the transistor can improve drive current while inhibiting a subthreshold oscillation range so as to further improve the switching speed and the response frequency of a device and simultaneously reduce the off-state power consumption of the device. The field effect transistor is very suitable for the manufacture of integrated circuit chips, particularly the manufacture of the high-speed high-power chips.
Description
Technical field
The invention belongs to the power semiconductor technical field, be specifically related to a kind of power semiconductor field effect transistor and manufacturing approach thereof, particularly a kind of collision ionization type field effect transistor of recess channel and manufacturing approach thereof.
Background technology
Power semiconductor is constantly the inherent actuating force of the power-electronic system of development, especially at aspects such as energy savings, dynamically control, noise minimizings, irreplaceable effect is arranged.Power semiconductor is mainly used in the control to NE BY ENERGY TRANSFER between the energy and the load, has precision height, speed characteristics fast and low in energy consumption.Over the past two decades, power device and encapsulation technology fast development, especially power MOS transistor with superior characteristic such as its input impedance height, turn-off time weak points, have replaced traditional bipolar transistor in many applications.Power MOS transistor of today mainly contains groove type MOS transistor (UMOSFET) and insulated gate bipolar transistor types such as (IGBT).
The basic structure of a kind of n type UMOSFET is shown in Fig. 1 a, and n type epitaxial loayer 101 is formed on the n type drain region 106, and n type source region 103a, 103b are respectively formed among p+ district 102a, the 102b, contain a gate oxide 104 between grid 105 and the substrate.When n type UMOSFET carries out work, to applying positive voltage U between grid and source electrode
GS, grid insulate, and does not flow through so do not have grid current.But the positive voltage of grid can be pushed the hole in the p+ district open, and the few son (electronics) in the p+ district is attracted to the surface, p+ district at grid place.Work as U
GSGreater than U
TWhen (cut-in voltage or threshold voltage), the electron concentration on p+ district, grid place surface will be above hole concentration, makes the P type semiconductor transoid become the N type and becomes inversion layer, and this inversion layer forms N raceway groove and PN junction is disappeared, and drains and the source electrode conducting.Electric current between grid control source electrode and the drain electrode.UMOSFET has been because adopted vertical raceway groove, and the sidewall of raceway groove can manufacturing grid, and its shared area is littler than planar diffusion type MOSFET, can further improve the area of device, and effectively reduces conducting resistance, reduces driving voltage.
The compound full-control type voltage driven type power semiconductor that IGBT is made up of BJT (double pole triode) and MOS transistor.The basic structure of a kind of N channel enhancement IGBT is shown in Fig. 1 b, and n type source region 114a, 114b are respectively formed among p type base (inferior channel region) 113a, the 113b, and the gate stack district comprises gate oxide 115 and gate electrode 116; Raceway groove is forming near the border, grid region, and n type drift region 112 is formed on the n type drain region 111, and the p+ district 110 of 111 opposite sides is called the leakage injection region in the drain region; It is IGBT functions peculiar district; Form the PNP bipolar transistor with drain region and inferior channel region, play emitter, to the drain region injected hole; Conduct electricity modulation, to reduce the on state voltage of device.The on-off action of IGBT is to form raceway groove through adding the forward grid voltage, base current is provided for the PNP transistor, makes the IGBT conducting, otherwise, add reverse grid voltage and eliminate raceway groove, cut off base current, IGBT is turn-offed.IGBT has high input impedance and GTR (the Giant Transistor of MOSFET concurrently; The advantage of low conduction voltage drop two aspects power transistor); Being fit to very much be applied to direct voltage is 600V and above converter system, like alternating current machine, frequency converter, Switching Power Supply, lighting circuit, towing gear etc.
But because UMOSFET and IGBT have all adopted grid-control n-p-n or p-n-p structure, their the minimum subthreshold value amplitude of oscillation (SS) is limited in 60mv/dec, and this has limited transistorized switching speed.On the higher chip of some integration densities, reduce size of devices and mean bigger SS value, and need littler SS value for high-speed chip, less SS value can reduce chip power-consumption when improving device frequency.
Summary of the invention
The objective of the invention is to propose a kind of new power semiconductor device structure,, and then can when improving device frequency, reduce chip power-consumption with the SS value of reduction device.
The collision ionization type field effect transistor that the present invention proposes comprises:
A Semiconductor substrate;
Be positioned at the drain region with first kind of doping type of said Semiconductor substrate bottom;
Be positioned at the groove structure of said Semiconductor substrate;
Cover the grid within the said groove;
Gate dielectric layer between said grid and Semiconductor substrate;
Be positioned at said groove both sides, the source region with second kind of doping type of substrate top;
Insulating medium layer between said groove and said source region.
Further, said Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Said grid is TiN, TaN, RuO
2, metal gate material or polysilicons such as Ru, WSi for mixing.Said gate dielectric layer is SiO
2, high k material or be the mixture between them.Said insulating medium layer is SiO
2, Si
3N
4It perhaps is the mixture between them.
Further, said first kind of doping type is the n type, and said second kind of doping type is the p type; Perhaps, said first kind of doping type is the p type, and said second kind of doping type is the n type.
Collision ionization type field effect transistor proposed by the invention has used recess channel; Can in less area, realize long raceway groove; Therefore its leakage current is littler than the field effect transistor tube leakage current of traditional type, and the structure of similar double grid has also improved the drive current of device.Simultaneously, the use of ionization by collision operation principle has suppressed the subthreshold value amplitude of oscillation of device, and then has improved the switching speed of device.Therefore, the power semiconductor device structure that the present invention proposes can reduce the SS value of device, and then can when improving device frequency, reduce chip power-consumption.
Simultaneously, the present invention also proposes the manufacturing approach of above-mentioned collision ionization type field effect transistor, and concrete steps are:
A Semiconductor substrate is provided;
Carry out ion and inject the zone that forms first kind of doping type;
On said Semiconductor substrate, form first kind of insulation film;
Deposit forms the ground floor photoresist;
First kind of insulation film of etching behind the mask exposure is until exposing silicon substrate;
The etch silicon substrate forms hatch frame;
Divest remaining ground floor photoresist;
Cover said opening and form second kind of insulation film;
The third insulation film of deposit, and said the third insulation film is carried out etching form the abutment wall structure;
Second kind of insulation film of etching exposes silicon substrate;
Along the abutment wall structure of moulding, the silicon substrate that uses anisotropic lithographic technique etching to expose;
Use isotropic lithographic technique to continue the Semiconductor substrate that etching exposes, form the groove structure of device;
Use the hydrofluoric acid clean groove surfaces of dilution and remove the ground floor insulation film;
In said groove, form the 4th kind of insulation film and first kind of conductive film successively;
Deposit forms second layer photoresist;
The mask exposure etching forms the grid structure of device;
Divest remaining second layer photoresist;
The 5th kind of insulation film of deposit, and etching forms through hole;
Second kind of conductive film of deposit, and etching forms metal electrode;
Carry out ion and inject, form the zone of second kind of doping type;
The 6th kind of insulation film of deposit, and etching forms through hole;
The third conductive film of deposit, and etching forms metal electrode.
Further, said Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Said first kind, the third, the 5th kind, the 6th kind insulation film be SiO
2, Si
3N
4It perhaps is the mixture between them.Said second kind, the 4th kind insulation film is SiO
2, high k material or be the mixture between them.Said first kind of conductive film is TiN, TaN, RuO
2, metal gate material or polysilicons such as Ru, WSi for mixing.Said second kind, the third conductive film are metallic aluminium, tungsten or are other metallic conduction material.
Further, said first kind of doping type is the n type, and said second kind of doping type is the p type; Perhaps, said first kind of doping type is the p type, and said second kind of doping type is the n type.
Description of drawings
Fig. 1 a is the sectional view of a kind of UMOSFET structure of prior art.
Fig. 1 b is the sectional view of a kind of IGBT structure of prior art.
Fig. 2 is the sectional view of an embodiment of the disclosed collision ionization type field effect transistor of the present invention.
Fig. 3 a to Fig. 3 h is for making the embodiment process chart of collision ionization type field effect transistor shown in Figure 2.
Embodiment
Below with reference to accompanying drawings illustrative embodiments of the present invention is elaborated.In the drawings, the thickness in layer and zone has been amplified in explanation for ease, shown in size do not represent actual size.Reference diagram is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all representes with rectangle, and the expression among the figure is schematically, but this should not be considered to limit scope of the present invention.Simultaneously in the following description, employed term wafer and substrate are appreciated that to be to comprise the just semiconductor wafer in processes, possibly comprise other prepared thin layer above that.
Fig. 2 is the embodiment of the disclosed a kind of collision ionization type field effect transistor of the present invention, and it is the profile along this device channel length direction.This field-effect transistor comprises substrate zone 201, source region 202a and 202b, drain region 213 and a gate stack district.The doping type of source region 202a, 202b is usually opposite with the doping type of drain region 213, substrate zone 201, and the impurity concentration in source region 202a, 202b and drain region 213 is heavy doping, and the impurity concentration of substrate zone 201 is a light dope.The gate stack district is made up of with conductive layer 209 high k material layer 208, and conductive layer 209 is metal gate material or the polysilicon for mixing.High k material layer 205a, 205b and silicon nitride layer 206a, 206b are between grid region and source region 202a, 202b.Dielectric the 210, the 214th, the passivation layer of this field-effect transistor, they separate other device of said transistor AND gate, and protect said transistor not receive the influence of external environment.Conductor 211a, 211b, 212, the 215th, metal material is as the metal electrode of this field-effect transistor.
When grid is applied suitable bias voltage, can accumulate minority carrier (such as the hole) and form inversion layer 21 near the substrate surface below the grid, thereby form conducting channel.Zone 23 between regional 22a between source region 202a, 202b and the inversion layer, 22b and inversion layer 21 and the drain region 213 is as the acceleration path of the charge carrier that is enough to produce the ionization by collision incident, and the height that quickens potential barrier is by the voltage control that is applied on the grid.When grid voltage is enough to form inversion layer 21, exist and to pass regional 22a, 22b, 23 enhancing electric field, make regional 22a, 22b, 23 break-through.Even and very high grid voltage can not make the zone 24 between source region and the drain region realize break-through yet.
The disclosed collision ionization type field effect transistor of the present invention can be through a lot of method manufacturings.It is following that what narrate is an instance of the manufacturing approach of the disclosed collision ionization type field effect transistor as shown in Figure 2 of the present invention.Fig. 3 a to Fig. 3 h has described the operation of making a collision ionization type field effect transistor as shown in Figure 2.
Although these figure can not entirely accurate reflect actual size, the reflection that they are complete mutual alignment between zone and the element, particularly between the element about and neighbouring relations.
At first, at the silicon substrate 301 that a light dope n type is provided, then carry out p type ion and inject formation doped regions 302, shown in Fig. 3 a.
Next, oxidation forms silica membrane 303, and deposit forms a photoresist layer 304, and then mask, exposure, etching form the hatch frame shown in Fig. 3 b.
Next, divest remaining photoresist layer 304, and deposit forms high k material layer 305 and silicon nitride material 306 successively, and etch silicon nitride material formation abutment wall structure, shown in Fig. 3 c.
Next; The high k material layer 305 of etching exposes silicon substrate, and the method for utilizing isotropic and anisotropic etching phase to combine, the silicon substrate etching is formed the recess channel zone 307 of device; Utilize the hydrofluoric acid of dilution that channel region is cleaned then, form the structure shown in Fig. 3 d.
Next; Divest remaining silica film 303, and deposit forms high k material layer 308, conductor layer 309 and photoresist layer successively, high k material layer 308 of mask, exposure and etching and conductor layer 309 form the grid structure of devices then; Divest remaining photoresist layer at last, shown in Fig. 3 e.Conductor layer 309 can be TiN, TaN, RuO
2, metal gate material or polycrystalline silicon materials such as Ru, WSi for mixing.
Next, deposit forms insulation film 310, can or be silicon nitride for silica.Deposit one deck photoresist passes through the method formation through hole of mask, exposure, etching then, and with photoresist lift off, follows deposit layer of metal more again, can be aluminium or tungsten, and etching forms source electrode 311a, 311b and gate electrode 312 then, shown in Fig. 3 f.
Next, carry out n type ion and inject the drain region 313 that forms device, shown in Fig. 3 g.
At last, deposit forms insulation film 314, can or be silicon nitride for silica, and deposit one deck photoresist, and mask, exposure, etching form through-hole structure then.After divesting remaining photoresist, depositing metal aluminium or tungsten, and etching formation drain electrode 315 are shown in Fig. 3 h.
As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like what claim limited, the invention is not restricted at the instantiation described in the specification.
Claims (6)
1. collision ionization type field effect transistor is characterized in that comprising:
A Semiconductor substrate;
Be positioned at the drain region with first kind of doping type of said Semiconductor substrate bottom;
Be positioned at the groove structure of said Semiconductor substrate;
Cover the grid within the said groove;
Gate dielectric layer between said grid and Semiconductor substrate;
Be positioned at said groove both sides, the source region with second kind of doping type of substrate top;
Insulating medium layer between said groove and said source region.
2. collision ionization type field effect transistor according to claim 1 is characterized in that, said Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon on the insulator.
3. collision ionization type field effect transistor according to claim 1 is characterized in that, said grid is TiN, TaN, RuO
2, Ru or WSi metal gate material, perhaps polysilicon for mixing.
4. collision ionization type field effect transistor according to claim 1 is characterized in that, said gate dielectric layer is SiO
2Or high k material, perhaps be the mixture between them.
5. collision ionization type field effect transistor according to claim 1 is characterized in that, said insulating medium layer is SiO
2Or Si
3N
4,It perhaps is the mixture between them.
6. collision ionization type field effect transistor according to claim 1 is characterized in that, said first kind of doping type is the n type, and said second kind of doping type is the p type; Be the p type for said first kind of doping type perhaps, said second kind of doping type is the n type.
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