CN110854192A - Tunneling field effect transistor and preparation method thereof - Google Patents
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
The application provides a tunneling field effect transistor and a preparation method thereof, wherein the tunneling field effect transistor comprises: a double buried oxide layer structure substrate; the double-buried-oxide-layer structure substrate at least comprises a silicon substrate, a first buried oxide layer, a silicon material layer and a second buried oxide layer from bottom to top in sequence, wherein the silicon material layer is provided with an air cavity; a source region, a channel region and a drain region; the source region, the channel region and the drain region are positioned on the surface of the second buried oxide layer, the channel region is connected between the source region and the drain region, and the positions of the source region and the channel region correspond to the air cavity; a gate dielectric layer and a gate material layer; the grid dielectric layer is at least positioned on the surface of the channel region, and the grid material layer is positioned on the surface of the grid dielectric layer; a source electrode, a drain electrode, and a gate electrode; the source electrode is formed on the surface of the source region, the drain electrode is formed on the surface of the drain region, and the gate electrode is formed on the surface of the gate material layer; a back gate electrode; the back gate electrode is formed on the surface of the silicon material layer, and the position of the back gate electrode corresponds to one side of the drain electrode.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a tunneling field effect transistor and a preparation method thereof.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in which carriers are hot-injected from the source into the channel across the PN junction barrier, and a Tunneling Field-Effect Transistor (TFET) operates by Band-to-Band Tunneling (BTBT), in which the PN junction is in a reverse bias state, when some unoccupied states in the N-region conduction Band and some occupied states in the P-region valence Band have the same energy, and when the barrier region is narrow, electrons tunnel from the P-region valence Band to the N-region conduction Band. The transistor designed by utilizing the electronic tunneling principle has the advantages of low subthreshold slope, low power consumption and the like, has a certain application prospect in the field of ultra-low power consumption chips, however, a bipolar parasitic current is easily formed by adopting an inverter structure designed by a Tunneling Field Effect Transistor (TFET), and great challenges are created on the performance and the functional reliability of a logic circuit.
Compared with the traditional bulk Silicon technology, the Silicon-on-insulator (SOI) technology introduces the buried oxide layer to isolate the top Silicon from the substrate, has the advantages of high speed, low power consumption, interference resistance and the like, can realize dynamic adjustment of threshold voltage by substrate bias, and has wide application prospect in the fields of high performance and low power consumption.
SOI-TFET is a semiconductor device technology that performs Tunneling Field Effect Transistor (TFET) design and fabrication on SOI wafers. However, because the top layer silicon of the SOI wafer is very thin, the area of the PN junction of the Tunneling Field Effect Transistor (TFET) prepared by using the SOI wafer is small, the on-state current driving capability is not high, and the off-state leakage current is large, which also limits the development of the SOI-TFET technology, so that a new technology needs to be adopted to improve the driving capability of the SOI-TFET transistor.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a tunneling field effect transistor and a method for manufacturing the same, which are used to solve the problems in the prior art that the tunneling field effect transistor is easy to form a bipolar parasitic current, and the on-state driving current is low.
In order to solve the above technical problem, an embodiment of the present application discloses a tunneling field effect transistor, including:
a double buried oxide layer structure substrate; the double-buried-oxide-layer structure substrate at least comprises a silicon substrate, a first buried oxide layer, a silicon material layer and a second buried oxide layer from bottom to top in sequence, wherein the silicon material layer is provided with an air cavity;
a source region, a channel region and a drain region; the source region, the channel region and the drain region are positioned on the surface of the second buried oxide layer, the channel region is connected between the source region and the drain region, and the positions of the source region and the channel region correspond to the air cavity;
a gate dielectric layer and a gate material layer; the grid dielectric layer is at least positioned on the surface of the channel region, and the grid material layer is positioned on the surface of the grid dielectric layer;
a source electrode, a drain electrode, and a gate electrode; the source electrode is formed on the surface of the source region, the drain electrode is formed on the surface of the drain region, and the gate electrode is formed on the surface of the gate material layer;
a back gate electrode; the back gate electrode is formed on the surface of the silicon material layer, and the position of the back gate electrode corresponds to one side of the drain electrode.
Optionally, the thickness of the second buried oxide layer is less than 500 nm.
Optionally, the material of the back gate electrode is a metal material.
Optionally, the material of the gate electrode is a metal material or a polysilicon material.
Optionally, a metal silicide layer is formed between the source region and the source electrode, between the drain region and the drain electrode, and between the gate material layer and the gate electrode.
Another aspect of the embodiments of the present application provides a method for manufacturing a tunneling field effect transistor, where the method includes the following steps:
preparing a double-buried-oxide-layer structure substrate, comprising: obtaining a first wafer; the first wafer sequentially comprises a first top silicon layer, a first buried oxide layer and a first bottom silicon layer from top to bottom;
grinding the surface of the first top silicon layer to obtain a thinned first top silicon layer;
photoetching at a preset position of the first top silicon layer to form an air cavity;
obtaining a second wafer; the second wafer sequentially comprises a second top silicon layer, a second buried oxide layer and a second bottom silicon layer from top to bottom;
thinning the second wafer to obtain a thinned second buried oxide layer and a thinned second top silicon layer;
bonding the first top silicon layer containing the air cavity and the second buried oxide layer to obtain a double buried oxide layer structure substrate;
preparing a source region, a channel region and a drain region, including: carrying out ion implantation doping in the first region of the second top silicon layer to form a source region, a channel region and a drain region;
preparing a gate dielectric layer and a gate material layer, including: forming a grid electrode dielectric layer on the surface of the second top silicon layer, and forming a grid electrode material layer on the surface of the grid electrode dielectric layer;
preparing a back gate electrode comprising: performing perforation etching on a second region of the second top silicon layer and a preset region of the second buried oxide layer to form a through hole, and filling electrode materials into the through hole to form a back gate electrode; the preset area corresponds to the second area;
preparing a source electrode, a drain electrode and a gate electrode, including: and respectively manufacturing a source electrode, a drain electrode and a gate electrode on the surface of the source region, the surface of the drain region and the surface of the gate material layer.
Optionally, thinning the second wafer to obtain a thinned second buried oxide layer and a thinned second top silicon layer, including:
removing the second bottom silicon layer;
and thinning the second top silicon layer and the second oxygen burying layer to obtain a thinned second oxygen burying layer and a thinned second top silicon layer.
Optionally, the source region is a P-type heavily doped semiconductor, the channel region is an N-type lightly doped semiconductor, and the drain region is an N-type heavily doped semiconductor.
Optionally, the ion implantation concentration of the source region is 1x1019～1x1021cm-3Leak, leakThe ion implantation concentration of the region is 1x1018～1x1020cm-3The ion implantation concentration of the channel region is 1x1015～1x1017cm-3。
Optionally, the gate dielectric layer and the gate material layer are formed by a chemical vapor deposition process.
By adopting the technical scheme, the application has the following beneficial effects:
according to the tunneling field effect transistor, the SOI with the double-buried-oxide-layer structure is used as the substrate, the back gate effect is combined, the bipolar parasitic current phenomenon can be effectively inhibited, the sub-threshold slope is improved, the back gate electrode is arranged on one side of the drain electrode region, the influence of the back gate electrode electric field on the source electrode electric field is reduced, the electron tunneling probability is improved, and therefore the on-state driving current is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a tunneling field effect transistor in the prior art;
fig. 2 is a schematic structural diagram of an alternative tunnel field effect transistor according to an embodiment of the present application;
fig. 3 is a flow chart illustrating an alternative process for fabricating a tunneling field effect transistor according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an alternative SOI wafer according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an alternative SOI wafer after photolithography of an air cavity according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an alternative thinned SOI wafer according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an alternative dual buried oxide structure substrate according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an alternative substrate with a dual buried oxide layer structure after a source region, a channel region, and a drain region are prepared in the embodiment of the present application;
fig. 9 is a schematic structural diagram of an alternative substrate with a dual buried oxide layer structure after a gate dielectric layer and a gate material layer are prepared in this embodiment of the present application;
FIG. 10 is a schematic structural diagram of a dual buried oxide structure substrate after an optional via etch according to an embodiment of the present application
The following is a supplementary description of the drawings:
1-a double buried oxide layer structure substrate; 101-a silicon substrate; 102-a first buried oxide layer; 103-a layer of silicon material; 103 a-air cavity; 104-a second buried oxide layer; 105-top layer silicon; 2-a source region; 3-a channel region; 4-a drain region; 5-a gate dielectric layer; 6-a layer of gate material; 7-a source electrode; 8-a drain electrode; 9-a gate electrode; 10-back gate electrode; 11-a top silicon layer; 12-buried oxide layer; 13-bottom silicon layer.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
The back gate effect of silicon-on-insulator (SOI) technology is that top silicon and substrate silicon are isolated by utilizing a buried oxide layer, and the top silicon electric field is regulated and controlled by applying an electric field on the substrate silicon, so that the carrier mobility is changed, and the semiconductor band structure is influenced, and further, the regulation and control of parameters such as the threshold voltage, the driving current, the parasitic capacitance and the like of a device are realized. The Tunneling Field Effect Transistor (TFET) is designed by utilizing the silicon-on-insulator (SOI) back gate effect, the bipolar parasitic current phenomenon can be effectively inhibited, the current switching ratio is improved, the subthreshold slope problem is further improved, and the method has wide application prospects in the fields of high performance and low power consumption.
Fig. 1 is a schematic structural diagram of an SOI-TFET transistor in the prior art, where after a voltage of a back gate electrode of the back gate SOI-TFET transistor is turned on, an on-state driving current is easily decreased.
Fig. 2 is a schematic structural diagram of an alternative tunneling field effect transistor according to an embodiment of the present application, where in fig. 2, the structure includes: a double buried oxide layer structure substrate 1; the substrate 1 with the double-buried oxide layer structure at least comprises a silicon substrate 101, a first buried oxide layer 102, a silicon material layer 103 and a second buried oxide layer 104 from bottom to top in sequence, wherein the silicon material layer 103 is provided with an air cavity 103 a;
a source region 2, a channel region 3, and a drain region 4; the source region 2, the channel region 3 and the drain region 4 are positioned on the surface of the second buried oxide layer 104, the channel region 3 is connected between the source region 2 and the drain region 4, and the positions of the source region 2 and the channel region 3 correspond to the air cavity 103 a;
a gate dielectric layer 5 and a gate material layer 6; the grid dielectric layer 5 is at least positioned on the surface of the channel region 3, and the grid material layer 6 is positioned on the surface of the grid dielectric layer 5; fig. 1 shows a situation where the gate dielectric layer 5 is located on the surfaces of the source region 2, the channel region 3, and the drain region 4, and in a specific implementation, the gate dielectric layer 5 may be located only on the surface of the channel region 3, may also be located on the surfaces of the source region 2 and the channel region 3, and may also be located on the surfaces of the channel region 3 and the drain region 4.
A source electrode 7, a drain electrode 8, and a gate electrode 9; the source electrode 7 is formed on the surface of the source region 2, the drain electrode 8 is formed on the surface of the drain region 4, and the gate electrode 9 is formed on the surface of the gate material layer 6;
a back gate electrode 10; the back gate electrode 10 is formed on the surface of the silicon material layer 103, and the position of the back gate electrode 10 corresponds to one side of the drain electrode 8.
According to the tunneling field effect transistor, the SOI with the double-buried-oxide-layer structure is used as the substrate, the back gate effect is combined, the bipolar parasitic current phenomenon can be effectively restrained, the sub-threshold slope is improved, the back gate electrode is arranged on one side of the drain electrode region, the influence of the back gate electrode electric field on the source electrode electric field is reduced, the electron tunneling probability is improved, and therefore the on-state driving current is improved.
As an alternative embodiment, the source region 2 is a heavily P-doped semiconductor, the channel region 3 is a lightly N-doped semiconductor, and the drain region 4 is a heavily N-doped semiconductor.
As an alternative embodiment, the thickness of the second buried oxide layer 4 is less than 500 nm.
As an alternative embodiment, the material of the back gate electrode 10 is a metal material.
As an alternative embodiment, the material of the gate electrode 9 is a metal material or a polysilicon material.
As an alternative embodiment, a metal silicide layer is formed between the source region 2 and the source electrode 7, between the drain region 4 and the drain electrode 8, and between the gate material layer 6 and the gate electrode 9.
Fig. 4 is a schematic structural diagram of an alternative SOI wafer according to an embodiment of the present disclosure, in which the SOI wafer includes a top silicon layer 11, a buried oxide layer 12, and a bottom silicon layer 13, a thickness of the top silicon layer 11 is preferably 10-150 nm, a thickness of the buried oxide layer 12 is preferably 5 nm-1 um, and a thickness of the bottom silicon layer 13 is preferably 100 nm-1 mm.
The embodiment of the present application further provides a preparation method of the tunneling field effect transistor, as shown in fig. 3, the preparation method includes the following steps:
step S1, preparing a double-buried-oxygen-layer structure substrate 1, including:
s101: obtaining a first SOI wafer; the first SOI wafer sequentially comprises a first top silicon layer, a first buried oxide layer and a first bottom silicon layer from top to bottom;
s102: grinding the surface of the first top silicon layer to obtain a thinned first top silicon layer;
s103: photoetching and forming an air cavity 103a at a preset position of the first top silicon layer to obtain the structure shown in FIG. 5;
s104: obtaining a second SOI wafer; the second SOI wafer sequentially comprises a second top silicon layer, a second buried oxide layer and a second bottom silicon layer from top to bottom;
s105: thinning the second SOI wafer to obtain a thinned second buried oxide layer and a thinned second top silicon layer, which have the structure shown in fig. 6;
s106: as shown in fig. 7, the dual buried oxide structure substrate 1 includes a silicon substrate 101, a first buried oxide layer 102, a silicon material layer 103, a second buried oxide layer 104, and a top silicon layer 105, wherein the silicon substrate 101 is a first bottom silicon layer of the first SOI wafer, the first buried oxide layer 102 is a first buried oxide layer of the first SOI wafer, the silicon material layer 103 is a first top silicon layer of the first SOI wafer, the second buried oxide layer 104 is a second buried oxide layer of the second SOI wafer, the top silicon layer 105 is a second top silicon layer of the second SOI wafer, and the air cavity 103a is located in the silicon material layer 103.
As an optional implementation manner, S105 specifically includes:
removing the second bottom silicon layer;
and thinning the second top silicon layer and the second oxygen burying layer to obtain a thinned second oxygen burying layer and a thinned second top silicon layer.
Step S2 of preparing the source region 2, the channel region 3, and the drain region 4 includes: ion implantation doping is performed on the first region of the second top silicon layer to form the source region 2, the channel region 3 and the drain region 4, so as to obtain the structure shown in fig. 8, wherein the positions of the source region 2 and the channel region 3 should correspond to the air cavity 103a, and the position of the drain region 4 should correspond to the silicon material of the first top silicon layer.
As an optional implementation manner, the source region 2 is a P-type heavily doped semiconductor, the channel region 3 is an N-type lightly doped semiconductor, and the drain 4 is an N-type heavily doped semiconductor, wherein P-type doped ions in the source region 2 are boron, and the ion implantation concentration is 1 × 1019～1x1021cm-3The N-type doped ions in the drain region 4 are phosphorus, and the ion implantation concentration is 1x1018～1x1020cm-3The N-type doped ion in the channel region 3 is phosphorus, and the ion implantation concentration is 1x1015～1x1017cm-3。
Step S3, preparing the gate dielectric layer 5 and the gate material layer 6, including: and forming a gate dielectric layer 5 on the surface of the second top silicon layer, and forming a gate material layer 6 on the surface of the gate dielectric layer 5 to obtain the structure shown in fig. 9.
As an alternative embodiment, the gate dielectric layer 5 and the gate material layer 6 are formed by a chemical vapor deposition process.
Step S4 is to prepare a back gate electrode 10 including: performing perforation etching on the second region of the second top silicon layer and the preset region of the second buried oxide layer to form a through hole 14, obtaining the structure shown in fig. 10, and filling the through hole 14 with an electrode material to form a back gate electrode 10; the preset area corresponds to the second area; the via 14 should be disposed at one side of the drain region 4, so that the electric field of the back gate electrode 10 does not affect the source electric field.
Step S5 of preparing the source electrode 7, the drain electrode 8, and the gate electrode 9 includes: a source electrode 7, a drain electrode 8 and a gate electrode 9 are formed on the surface of the source region 2, the surface of the drain region 4 and the surface of the gate material layer 6, respectively, to obtain the transistor structure shown in fig. 2.
As an alternative embodiment, the forming of the source electrode 7, the drain electrode 8 and the gate electrode 9 further includes the step of forming a metal silicide layer on the surface of the source region 2, the surface of the drain region 4 and the surface of the gate material layer 6.
And finally, preparing an electrode to finish the preparation process of the tunneling field effect transistor.
According to the technical scheme provided by the embodiment of the application, device manufacturing and wafer manufacturing are combined, a back gate tunneling field effect transistor structure with a double-buried oxide layer structure can be formed, the preparation is simple, and the preparation method can be compatible with a CMOS (complementary metal oxide semiconductor) process. According to the structure, the back gate electrode is introduced below the drain region, so that a bipolar parasitic current effect can be inhibited, the subthreshold slope is improved, and the on-state drive current of the device is not reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A tunneling field effect transistor, comprising:
a double buried oxide layer structure substrate (1); the double-buried-oxide-layer structure substrate (1) at least comprises a silicon substrate (101), a first buried oxide layer (102), a silicon material layer (103) and a second buried oxide layer (104) from bottom to top in sequence, wherein the silicon material layer (103) is provided with an air cavity (103 a);
a source region (2), a channel region (3) and a drain region (4); the source region (2), the channel region (3) and the drain region (4) are positioned on the surface of the second buried oxide layer (104), the channel region (3) is connected between the source region (2) and the drain region (4), and the positions of the source region (2) and the channel region (3) correspond to the air cavity (103 a);
a gate dielectric layer (5) and a gate material layer (6); the grid electrode dielectric layer (5) is at least positioned on the surface of the channel region (3), and the grid electrode material layer (6) is positioned on the surface of the grid electrode dielectric layer (5);
a source electrode (7), a drain electrode (8), and a gate electrode (9); the source electrode (7) is formed on the surface of the source region (2), the drain electrode (8) is formed on the surface of the drain region (4), and the gate electrode (9) is formed on the surface of the gate material layer (6);
a back gate electrode (10); the back gate electrode (10) is formed on the surface of the silicon material layer (103), and the position of the back gate electrode (10) corresponds to one side of the drain electrode (8).
2. The tunneling field effect transistor according to claim 1, wherein the thickness of the second buried oxide layer (4) is less than 500 nm.
3. The tunneling field effect transistor according to claim 1, wherein the material of the back gate electrode (10) is a metal material.
4. The tunneling field effect transistor according to claim 1, wherein the material of the gate electrode (9) is a metal material or a polysilicon material.
5. The tunneling field effect transistor according to claim 1, wherein a metal silicide layer is formed between the source region (2) and the source electrode (7), between the drain region (4) and the drain electrode (8), and between the gate material layer (6) and the gate electrode (9).
6. A preparation method of a tunneling field effect transistor is characterized by comprising the following steps:
preparing a substrate (1) with a double buried oxide layer structure, comprising: obtaining a first wafer; the first wafer sequentially comprises a first top silicon layer, a first buried oxide layer and a first bottom silicon layer from top to bottom;
grinding the surface of the first top silicon layer to obtain a thinned first top silicon layer;
photoetching at a preset position of the first top silicon layer to form an air cavity;
obtaining a second wafer; the second wafer sequentially comprises a second top silicon layer, a second buried oxide layer and a second bottom silicon layer from top to bottom;
thinning the second wafer to obtain a thinned second buried oxide layer and a thinned second top silicon layer;
bonding the first top silicon layer containing the air cavity and the second buried oxide layer to obtain the substrate (1) with the double buried oxide layer structure;
preparing a source region (2), a channel region (3) and a drain region (4), comprising: carrying out ion implantation doping on a first region of the second top silicon layer to form the source region (2), the channel region (3) and the drain region (4);
preparing a gate dielectric layer (5) and a gate material layer (6), including: forming the grid electrode dielectric layer (5) on the surface of the second top silicon layer, and forming the grid electrode material layer (6) on the surface of the grid electrode dielectric layer (5);
preparing a back gate electrode (10) comprising: performing perforation etching on a second region of the second top silicon layer and a preset region of the second buried oxide layer to form a through hole, and filling electrode materials into the through hole to form the back gate electrode (10); the preset area corresponds to the second area;
preparing a source electrode (7), a drain electrode (8) and a gate electrode (9), comprising: and manufacturing the source electrode (7), the drain electrode (8) and the gate electrode (9) on the surface of the source region (2), the surface of the drain region (4) and the surface of the gate material layer (6) respectively.
7. The method according to claim 6, wherein the thinning the second wafer to obtain the thinned second buried oxide layer and the thinned second top silicon layer comprises:
removing the second bottom silicon layer;
and thinning the second top silicon layer and the second oxygen burying layer to obtain a thinned second oxygen burying layer and a thinned second top silicon layer.
8. The preparation method of the tunneling field effect transistor according to claim 6, wherein the source region (2) is a heavily P-doped semiconductor, the channel region (3) is a lightly N-doped semiconductor, and the drain region (4) is a heavily N-doped semiconductor.
9. The method of claim 8, wherein the ion implantation concentration of the source region (2) is 1x1019～1x1021cm-3The ion implantation concentration of the drain region (4) is 1x1018～1x1020cm-3The ion implantation concentration of the channel region (3) is 1x1015～1x1017cm-3。
10. The device according to claim 6, wherein the gate dielectric layer (5) and the gate material layer (6) are formed by a chemical vapor deposition process.
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