CN101894821B - 半导体封装打线用的导线结构及其结合构造 - Google Patents

半导体封装打线用的导线结构及其结合构造 Download PDF

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CN101894821B
CN101894821B CN2010101874902A CN201010187490A CN101894821B CN 101894821 B CN101894821 B CN 101894821B CN 2010101874902 A CN2010101874902 A CN 2010101874902A CN 201010187490 A CN201010187490 A CN 201010187490A CN 101894821 B CN101894821 B CN 101894821B
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routing
lead core
conductor structure
coating
conductor
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CN101894821A (zh
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王德峻
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ASE Assembly & Test (Shanghai) Limited
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Ase Assembly & Test (shanghai) Ltd
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Abstract

本发明公开一种半导体封装打线用的导线结构及其结合构造，所述导线结构用于半导体封装打线工艺，其包含一导线芯材及包覆于其外表面的一同质镀层，所述同质镀层的晶粒较小，可提高所述导线结构的表面硬度及拉力强度。并且，于第二打线接合时，在所述导线结构表面的同质镀层及一打线接合表面之间可产生一接触面的微结构，可提供锚固附着作用，进而增强所述导线结构与所述接合表面的接合强度，故不但能达到与现有异质镀层的导线结构相当的导线打线接合强度及拉力强度，并且能进一步降低镀层材料成本。

Description

半导体封装打线用的导线结构及其结合构造
【技术领域】
本发明涉及一种半导体封装打线用的导线结构及其结合构造，特别是涉及一种在半导体封装打线工艺中利用同质镀层包覆导线芯材且同质镀层的晶粒粒径小于1微米的半导体封装打线用的导线结构及其结合构造。
【背景技术】
现有半导体封装构造制造过程中，打线接合(wire bonding)技术已广泛地应用于半导体芯片与封装基板或导线架之间的电性连接上。以半导体芯片与导线架之电性连接为例，其目的是利用极细的导线(小于50微米)将芯片上的接点连接到导线架上之内引脚上，进而将芯片之电路讯号传输到外界。当导线架被移送至打线位置后，应用电子影像处理技术来确定芯片上各个接点以及每一接点所相对应之内引脚上之接点的位置，然后做打线接合的动作。
请参照图1A、1B及1C所示，其揭示一种现有的导线应用于半导体封装打线工艺中的打线接合方法的流程示意图。当进行一芯片10与一导线架20打线接合时，以芯片10上的接点为第一焊接点11，以导线架20的内引脚上之接点为第二焊接点21。首先，如图1A所示，提供一焊针(capillary)30用以输出一导线31，以及提供一电子火焰点火杆(electronic flame offwand)(未绘示)用以在导线31的端部形成焊球(未标示)，而后将焊球压焊在第一焊接点11上(此称为第一接合，first bond)。接着，如图1B所示，依照设计好之路径移动焊针30，最后焊针30将导线31压焊在第二焊接点21上(此称为第二接合，second bond)。接着，如图1C所示，拉断焊针30在第二焊接点21处的导线31，从而完成一条导线31的打线接合动作。接着，焊针30上的导线31又再一次重新熔结形成焊球，以开始下一条导线31之打线接合动作。
在一般打线接合制造过程是以金线(gold wire)为主，但相较于金线，铜线(copper wire)具有低成本的优势且具有较佳的导电性、导热性及机械强度，因而铜制焊线的线径可设计得更细且散热效率较佳。然而，铜线最大的缺点在于铜金属本身容易与氧起氧化反应。特别是，当铜线处于高温打线环境下时，铜线表面极易发生严重的氧化问题，因而影响了铜线与半导体芯片或基板的焊垫之间的结合可靠度。
为了解决上述技术问题，在使用铜线打线接合时，可于铜线外层镀上一惰性金属层，例如钯(palladium)，以解决铜线表面发生氧化的问题。并且，此种表面具有异质镀层(钯镀层)的导线相较于纯质无镀层的导线具有较高的导线表面硬度与拉力强度，并且此种表面硬度较高的导线，当其与焊接点接合时(特别是指第二接合)，在接触面上可提供足够的锚固附着力，进而提高了焊接点的强度。
但是，此种表面具有异质镀层导线的成本通常相较于纯质导线的成本为高。并且，在进行第一接合形成焊球时，因为惰性金属薄层易于所述铜线的焊球表面上产生不规则的成分分布，而使所述焊球具有不均匀的同质、异质接合介面。结果，造成打线工艺难以控制使第一接合的焊球结合构造具有一致性(uniform)的结合可靠度表现，因而影响打线质量(quality)以及打线工艺的可操控性。
因此，有必要提供一种半导体封装打线用的导线结构及其结合构造，以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的是提供一种半导体封装打线用的导线结构，其用于半导体封装打线工艺，其导线结构包含导线芯材及包覆于其外表面的同质镀层，同质镀层的材质与导线芯材的材质相同，且同质镀层的晶粒较导线芯材的晶粒小，同质镀层可提高所述导线结构的表面硬度及拉力强度，同时此种同质镀层导线的成本相较于异质镀层导线的成本亦可降低。
本发明的次要目的是提供一种半导体封装导线结合构造，其形成于半导体封装打线工艺，其导线结构包含导线芯材及包覆于其外表面的同质镀层，同质镀层的材质与导线芯材的材质相同，且同质镀层的晶粒较导线芯材的晶粒小，同质镀层可提高所述导线结构的表面硬度及拉力强度，因此在第二打线接合时，可以在导线结构表面的同质镀层及打线接合表面之间产生一接触面的微结构，以提供锚固附着作用，增强接合强度，达到与现有异质镀层的导线结构相当的导线拉力强度与打线接合强度，并且能进一步降低镀层材料成本。
为达上述目的，本发明提供一种半导体封装打线用的导线结构，其用于半导体封装打线工艺，其特征在于：所述导线结构包含：一导线芯材；及一同质镀层，包覆于所述导线芯材的外表面，其中所述同质镀层的材质与所述导线芯材的材质相同，且所述同质镀层的晶粒粒径小于1微米。
在本发明的一实施例中，所述导线芯材是一单晶的导线芯材。
在本发明的一实施例中，所述导线芯材是一多晶的导线芯材，且所述同质镀层的晶粒粒径小于所述导线芯材的晶粒粒径。
在本发明的一实施例中，所述同质镀层的晶粒粒径小于所述导线芯材的晶粒粒径至少10倍。
在本发明的一实施例中，所述导线芯材的直径大于或等于20微米。
在本发明的一实施例中，所述同质镀层的厚度小于或等于1微米。
在本发明的一实施例中，所述导线芯材的材质选自铜、铝、银或金，所述同质镀层的材质与所述导线芯材的材质相同。
为达上述的另一目的，本发明提供一种半导体封装打线用的导线结合构造，其用于半导体封装打线工艺，其特征在于：所述导线结构包含一导线芯材；及一同质镀层，包覆于所述导线芯材的外表面，其中所述导线结构具有一结球端及一截切端，所述截切端结合于一打线接合表面，所述同质镀层的材质与所述导线芯材的材质相同，且所述同质镀层的晶粒小于1微米，其中所述导线芯材及所述打线接合表面之间存在由所述同质镀层形成的一接触面微结构。
在本发明的一实施例中，所述导线芯材是一单晶的导线芯材。
在本发明的一实施例中，所述导线芯材是一多晶的导线芯材，且所述同质镀层的晶粒粒径小于所述导线芯材的晶粒粒径。
在本发明的一实施例中，所述导线芯材的材质选自铜、铝、银或金，所述同质镀层的材质与所述导线芯材的材质相同。
【附图说明】
图1A～1C：现有的导线应用于半导体封装打线工艺中的打线接合方法的流程示意图。
图2：本发明第一实施例的一种半导体封装打线用的导线结构的剖面图。
图3A～3C：本发明第一实施例的一种半导体封装打线工艺中的打线接合(第一接合，first bond)方法的流程示意图。
图4A～4C：本发明第一实施例的一种半导体封装打线工艺中的打线接合(第二接合，second bond)方法的流程示意图。
图5：本发明第一实施例的一种半导体封装打线用的导线结合构造剖面图(图4C)的局部放大图。
图6：本发明第二实施例的一种半导体封装打线用的导线结构的剖面图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下：
请参照图2所示，其揭示本发明第一实施例的一种半导体封装打线用的导线结构的剖面图，本发明的一导线结构40包含一导线芯材41及包覆于其外表面的一同质镀层42，所述同质镀层42的材质与所述导线芯材41的材质相同，并且本发明的所述同质镀层42的晶粒(grain)粒径(grain size)小于所述导线芯材41的晶粒粒径。
如图2所示，在本发明中第一实施例中，所述导线芯材41的材质可选自铜(Cu)、铝(Al)、银(Ag)或金(Au)等，但不限于此。所述导线芯材41是一多晶(poly-crystalline)的导线芯材41，所谓多晶，是指材料内的数个晶粒是由排列方向并不相同的原子群所组成，而晶粒与晶粒间会产生晶界(grainboundaries)的结构缺陷。
再者，在本发明中第一实施例中，所述同质镀层42的材质与所述导线芯材41的材质相同，所述同质镀层42可选择利用各镀层的技术(如电镀、无电沉积、蒸镀等)来制作形成，其中优选是无电沉积，但本发明并不限制其镀层的方法。如图2所示，本发明第一实施例中的所述同质镀层42的厚度是由所述同质镀层42晶粒的大小及其排列的层数所决定。所述同质镀层42是由一排或一排以上的晶粒所组成，也就是所述同质镀层42的厚度至少等于或大于一个所述同质镀层42的晶粒大小。
如上所述，本发明的所述同质镀层42的晶粒粒径小于所述导线芯材41的晶粒粒径。因此，所述同质镀层42与所述导线芯材41具有一定的比例关系。以一般所述导线芯材41的直径是大于或等于20微米(μm)为例，所述同质镀层42优选与所述导线芯材41具有的比例关系是：
所述同质镀层42的晶粒粒径小于所述导线芯材41的晶粒粒径至少10倍；
或者，所述同质镀层42的晶粒粒径小于1微米(μm)；
或者，所述同质镀层42的厚度小于或等于1微米(μm)，其中所述同质镀层42的厚度最少是等于一个所述同质镀层42的晶粒大小。
由于所述同质镀层42的晶粒较小，因此所述导线结构40虽然不是异质镀层的结构(例如表面镀有钯层的铜线)，但相对于所述导线芯材41，所述同质镀层42也能提供较大的表面硬度及拉力强度。并且，相较于现有异质镀层，所述同质镀层42的镀层材料成本较低。并且，改善了由于异质镀层所导致的焊球具有不均匀的同质、异质接合介面的情况。
请参照图3A、3B及3C所示，其揭示本发明第一实施例的一种半导体封装打线工艺中的打线接合(第一接合，first bond)方法的流程示意图。如图3A所示，在本实施例中，所述第一接合动作的打线接合方法首先是：提供一焊针30及一邻接于所述焊针30的电子点火杆(未绘示)，所述焊针30具有一供线孔(未标示)，以输出所述导线结构40。接着，本发明通过上述焊针30及电子点火杆使所述导线结构40的一端焊接于一第一接合表面50。通过所述焊针30的供线孔输出所述导线结构40，所述导线结构40凸出所述焊针30的供线孔一长度。其中，所述导线结构40的特征在于：所述同质镀层42的材质与所述导线芯材41的材质相同，并且所述同质镀层42的晶粒粒径小于所述导线芯材41的晶粒粒径。
再者，所述第一接合表面50例如是一芯片的焊垫，但亦可能为导线架(leadframe)的内引脚或是基板(substrate)电路的接点。在本实施例中，所述第一接合表面50是一芯片的焊垫，所述焊垫的表面材质例如为铝，但并不限于此。
接着，如图3B所示，本发明通过所述电子点火杆(未绘示)的点火加热，使所述焊针30输出的导线结构40的端部的导线芯材41及同质镀层42熔结形成一焊球B，其中所述焊球B的直径至少大于所述导线结构40的最大外径。此时，由于所述导线结构40的同质镀层42的材质与所述导线芯材41的材质相同，因此所述同质镀层42将与所述导线芯材41熔融在一起，以形成材质均匀的所述焊球B。
最后，如图3C所示，本发明通过将所述焊针30下压，使所述导线结构40的一端，即所述焊球B焊接于所述第一接合表面50，并形成所述导线结构40的一结球端43。
综上所述，由于本发明的所述导线结构40包含所述导线芯材41及包覆于其外表面的所述同质镀层42，而所述同质镀层42的材质与所述导线芯材41的材质相同，因此在第一接合形成焊球时，能提供一材质均匀的焊球B与第一接合表面50进行焊接，以增进焊点的结合可靠度。
请再参照图4A、4B及4C所示，其揭示本发明第一实施例的一种半导体封装打线工艺中的打线接合(第二接合，second bond)方法的流程示意图，在完成第一实施例的打线接合制造过程的第一接合动作后，依照设计好之移动路径，所述焊针30牵引所述导线结构40至第二接合的位置，通过另一打线接合方法使所述导线结构40的另一端焊接于一第二接合表面60，所述第二接合表面60例如可以是导线架(leadframe)的内引脚或基板(substrate)电路的接点，但亦可能是芯片的焊垫，在本实施例中，所述第二接合表面60是一导线架(leadframe)的内引脚。
如图4A、4B及4C所示，所述打线接合制造过程的第二接合的详细说明如下：首先，如图4A所示，本发明通过所述焊针30的供线孔继续输出所述导线结构40，并从第一接合的第一接合表面50(未绘示)牵引所述导线结构40，直到所述导线结构40到达所述第二接合表面60上方为止。其中，所述镀层42及所述第二接合表面60的材质例如为铝(Al)、银(Ag)或金(Au)，但并不限于此。
接着，如图4B所示，本发明通过将所述焊针30下压，而使所述焊针30的供线孔的所述导线结构40一小段焊接于所述第二接合表面60。
最后，如图4C所示，本发明通过将所述焊针30上升，使所述导线结构40被拉断，同时保留所述导线结构40的接点于所述第二接合表面60上，以完成打线接合制造过程的第二接合动作，并形成所述导线结构40的一截切端44。
如图5所示，其揭示本发明图4C的导线结合构造剖面图的局部放大图，其中所述导线结构40包含所述导线芯材41及包覆于其外表面的所述同质镀层42，并且具有所述截切端44，所述截切端44结合于一打线接合表面60，所述同质镀层42的材质与所述导线芯材41的材质相同，且所述同质镀层42的晶粒小于1微米，其中所述导线结构40的同质镀层42及所述打线接合表面60之间存在由所述同质镀层42形成的一接触面S。
由于所述同质镀层42的晶粒较小，可使所述导线结构40表面硬度提高，因此在进行第二接合打线时，能够在所述导线结构40的表面(所述同质镀层42)及所述打线接合表面60之间形成所述不规则接触面S。所述接触面S可产生一种微结构锚固附着作用，因此可增强所述导线结构40与所述第二接合表面60的接合强度。因此，虽然本发明的所述导线结构40不是现有异质镀层的导线结构(例如表面镀有钯层的铜线)，但也能具有相当于现有异质镀层导线结构的导线打线接合强度及拉力强度，并且本发明的所述导线结构40具有较低的镀层材料成本。
请参照图6所示，其揭示本发明第二实施例的一种半导体封装打线用的导线结构的剖面图，本发明第二实施例相似于本发明第一实施例，并大致沿用相同元件名称与图号。在本发明第二实施例中，一导线结构40包含一导线芯材41及包覆于其外表面的一同质镀层42，所述同质镀层42的材质与所述导线芯材41的材质相同，并且，本发明的所述同质镀层的晶粒(grain)粒径(grain size)小于所述导线芯材的晶粒粒径。
本发明第二实施例与第一实施例不同的地方在于：所述导线芯材41是一单晶(single crystal)的导线芯材41，所谓单晶是指凝固过程经严谨控制，原子的聚集仅从一处成长，所形成仅有一个晶粒未具有晶界缺陷的结晶材料。而此种单晶所形成的导线芯材41能具有更佳的讯号传送质量。
如图6所示，所述同质镀层42与所述导线芯材41具有一定的比例关系。以一般所述导线芯材41的直径是大于或等于20微米(μm)为例，所述同质镀层42优选与所述导线芯材41具有的比例关系是：
所述同质镀层的晶粒粒径小于1微米(μm)；
或者，所述同质镀层42的厚度小于或等于1微米(μm)，其中所述同质镀层42的厚度最少是等于一个所述同质镀层42的晶粒大小。
综上所述，在现有的铜线表面具有钯材等异质镀层中，虽然异质镀层可提高其导线表面硬度、拉力强度及在第二接合的焊接点的强度，但是镀层的材料成本也相对提高。反观，如图2至6所示，本发明的导线结构40包含所述导线芯材41及包覆于其外表面的所述同质镀层42，由于所述同质镀层42的晶粒较小，可提高所述导线结构40的表面硬度及拉力强度。并且，在所述导线结构40表面及所述打线接合表面60之间可产生所述接触面S的微结构，以提供锚固附着作用，进而增强所述导线结构40与所述第二接合表面60的接合强度，故不但能达到与现有异质镀层的导线结构相当的导线打线接合强度及拉力强度，并且能进一步降低镀层材料成本。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

1.一种半导体封装打线用的导线结构，其用于半导体封装打线工艺，其特征在于：所述导线结构包含：一导线芯材；及一同质镀层，包覆于所述导线芯材的外表面，其中所述同质镀层的材质与所述导线芯材的材质相同，所述同质镀层的晶粒粒径小于1微米且小于所述导线芯材的晶粒粒径。
2.如权利要求1所述的半导体封装打线用的导线结构，其特征在于：所述导线芯材是一单晶的导线芯材。
3.如权利要求1所述的半导体封装打线用的导线结构，其特征在于：所述导线芯材是一多晶的导线芯材。
4.如权利要求3所述的半导体封装打线用的导线结构，其特征在于：所述同质镀层的晶粒粒径小于所述导线芯材的晶粒粒径至少10倍。
5.如权利要求1所述的半导体封装打线用的导线结构，其特征在于：所述同质镀层的厚度小于或等于1微米。
6.如权利要求1所述的半导体封装打线用的导线结构，其特征在于：所述导线芯材的材质选自铜、铝、银或金，所述同质镀层的材质与所述导线芯材的材质相同。
7.一种半导体封装导线结合构造，其形成于半导体封装打线工艺，其特征在于：所述半导体封装导线结合构造包含：一导线芯材；及一同质镀层，包覆于所述导线芯材的外表面，其中所述半导体封装导线结合构造具有一结球端及一截切端，所述截切端结合于一打线接合表面，所述同质镀层的材质与所述导线芯材的材质相同，所述同质镀层的晶粒粒径小于1微米且小于所述导线芯材的晶粒粒径，其中所述导线芯材及所述打线接合表面之间存在由所述同质镀层形成的一接触面微结构。
8.如权利要求7所述的半导体封装导线结合构造，其特征在于：所述导线芯材是一单晶的导线芯材。
9.如权利要求7所述的半导体封装导线结合构造，其特征在于：所述导线芯材是一多晶的导线芯材。
10.如权利要求7所述的半导体封装导线结合构造，其特征在于：所述导线芯材的材质选自铜、铝、银或金，所述同质镀层的材质与所述导线芯材的材质相同。
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