CN101888748B - Manufacturing method of circuit board - Google Patents
Manufacturing method of circuit board Download PDFInfo
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- CN101888748B CN101888748B CN200910137583A CN200910137583A CN101888748B CN 101888748 B CN101888748 B CN 101888748B CN 200910137583 A CN200910137583 A CN 200910137583A CN 200910137583 A CN200910137583 A CN 200910137583A CN 101888748 B CN101888748 B CN 101888748B
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- circuit board
- conductive layer
- manufacture method
- bump structure
- metal bump
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Abstract
The invention discloses a manufacturing method of a circuit board, which comprises the steps of: providing a substrate with a tapered metallic bump structure; laminating the substrate with an insulation layer so as to ensure that the tapered metallic bump structure pierces the insulation layer , exposing a tip part; laminating a metallic layer to ensure that the tip part is extruded to form a passivation part; flattening the metallic layer; and forming a conductive layer on the insulation layer, wherein the conductive layer is in contact with the passivation part.
Description
Technical field
The invention relates to the circuit board technology field, particularly relevant for the manufacture method of internal layer conducting thin plate in a kind of circuit board or internal layer web.
Background technology
Circuit board is an indispensable key component in the electronic installations such as computer, mobile phone, mainly is responsible for signal transmission, binding between the internal electrical components, and heat sinking function is provided.Constantly pursue under the compact trend at electronic installation; The live width of the lead on the circuit board is also constantly and then dwindled; Therefore the dealer there's no one who doesn't or isn't joins hands in how studying limiting factors such as breakthrough process, material, to obtain low cost, to possess high confidence level, high performance circuit board simultaneously.
According to application, circuit board is broadly divided into single sided board, double sided board, the above multi-layer sheet of four laminates and soft board or the like.Generally speaking, the electronic product function is more complicated, loop distance is longer, contact pin number is many more, and the required number of plies of circuit board is also many more, for example high-order consumer electronics, information and communication product etc.And soft board be mainly used in need curved around product in, for example mobile computer, camera, automobile instrument etc.
In the past, the normally first etching copper of the production method window of the internal layer conducting thin plate (or internal layer web) in the circuit board, again with laser punching, last re-plating filling perforation; Perhaps, utilize laser (DLD) technology of directly holing, direct laser punching, and then electroplate filling perforation.Wherein, it is that general blind hole is electroplated (non-filling perforation type) that the specification that pore-forming is electroplated has two: one usually, and another kind of is that filling perforation is electroplated.
The specification that above-mentioned two kinds of pore-formings are electroplated all has its defective, and for example, the defective that general blind hole is electroplated is that the electroplated metal layer thickness is not enough to be applied to high density, high radiating requirements field; And the defective that filling perforation is electroplated is that the thickness of insulating layer increase causes degree of difficulty, plate face planarization and the follow-up quality confidence level problem of electroplating filling perforation, for example, and the not good phenomenon of electroplating qualities such as cavity and bubble, and the quality of plating filling perforation is subject to the pore size influence.
In addition; In the technical literature relevant with the present invention; Chinese patent Granted publication CN1053785C has disclosed a kind of buried bump interconnection technology (Buried Bump Interconnection Technology); It is a kind of new layer technology that increase of Toshiba (Toshiba) exploitation, and step comprises: on a base plate, form copper foil pattern; The silver paste of on copper foil pattern, repeating print forms near cone shape conductor projection; Then with insulating barrier, for example, synthetic resin is pressed together on the circular cone conductor projection, and makes circular cone conductor projection run through insulating barrier; Then another definition there is the base plate alignment circular cone conductor projection of copper foil pattern and carries out hot pressing; At last, remove base plate.
Yet the shortcoming of this patent is, the poor thermal conductivity of the coniform conductor projection that it utilizes elargol to repeat print to constitute; It is not enough that engaging force between elargol and the copper foil pattern is also disliked in high reliability is used; And utilize mode of printing formation circular cone conductor projection that the restriction on its printing density is arranged.
Summary of the invention
So the object of the invention is providing a kind of circuit board manufacturing method of improvement, can reduce cost replaces the practice of past pore-forming and plating filling perforation, and can not receive the restriction of via aspect ratio, does not also have the bad quality confidence level influence of the electroplates in hole bubble.
For reaching above-mentioned purpose, the present invention provides a kind of preparation method of circuit board, includes: a substrate with taper metal bump structure is provided, and metal coupling for example is copper or silver metal; Make this substrate and an insulating barrier pressing, this taper metal bump structure pierces through this insulating barrier, and exposes a most advanced and sophisticated position; Pressing one metal level is squeezed this position, tip, forms a passivation part; Carry out a flatening process and remove this passivation part of this metal level and part, the upper surface that makes this passivation part of this surface of insulating layer and exposure is a copline; On this insulating barrier, form a conductive layer, contact this passivation part; On this conductive layer, form a photoresist and carve the agent pattern; Carry out an electroplating technology, on this conductive layer that exposes, to form electrodeposited coating; This photoresist is carved the agent pattern to be divested; And erosion forms a patterned circuit except that this conductive layer that comes out.
Your, see also following about detailed description of the present invention and accompanying drawing in order to make juror can further understand characteristic of the present invention and technology contents.Yet appended graphic only for reference and aid illustration usefulness is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Figure 10 is the manufacture method sketch map according to the circuit board that the preferred embodiment of the present invention illustrated.
Figure 11 to Figure 13 is the manufacture method sketch map of the circuit board that illustrated according to another preferred embodiment of the present invention.
Wherein, description of reference numerals is following:
10 substrates
12 taper metal bump structures
The most advanced and sophisticated position of 12a
The 12b passivation part
14 insulating barriers
15 metal levels
16 conductive layers
20 photoresists are carved the agent pattern
The 20a opening
22 copper electroplating layers
24 patterned circuit
35 steel plate moulds
Embodiment
See also Fig. 1 to Figure 10, it is the manufacture method sketch map according to the circuit board that the preferred embodiment of the present invention illustrated.As shown in Figure 1, a substrate 10 at first is provided, for example, Copper Foil then, forms a plurality of taper metal bump structures 12 on substrate 10.
According to a preferred embodiment of the invention; Taper metal bump structure 12 is to utilize to comprise mode formers such as plating, etching or mould printing; For example; Form a bronze medal layer (comprising chemical copper layer and copper electroplating layer) with plating mode at substrate 10, etch taper metal bump structure 12 with etching mode again.
As shown in Figure 2, form an insulating barrier 14.With this insulating barrier 14, for example, preimpregnation material (prepreg); It includes B stage (B-stage) thermosetting resin; Towards taper metal bump structure 12, insulating barrier 14 and substrate 10 are fitted, and when fitting; Taper metal bump structure 12 meeting insulation-piercing layers 14, and expose its most advanced and sophisticated position 12a.
According to another preferred embodiment of the invention, the practice that forms insulating barrier 14 can also be utilized the liquid resin coating technique.
Like Fig. 3 and shown in Figure 4, then utilize a metal level 15 to carry out pressing, make taper metal bump structure 12 insulation-piercing layers 14, and the most advanced and sophisticated position 12a that exposes is squeezed and is out of shape, form passivation part 12b.According to a preferred embodiment of the invention, between 65 microns to 250 microns, it can be copper, aluminium or other metal to the thickness of thick metal layers 15 approximately.
As shown in Figure 5; Then, at high temperature, for example; 190 ℃ to 200 ℃; Insulating barrier 14 hot settings that will contain B stage thermosetting resin become C stage (C-stage) thermosetting resin, then metal level 15 and passivation part 12b are carried out whole plane etching thinning, perhaps with polishing mode with its planarization or coplineization.
Through after the coplineization, at this moment, the surface of its upper surface that comes out of passivation part 12b and insulating barrier 14 is a copline, and passivation part 12b can not protrude from the surface of insulating barrier 14 in fact.
As shown in Figure 6; After accomplishing coplineization; Then form a conductive layer 16, its practice can be to utilize galvanoplastic (comprising chemical copper layer and copper electroplating layer), physical vapour deposition (PVD) (physical vapor deposition, PVD) method, sputtering method or utilize special covering material; For example, tape tree fat conductor foil (primer coated foil).
As shown in Figure 7, then on conductive layer 16, form photoresist and carve agent pattern 20, wherein, photoresist is carved agent pattern 20 and is included opening 20a, defines the position of patterned circuit, and exposes the conductive layer 16 of part.
As shown in Figure 8, carry out electroplating technology, in the opening 20a of photoresist agent at quarter pattern 20, form copper electroplating layer 22.
As shown in Figure 9, then photoresist is carved agent pattern 20 and divest, stay copper electroplating layer 22, and expose the conductive layer 16 of part.
Shown in figure 10, erosion at last removes the conductive layer 16 of the part that comes out, and forms patterned circuit 24 (comprising conductive layer 16 and copper electroplating layer 22).
Figure 11 to Figure 13 illustrates the sketch map of another embodiment of the present invention.Like Figure 11 and shown in Figure 12, on substrate 10, form a plurality of taper metal bump structures 12, metal coupling for example is copper or silver metal, and forms after the insulating barrier 14, utilizes a steel plate mould 35 that most advanced and sophisticated position 12a is squeezed into passivation part 12b immediately.
Then, shown in figure 13, at high temperature; For example, 190 ℃ to 200 ℃, insulating barrier 14 hot settings that will contain B stage thermosetting resin become C stage thermosetting resin; Then passivation part 12b is carried out the etching thinning, perhaps with polishing mode with its planarization or coplineization.Through after the coplineization, at this moment, the surface of its upper surface that comes out of passivation part 12b and insulating barrier 14 is a copline, and passivation part 12b can not protrude from the surface of insulating barrier 14 in fact.Subsequent step after the coplineization is then with extremely person shown in Figure 10, therefore no longer repetition of Fig. 6.
Compared to prior art, the advantage below the present invention provides at least: for example
(1) formed taper metal bump structure 12 on the substrate 10; Be to utilize modes such as plating, etching or mould printing to form; So can excellent engaging force be arranged with Copper Foil; In addition, the taper metal bump structure 12 that utilizes modes such as plating, etching to form also provides better thermal conductivity, makes circuit board possess better heat-sinking capability, usefulness and confidence level.
(2) utilize thick metal layers 15 to carry out pressing; The most advanced and sophisticated position 12a that pushes taper metal bump structure 12 insulation-piercing layers 14 and expose; And carry out whole plane etching thinning,, give planarization or coplineization perhaps with polishing mode; Utilize semi-additive process to form the fine rule road then, make patterned circuit 24 have high-reliability and high density.
The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. the manufacture method of a circuit board includes:
Provide one have a taper metal bump structure substrate;
Make this substrate and an insulating barrier pressing, this taper metal bump structure pierces through this insulating barrier, and exposes a most advanced and sophisticated position;
Pressing one metal level is squeezed this position, tip, forms a passivation part;
Carry out a flatening process, remove this passivation part of this metal level and part, the upper surface that makes this passivation part of this surface of insulating layer and exposure is a copline;
On this copline, form a conductive layer, and contact this passivation part;
On this conductive layer, form photoresist and carve the agent pattern;
Carry out an electroplating technology, on this conductive layer that exposes, to form electrodeposited coating;
Remove this photoresist and carve the agent pattern; And
Erosion removes this conductive layer of part that exposes.
2. the manufacture method of circuit board according to claim 1, wherein this taper metal bump structure be utilize electroplate, etching mode forms.
3. the manufacture method of circuit board according to claim 1, wherein this taper metal bump structure is to utilize the mould printing mode to form.
4. the manufacture method of circuit board according to claim 1, wherein this metal level of planarization comprises etching thinning mode or polishing mode.
5. the manufacture method of circuit board according to claim 1, wherein this conductive layer is to utilize galvanoplastic, physical vaporous deposition or sputtering method to form.
6. the manufacture method of a circuit board includes:
Provide one have a taper metal bump structure substrate;
Make this substrate and an insulating barrier pressing, this taper metal bump structure pierces through this insulating barrier, and exposes a most advanced and sophisticated position;
Should be pressed into a passivation part in the position, tip with a steel plate mould;
Carry out a flatening process, remove this passivation part of part, the upper surface that makes this passivation part of this surface of insulating layer and exposure is a copline;
On this copline, form a conductive layer, and contact this passivation part;
On this conductive layer, form photoresist and carve the agent pattern;
Carry out an electroplating technology, on this conductive layer that exposes, to form electrodeposited coating;
Remove this photoresist and carve the agent pattern; And
Erosion removes this conductive layer of part that exposes.
7. like the manufacture method of the said circuit board of claim 6, wherein this taper metal bump structure is to utilize plating, etching mode to form.
8. like the manufacture method of the said circuit board of claim 6, wherein this taper metal bump structure is to utilize the mould printing mode to form.
9. like the manufacture method of the said circuit board of claim 6, wherein this conductive layer is to utilize galvanoplastic, physical vaporous deposition or sputtering method to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910137583A CN101888748B (en) | 2009-05-14 | 2009-05-14 | Manufacturing method of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910137583A CN101888748B (en) | 2009-05-14 | 2009-05-14 | Manufacturing method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101888748A CN101888748A (en) | 2010-11-17 |
| CN101888748B true CN101888748B (en) | 2012-09-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910137583A Active CN101888748B (en) | 2009-05-14 | 2009-05-14 | Manufacturing method of circuit board |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832138A (en) * | 2011-06-15 | 2012-12-19 | 景硕科技股份有限公司 | Method for forming packaging substrate with ultrathin seed layer |
| KR102384863B1 (en) * | 2015-09-09 | 2022-04-08 | 삼성전자주식회사 | Semiconductor chip package and method of manufacturing the same |
| CN110913571A (en) * | 2019-12-05 | 2020-03-24 | 深圳市友泰实业有限公司 | Novel magnetically attractable circuit board and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1053785C (en) * | 1993-04-16 | 2000-06-21 | 株式会社东芝 | Circuit elements and manufacture of same |
| JP2004193520A (en) * | 2002-12-13 | 2004-07-08 | Sumitomo Bakelite Co Ltd | Manufacturing method of printed circuit board |
-
2009
- 2009-05-14 CN CN200910137583A patent/CN101888748B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1053785C (en) * | 1993-04-16 | 2000-06-21 | 株式会社东芝 | Circuit elements and manufacture of same |
| JP2004193520A (en) * | 2002-12-13 | 2004-07-08 | Sumitomo Bakelite Co Ltd | Manufacturing method of printed circuit board |
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| Publication number | Publication date |
|---|---|
| CN101888748A (en) | 2010-11-17 |
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