CN101874272B - 用于提高电子电路中成品率的方法和设备 - Google Patents

用于提高电子电路中成品率的方法和设备 Download PDF

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Publication number
CN101874272B
CN101874272B CN2008801175383A CN200880117538A CN101874272B CN 101874272 B CN101874272 B CN 101874272B CN 2008801175383 A CN2008801175383 A CN 2008801175383A CN 200880117538 A CN200880117538 A CN 200880117538A CN 101874272 B CN101874272 B CN 101874272B
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CN
China
Prior art keywords
circuit
voltage level
weak
memory
partition
Prior art date
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Expired - Fee Related
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CN2008801175383A
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English (en)
Chinese (zh)
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CN101874272A (zh
Inventor
R·B·戴尔
R·A·柯勒
R·J·麦克帕特兰德
范海光
W·E·沃纳
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Agere Systems LLC
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Agere Systems LLC
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Publication of CN101874272A publication Critical patent/CN101874272A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Power Sources (AREA)
CN2008801175383A 2008-01-30 2008-01-30 用于提高电子电路中成品率的方法和设备 Expired - Fee Related CN101874272B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2008/052454 WO2009096957A1 (en) 2008-01-30 2008-01-30 Method and apparatus for increasing yeild in an electronic circuit

Publications (2)

Publication Number Publication Date
CN101874272A CN101874272A (zh) 2010-10-27
CN101874272B true CN101874272B (zh) 2013-08-14

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CN2008801175383A Expired - Fee Related CN101874272B (zh) 2008-01-30 2008-01-30 用于提高电子电路中成品率的方法和设备

Country Status (7)

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US (1) US7940594B2 (enExample)
EP (1) EP2240936A1 (enExample)
JP (1) JP2011511395A (enExample)
KR (1) KR20100121475A (enExample)
CN (1) CN101874272B (enExample)
TW (1) TWI479500B (enExample)
WO (1) WO2009096957A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2240936A1 (en) 2008-01-30 2010-10-20 Agere Systems, Inc. Method and apparatus for increasing yeild in an electronic circuit
CN101682325B (zh) * 2008-02-27 2013-06-05 松下电器产业株式会社 半导体集成电路以及包括该半导体集成电路的各种装置
DE202009007395U1 (de) * 2009-05-19 2009-08-20 Balluff Gmbh Stromversorgungs-Anschlussvorrichtung für ein parametrierbares elektrisches Gerät
CN102468650B (zh) 2010-11-18 2015-07-08 英业达股份有限公司 多电源供电装置
TWI492471B (zh) * 2010-12-20 2015-07-11 英業達股份有限公司 多電源供電裝置
US9786385B2 (en) * 2015-03-02 2017-10-10 Oracle International Corporation Memory power selection using local voltage regulators
US10664035B2 (en) * 2017-08-31 2020-05-26 Qualcomm Incorporated Reconfigurable power delivery networks

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1414563A (zh) * 2001-10-23 2003-04-30 株式会社日立制作所 半导体器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214122A (ja) * 1996-11-27 1998-08-11 Yamaha Corp 降圧回路および集積回路
JPH10261946A (ja) 1997-03-19 1998-09-29 Mitsubishi Electric Corp 半導体集積回路
US20030076729A1 (en) * 2001-10-24 2003-04-24 Fetzer Eric S. Method and apparatus for reducing average power and increasing cache performance by modulating power supplies
KR100488544B1 (ko) * 2002-11-11 2005-05-11 삼성전자주식회사 반도체 메모리장치의 블록선택정보를 이용한 뱅크전압제어장치 및 그 제어방법
US7456525B2 (en) * 2004-07-09 2008-11-25 Honeywell International Inc. Multi-output power supply device for power sequencing
JP2006228277A (ja) * 2005-02-15 2006-08-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7236396B2 (en) * 2005-06-30 2007-06-26 Texas Instruments Incorporated Area efficient implementation of small blocks in an SRAM array
ITVA20060081A1 (it) * 2006-12-22 2008-06-23 St Microelectronics Srl Riduzione del consumo da parte di un sistema elettronico integrato comprendente distinte risorse statiche ad accesso casuale di memorizzazione dati
JP2008251603A (ja) * 2007-03-29 2008-10-16 Toshiba Corp 半導体集積回路
EP2240936A1 (en) 2008-01-30 2010-10-20 Agere Systems, Inc. Method and apparatus for increasing yeild in an electronic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1414563A (zh) * 2001-10-23 2003-04-30 株式会社日立制作所 半导体器件

Also Published As

Publication number Publication date
TWI479500B (zh) 2015-04-01
US20100238751A1 (en) 2010-09-23
WO2009096957A1 (en) 2009-08-06
KR20100121475A (ko) 2010-11-17
US7940594B2 (en) 2011-05-10
EP2240936A1 (en) 2010-10-20
CN101874272A (zh) 2010-10-27
JP2011511395A (ja) 2011-04-07
TW200933642A (en) 2009-08-01

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