CN101866873A - Slot filling method in multilayer integrated circuit - Google Patents
Slot filling method in multilayer integrated circuit Download PDFInfo
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- CN101866873A CN101866873A CN200910057076A CN200910057076A CN101866873A CN 101866873 A CN101866873 A CN 101866873A CN 200910057076 A CN200910057076 A CN 200910057076A CN 200910057076 A CN200910057076 A CN 200910057076A CN 101866873 A CN101866873 A CN 101866873A
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Abstract
The invention discloses a slot filling method in a multilayer integrated circuit. In the method, slots are etched on the surface of a silicone wafer, and a layer of silicon dioxide is grown by thermal oxidation, and then the following steps are carried out: firstly, depositing a layer of silicon dioxide on the surface of the silicon wafer with the slots, wherein the layer of the silicon dioxide is a laying layer; secondly, depositing a layer of silicon dioxide mixed with p type or n type impurities on the laying layer, wherein the silicon dioxide mixed with the impurities fills the slots and is the material of the interlayer media of the first layer; and thirdly, carrying out planarization treatment on the silicon dioxide on the surface of the silicon wafer by a chemical mechanical polishing process until the required thickness of the interlayer media of the first layer is met. In the invention, the filling of the slots and the preparation of ILD-1 are skillfully integrated, and the material of the ILD-1 is determined as the silicon dioxide mixed with the impurities simultaneously. The silicon dioxide mixed with the impurities has good fluidity, and therefore, the requirements for filling deep slots with different widths can be completely met.
Description
Technical field
The present invention relates to a kind of manufacturing process of semiconductor integrated circuit.
Background technology
Modern semiconductor integrated circuit all adopts sandwich construction (at least two layers), and the below is a silicon, and one or more layers metal is arranged on the silicon, all has inter-level dielectric (ILD) between each layer metal and between ground floor metal and the silicon.
In the manufacturing process of the silicon of below, often need to use spacer medium (for example silicon dioxide) filling groove.Shallow-trench isolation (STI) technology is exactly a kind of fill method of common groove, but it is applicable to shallow trench (degree of depth is below 1 μ m).For deep trench (degree of depth at 1 μ m between the 10 μ m), adopt the method for repeatedly filling usually, its concrete steps are as follows:
State during beginning, silicon chip surface have just etched groove 10, and have the silicon chip surface thermal oxide growth layer of silicon dioxide (not shown) of groove 10, the thickness of this one deck silicon dioxide 50～
Between.This step is called hot oxygen reparation, and in the semiconductor integrated circuit manufacturing process, hot oxygen reparation is a necessary procedure behind the etching groove, is used to repair the surface state of the silicon behind the etching groove.
The 1st step saw also Fig. 1 a, had the silicon chip surface deposit layer of silicon dioxide of groove 10, and this one deck silicon dioxide is laying 21, thickness 500～
Between, be used for improving the adhesiveness between silicon and the trench filling (for example silicon dioxide).This step is an optional step, can omit.
The 2nd step saw also Fig. 1 b, in silicon chip surface deposit layer of silicon dioxide again, thickness 5000～
Between, this is that groove 10 is carried out first packed layer 22 of filling for the first time.First packed layer 22 combines together with laying 21, and therefore boundary between the two is represented by dotted lines.
The 3rd step saw also Fig. 1 c, adopted dry etch process to anti-carve silicon dioxide (comprising first packed layer 22 and laying 21), until the upper surface that exposes groove 10 sidewalls (silicon).This moment, also residually there was silicon dioxide the bottom of groove 10 and side, and the thickness of residual fraction is not more than
After anti-carving, can also carry out the cleaning of silicon chip surface in this step.
The 4th step saw also Fig. 1 d, in silicon chip surface deposit layer of silicon dioxide again, thickness 5000～
Between, this is that groove 10 is carried out second packed layer 23 of filling for the second time.Second packed layer 23 combines together with packed layer 22, laying 21 for the first time, so the boundary between the three is represented by dotted lines.It should be noted that for deep trench this step tends in the inner cavity 30 that forms of groove.
The 5th step, see also Fig. 1 e or Fig. 1 f, with chemical mechanical milling tech silicon chip surface is carried out planarization, also can after cmp, increase dry etch process and anti-carve silicon dioxide (second packed layer 23), until the upper surface that exposes groove 10 sidewalls.
Two kinds of situations may appear in this moment, and for the less groove 10 of some width, cavity 30 is completely enclosed within below the silicon chip surface (upper surfaces of groove 10 sidewalls), has filling effect preferably, shown in Fig. 1 e.And for the bigger groove 10 of some width, polish or when anti-carving cavity 30 got through, promptly cavity 30 has passage to be connected on the silicon chip surface, filling effect is relatively poor, shown in Fig. 1 f.
The fill method of the deep trench shown in above-mentioned five steps, by the adjusting process parameter, can guarantee that the groove of a certain concrete width is had filling effect preferably, but the different in width groove is always had inconsistent filling capacity, and this has just brought restriction to the design and the manufacturing process of semiconductor product.In the common CMOS manufacturing process, must comprise one or more lithography steps (technologies such as for example etching polysilicon gate, lightly doped drain inject, source leakage injection, local interlinkage) after the step of trench fill, lithography step need cover one deck photoresist at silicon chip surface.In case the filling of groove is not thorough, the cavity of groove inside is in communication with the outside, and photoresist will remain in cavity or the structure that is in communication with the outside of cavity and can't remove, and residual photoresist can bring pollution to subsequent technique.
Because the filling of groove all is the silicon that occurs in the below of multilevel integration, therefore must have the step of formation inter-level dielectric the filling of groove after, the ground floor inter-level dielectric is commonly referred to ILD-1 between ground floor metal and silicon.
The concrete steps of preparation ILD-1 are at present:
In the 1st step, in silicon chip surface deposit layer of silicon dioxide, this one deck silicon dioxide is laying;
The 2nd step, deposit layer of silicon dioxide again on laying, this one deck silicon dioxide is the material of ILD-1;
The 3rd step, with chemical mechanical milling tech the ILD-1 of silicon chip surface is carried out planarization, also can after cmp, increase dry etch process and anti-carve silicon dioxide, reach preset thickness until the ILD-1 layer.
Summary of the invention
Technical problem to be solved by this invention provides the fill method of groove in a kind of multilevel integration, and this method all has good filling effect for the groove of different in width.
For solving the problems of the technologies described above, the fill method of groove is right after after silicon chip surface etches groove and thermal oxide growth layer of silicon dioxide and carries out following steps in the multilevel integration of the present invention:
The 1st step had the silicon chip surface deposit layer of silicon dioxide of groove, and this one deck silicon dioxide is laying;
In the 2nd step, deposit one deck is doped with the silicon dioxide of p type or n type impurity again on laying, and described have doped silica both to fill described groove, is again the material of ground floor inter-level dielectric;
In the 3rd step, with chemical mechanical milling tech the silicon dioxide of silicon chip surface is carried out planarization, until reaching the desired thickness of ground floor inter-level dielectric.
The present invention unites two into one the filling of groove and the preparation of ILD-1 dexterously, simultaneously the material of ILD-1 is defined as being doped with the silicon dioxide of p type impurity (for example boron) or n type impurity (for example phosphorus, arsenic, antimony).Have extraordinary flowability owing to be doped with the silicon dioxide of impurity, therefore can satisfy the deep trench of different in width fully and fill requirement.
Description of drawings
Fig. 1 a～Fig. 1 f be among the 5th step of present LCTVS pipe manufacturing method filling groove respectively go on foot schematic diagram;
Fig. 2 a～Fig. 2 c be groove in the multilevel integration of the present invention fill method respectively go on foot schematic diagram.
Description of reference numerals among the figure:
10 is groove; 21 is laying; 22 is first packed layer; 23 is second packed layer; 30 is the cavity; 41 is laying; 42 is ILD-1.
Embodiment
The fill method of groove comprises the steps: in the multilevel integration of the present invention
State during beginning, silicon chip surface have just etched groove 10, and have the silicon chip surface thermal oxide growth layer of silicon dioxide (not shown) of groove 10, the thickness of this one deck silicon dioxide 50～
Between.
The 1st step saw also Fig. 2 a, had the silicon chip surface deposit layer of silicon dioxide of groove 10, and this one deck silicon dioxide is laying 41, the p type that undopes or n type impurity, thickness 500～
Between.
The 2nd step saw also Fig. 2 b, silicon chip surface again deposit one deck be doped with the silicon dioxide of p type or n type impurity, thickness 5000～
Between, this one deck silicon dioxide is filled groove 10 on the one hand, on the other hand as the material of ground floor inter-level dielectric 42.The material of ground floor inter-level dielectric 42 and laying 21 combine together, and therefore boundary between the two is represented by dotted lines.It should be noted that for deep trench this step tends in the inner cavity 30 that forms of groove.
The 3rd step, see also Fig. 2 c, with chemical mechanical milling tech silicon chip surface is carried out planarization, also can after cmp, increase dry etch process and anti-carve silicon dioxide (material of ground floor inter-level dielectric 42), meet the requirements of thickness until ground floor inter-level dielectric 42.For example, the ILD-1 layer is predefined for
Then no matter adopt cmp, or cmp adds dry etching, it a little is exactly that silicon dioxide layer on the side wall upper surface of groove 10 reaches that final stopping to be detected
Because ground floor inter-level dielectric 42 is doped with impurity, has extraordinary flowability, no matter therefore for the groove 10 of any width, cavity 30 can both guarantee to be completely enclosed within below the silicon chip surface (upper surfaces of groove 10 sidewalls).
The present invention will be described in detail with the manufacturing process of a concrete device below.
Transient state (transition, moment) voltage suppressor spare (TVS, Transient Voltage Suppressor) is a kind of diode, is connected in parallel on and realizes the circuit overvoltage protection in the circuit.It is a kind of of TVS pipe that low capacitor transient stage voltage suppresses (LCTVS, low-capacitance Transient Voltage Suppressor), and the classical production process of LCTVS pipe is:
The 1st step, make mark at the ad-hoc location of silicon chip (wafer, wafer), for example etch groove etc., these marks are as the usefulness of the aligning of subsequent process steps.
The 2nd step, adopt ion implantation technology in silicon chip, to form a buried regions, the impurity of injection can be p type or n type.
The 3rd step is in silicon chip surface deposit one deck epitaxial loayer (p type or n type monocrystalline silicon are with the type opposite of buried regions impurity).
The 4th step, in epitaxial loayer, carry out ion and inject, the impurity of injection is identical with the type of epitaxial loayer impurity, is used for adjusting the impurity concentration in the epitaxial loayer, in the p district of formation LCTVS pipe or the n district one.
In the 5th step, (if arts demand, it is inner to comprise that also LCTVS manages) etches groove and carries out hot oxygen reparation around the LCTVS pipe, and filled media material in groove (for example silicon dioxide) is as the usefulness of isolation.
The 6th step, in epitaxial loayer, carry out the source and leak to inject (highly doped ion injects), form the p district of LCTVS pipe or in the n district another.
The 7th step is in silicon chip surface deposit layer of silicon dioxide, as ILD-1.The planarization step that can also comprise cmp after the step that can also comprise deposit laying silicon dioxide before the deposit, deposit.
In the 5th step of said method,, all adopt the method for repeatedly filling at present as stated in the Background Art, but but always there is the inconsistent defective of filling capacity in the different in width groove for the filling step of groove.As adopt the fill method of groove of the present invention, and then keep～the 4 step of the 1st step constant ,～the 7 step of the 5th step is changed into:
The 5th ' step, in epitaxial loayer, carry out the source and leak to inject (highly doped ion injects), form the p district of LCTVS pipe or in the n district another.
The 6th ' step, (if arts demand, it is inner to comprise that also LCTVS manages) etches groove and carries out hot oxygen reparation around the LCTVS pipe.
The 7th ' step is doped with the silicon dioxide of p type or n type impurity at silicon chip surface deposit one deck, and as ILD-1, this one deck ILD-1 has the effect of filling groove concurrently.The planarization step that also comprises cmp after the step that also comprises deposit laying silicon dioxide before the deposit, deposit.
It should be noted that the method for the invention, must be followed by the depositing step that carries out ILD-1 after etching groove step (comprising hot oxygen reparation) is finished.With regard to needing original step (technologies such as for example etching polysilicon gate, lightly doped drain inject, source leakage injection, local interlinkage) between these two steps was all changed into before the etching groove step and carrying out like this.
Claims (5)
1. the fill method of groove in the multilevel integration is characterized in that described method is right after carries out following steps after silicon chip surface etches groove and thermal oxide growth layer of silicon dioxide:
The 1st step had the silicon chip surface deposit layer of silicon dioxide of groove, and this one deck silicon dioxide is laying;
In the 2nd step, deposit one deck is doped with the silicon dioxide of p type or n type impurity again on laying, and described have doped silica both to fill described groove, is again the material of ground floor inter-level dielectric;
In the 3rd step, with chemical mechanical milling tech the silicon dioxide of silicon chip surface is carried out planarization, until reaching the desired thickness of ground floor inter-level dielectric.
2. the fill method of groove is characterized in that in the multilevel integration according to claim 1, the thickness of the silicon dioxide of described thermal oxide growth is 50～
3. the fill method of groove is characterized in that in the multilevel integration according to claim 1, and described method is in the 1st step, the thickness of deposit silicon dioxide is 500～
4. the fill method of groove is characterized in that in the multilevel integration according to claim 1, and described method is in the 2nd step, the thickness that is deposited with doped silica is 5000～
5. the fill method of groove is characterized in that in the multilevel integration according to claim 1, and described method also comprises the silicon dioxide that anti-carves silicon chip surface with dry etch process, until reaching the desired thickness of ground floor inter-level dielectric in the 3rd step.
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| CN2009100570767A CN101866873B (en) | 2009-04-16 | 2009-04-16 | Slot filling method in multilayer integrated circuit |
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| CN2009100570767A CN101866873B (en) | 2009-04-16 | 2009-04-16 | Slot filling method in multilayer integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112802755A (en) * | 2021-02-01 | 2021-05-14 | 深圳吉华微特电子有限公司 | Method for manufacturing plane and groove combined field effect semiconductor device |
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| TW444333B (en) * | 1998-07-02 | 2001-07-01 | United Microelectronics Corp | Method for forming corner rounding of shallow trench isolation |
| US7125815B2 (en) * | 2003-07-07 | 2006-10-24 | Micron Technology, Inc. | Methods of forming a phosphorous doped silicon dioxide comprising layer |
| CN101246842A (en) * | 2007-02-16 | 2008-08-20 | 中微半导体设备(上海)有限公司 | Method for forming shallow plough groove isolation area in semiconductor integrated circuit technique |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112802755A (en) * | 2021-02-01 | 2021-05-14 | 深圳吉华微特电子有限公司 | Method for manufacturing plane and groove combined field effect semiconductor device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131219 |
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Effective date of registration: 20131219 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |