CN112802755A - Method for manufacturing plane and groove combined field effect semiconductor device - Google Patents
Method for manufacturing plane and groove combined field effect semiconductor device Download PDFInfo
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- CN112802755A CN112802755A CN202110137004.4A CN202110137004A CN112802755A CN 112802755 A CN112802755 A CN 112802755A CN 202110137004 A CN202110137004 A CN 202110137004A CN 112802755 A CN112802755 A CN 112802755A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 75
- 238000005530 etching Methods 0.000 claims abstract description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 238000000151 deposition Methods 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000002513 implantation Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a planar and groove combined field effect semiconductor device, which comprises the following steps: step S1: depositing silicon oxide on the surface of the N-type silicon wafer and carrying out photoetching; step S2: removing part of the silicon oxide to form a groove etching window, and etching the groove; step S3: removing silicon oxide on the surface of the N-type silicon wafer, oxidizing the surface of the N-type silicon wafer to form silicon oxide, depositing a layer of silicon oxide on the silicon oxide, and depositing polycrystalline silicon on the upper layer of silicon oxide; step S4: etching the polycrystalline silicon in the step S3 and two layers of silicon oxide below the polycrystalline silicon, performing gate oxidation, depositing the polycrystalline silicon, and depositing silicon oxide on the polycrystalline silicon; step S5: photoetching and etching the polysilicon, etching the silicon oxide, and etching a P-injection window; step S6: performing P-implantation and junction pushing; step S7: and etching an N + injection window and carrying out N + injection and annealing.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a planar and groove combined field effect semiconductor device.
[ background of the invention ]
The field effect semiconductor device with the groove structure and the plane structure is widely applied to the technical field of power semiconductor devices, and the primitive cell size of the plane structure is large, and the on-resistance is high; at present, a trench structure is generally adopted.
The cell density of the trench structure is increased, the on-resistance per unit area is low, but the gate charge and the reverse transfer capacitance are large, and the low on-resistance and the low gate charge and the low reverse transfer capacitance are required in part of applications.
Therefore, how to solve the product parameters of the prior art, namely the problem that the field effect semiconductor device with the trench structure is difficult to realize low gate charge and reverse transmission capacitance, becomes the key point to be solved.
[ summary of the invention ]
In order to overcome the technical problems, the invention provides a manufacturing method of a planar and groove combined field effect semiconductor device.
The invention provides a method for manufacturing a planar and groove combined field effect semiconductor device, which comprises the following steps:
step S1: depositing silicon oxide on the surface of the N-type silicon wafer and carrying out photoetching;
step S2: removing part of the silicon oxide to form a groove etching window, and etching the groove;
step S3: removing silicon oxide on the surface of the N-type silicon wafer, oxidizing the surface of the N-type silicon wafer to form silicon oxide, depositing a layer of silicon oxide on the silicon oxide, and depositing polycrystalline silicon on the upper layer of silicon oxide;
step S4: etching the polycrystalline silicon in the step S3 and two layers of silicon oxide below the polycrystalline silicon, performing gate oxidation, depositing the polycrystalline silicon, and depositing silicon oxide on the polycrystalline silicon;
step S5: photoetching and etching the polysilicon, etching the silicon oxide, and etching a P-injection window;
step S6: performing P-implantation and junction pushing;
step S7: etching an N + injection window and carrying out N + injection and annealing;
step S8: carrying out polycrystal CUT photoetching, etching silicon oxide on the polycrystalline silicon, and then etching the polycrystalline silicon and etching the polycrystalline silicon;
step S9: depositing silicon oxide, and performing spacer etching;
step S10: depositing silicon oxide, etching the silicon oxide on the surface of the N-type silicon wafer of the source contact hole, and then etching the N-type silicon wafer;
step S11: carrying out P + fire injection and annealing;
step S12: and carrying out metal deposition to form a source electrode.
Preferably, in step S2, an anisotropic dry etching process is used to remove a portion of the silicon oxide.
Preferably, in step S3, silicon oxide is formed on the surface of the N-type silicon wafer by thermal oxidation.
Preferably, in step S10, the etching groove depth of the N-type silicon wafer is 0.3-0.5 um.
Preferably, in step S12, the source electrode is 4-6um thick.
Preferably, in step S3, an isotropic wet etching process is used to remove the silicon oxide on the surface of the N-type silicon wafer.
Compared with the prior art, the manufacturing method of the plane and groove combined field effect semiconductor device has the following advantages:
the invention realizes lower on-resistance through the groove structure, reduces gate charge and reverse transmission capacitance through the plane grid and the polycrystalline separation structure, simultaneously reduces the primitive cell area by adopting a groove carving mode of the contact hole above the groove to facilitate the realization of lower on-resistance, ensures lower gate charge and reverse transmission capacitance through realizing low on-resistance, and is beneficial to meeting the further requirements of enterprises on field effect semiconductors.
[ description of the drawings ]
FIG. 1 is a detailed flowchart of steps S1-S6 of the method for fabricating a planar and trench combined field effect semiconductor device according to the present invention.
Fig. 2 is a detailed flowchart of steps S7-S12 of the method for manufacturing a planar and trench combined field effect semiconductor device according to the present invention.
Fig. 3-12 are schematic manufacturing flow diagrams of steps S1-S12 of the method for manufacturing a planar and trench combined field effect semiconductor device according to the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1-12, the present invention provides a method for fabricating a planar and trench combined field effect semiconductor device, comprising the steps of:
step S1: depositing silicon oxide on the surface of the N-type silicon wafer and carrying out photoetching;
step S2: and removing part of the silicon oxide to form a groove etching window, and etching the groove.
Specifically, silicon oxide deposited on the surface of an N-type silicon wafer is used as a mask layer for groove etching, during photoetching, an anisotropic dry etching process is adopted to remove part of the silicon oxide to form a groove etching window, and groove etching is carried out according to actually determined etching depth.
Step S3: removing silicon oxide on the surface of the N-type silicon wafer, oxidizing the surface of the N-type silicon wafer to form silicon oxide, depositing a layer of silicon oxide on the silicon oxide, and depositing polycrystalline silicon on the upper layer of silicon oxide.
Specifically, removing silicon oxide on the surface of the N-type silicon wafer by adopting an isotropic wet etching process, performing sacrificial oxidation, removing etching damage on the surface of the groove by adopting a wet process, forming a layer of silicon oxide on the side wall of the groove and the plane of the N-type silicon wafer by adopting a thermal oxidation mode, and depositing a layer of silicon oxide on the layer of silicon oxide; and depositing source polysilicon on the upper layer of silicon oxide.
Step S4: and etching the polycrystalline silicon in the step S3 and the two layers of silicon oxide below the polycrystalline silicon, carrying out gate oxidation, depositing the polycrystalline silicon, and depositing silicon oxide on the polycrystalline silicon.
Specifically, a dry etching process is adopted to etch polycrystalline silicon on a silicon plane to be below an interface of the N-type silicon wafer, and a dry etching process is adopted to etch silicon oxide on the surface of the N-type silicon wafer and a layer of silicon oxide positioned between the polycrystalline silicon and the silicon oxide.
Step S5: photoetching and etching the polysilicon, etching the silicon oxide, and etching a P-injection window;
step S6: p-implantation and junction push-off are performed.
Specifically, a dry etching process is adopted to etch the polysilicon, a dry etching process is adopted to etch the silicon oxide, and a window etched by the polysilicon is utilized to perform P-injection and junction pushing.
Step S7: etching an N + injection window and carrying out N + injection and annealing;
step S8: and carrying out polycrystal CUT photoetching, etching silicon oxide on the polycrystalline silicon, then etching the polycrystalline silicon and etching the polycrystalline silicon.
Specifically, the silicon oxide on the polysilicon is etched by a dry etching process until the polysilicon is etched to the silicon oxide interface by the dry etching process. Wherein the polycrystalline CUT is polycrystalline etching.
Step S9: depositing silicon oxide and performing spacer etching.
The step is used for etching the residual or newly generated silicon oxide on the surface of the N-type silicon chip and is realized by adopting an anisotropic dry etching process. Wherein the spacer etching is side wall etching.
Step S10: and depositing silicon oxide, etching the silicon oxide on the surface of the N-type silicon wafer with the source contact hole, and then etching the N-type silicon wafer.
Specifically, depositing silicon oxide to isolate the dielectric layer from the electrode layer, and etching the silicon oxide on the surface of the N-type silicon wafer of the source contact hole and the N-type silicon wafer below the silicon oxide by adopting an anisotropic dry etching process.
Preferably, in step S10, the etching trench depth of the N-type silicon wafer is 0.3-0.5um, which is greater than the P-well depth.
Step S11: carrying out P + fire injection and annealing;
step S12: and carrying out metal deposition to form a source electrode.
Specifically, in step S12, a metal layer, i.e., a source electrode, is deposited to a thickness of 4-6 um.
Compared with the prior art, the manufacturing method of the plane and groove combined field effect semiconductor device has the following advantages:
the invention realizes lower on-resistance through the groove structure, reduces gate charge and reverse transmission capacitance through the plane grid and the polycrystalline separation structure, simultaneously reduces the primitive cell area by adopting a groove carving mode of the contact hole above the groove to facilitate the realization of lower on-resistance, ensures lower gate charge and reverse transmission capacitance through realizing low on-resistance, and is beneficial to meeting the further requirements of enterprises on field effect semiconductors.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and any modifications, equivalents, improvements, etc. made within the spirit of the present invention should be included in the scope of the present invention.
Claims (6)
1. A method for manufacturing a planar and trench combined field effect semiconductor device is characterized in that: the manufacturing method of the plane and groove combined field effect semiconductor device comprises the following steps:
step S1: depositing silicon oxide on the surface of the N-type silicon wafer and carrying out photoetching;
step S2: removing part of the silicon oxide to form a groove etching window, and etching the groove;
step S3: removing silicon oxide on the surface of the N-type silicon wafer, oxidizing the surface of the N-type silicon wafer to form silicon oxide, depositing a layer of silicon oxide on the silicon oxide, and depositing polycrystalline silicon on the upper layer of silicon oxide;
step S4: etching the polycrystalline silicon in the step S3 and two layers of silicon oxide below the polycrystalline silicon, performing gate oxidation, depositing the polycrystalline silicon, and depositing silicon oxide on the polycrystalline silicon;
step S5: photoetching and etching the polysilicon, etching the silicon oxide, and etching a P-injection window;
step S6: performing P-implantation and junction pushing;
step S7: etching an N + injection window and carrying out N + injection and annealing;
step S8: carrying out polycrystal CUT photoetching, etching silicon oxide on the polycrystalline silicon, and then etching the polycrystalline silicon and etching the polycrystalline silicon;
step S9: depositing silicon oxide, and performing spacer etching;
step S10: depositing silicon oxide, etching the silicon oxide on the surface of the N-type silicon wafer of the source contact hole, and then etching the N-type silicon wafer;
step S11: carrying out P + fire injection and annealing;
step S12: and carrying out metal deposition to form a source electrode.
2. A method of fabricating a combined planar and trench field effect semiconductor device as claimed in claim 1 wherein: in step S2, an anisotropic dry etching process is used to remove a portion of the silicon oxide.
3. A method of fabricating a combined planar and trench field effect semiconductor device as claimed in claim 1 wherein: in step S3, silicon oxide is formed on the surface of the N-type silicon wafer by thermal oxidation.
4. A method of fabricating a combined planar and trench field effect semiconductor device as claimed in claim 1 wherein: in step S10, the etching depth of the N-type silicon wafer is 0.3-0.5 um.
5. A method of fabricating a combined planar and trench field effect semiconductor device as claimed in claim 1 wherein: in step S12, the source electrode is 4-6um thick.
6. A method of fabricating a combined planar and trench field effect semiconductor device as claimed in claim 1 wherein: in step S3, an isotropic wet etching process is used to remove the silicon oxide on the surface of the N-type silicon wafer.
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| CN202110137004.4A CN112802755A (en) | 2021-02-01 | 2021-02-01 | Method for manufacturing plane and groove combined field effect semiconductor device |
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| CN202110137004.4A CN112802755A (en) | 2021-02-01 | 2021-02-01 | Method for manufacturing plane and groove combined field effect semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101529589A (en) * | 2006-07-28 | 2009-09-09 | 万国半导体股份有限公司 | Bottom source ldmosfet structure and method |
| CN101866873A (en) * | 2009-04-16 | 2010-10-20 | 上海华虹Nec电子有限公司 | Slot filling method in multilayer integrated circuit |
| US20130341689A1 (en) * | 2009-12-21 | 2013-12-26 | Alpha & Omega Semiconductor Incorporated | Method of forming a self-aligned charge balanced power dmos |
| US20150357461A1 (en) * | 2014-06-09 | 2015-12-10 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
| US20180166540A1 (en) * | 2016-12-13 | 2018-06-14 | Hyundai Motor Company | Semiconductor device and method manufacturing the same |
-
2021
- 2021-02-01 CN CN202110137004.4A patent/CN112802755A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101529589A (en) * | 2006-07-28 | 2009-09-09 | 万国半导体股份有限公司 | Bottom source ldmosfet structure and method |
| CN101866873A (en) * | 2009-04-16 | 2010-10-20 | 上海华虹Nec电子有限公司 | Slot filling method in multilayer integrated circuit |
| US20130341689A1 (en) * | 2009-12-21 | 2013-12-26 | Alpha & Omega Semiconductor Incorporated | Method of forming a self-aligned charge balanced power dmos |
| CN104485359A (en) * | 2009-12-21 | 2015-04-01 | 万国半导体股份有限公司 | Method of forming a self-aligned charge balanced power dmos |
| US20150357461A1 (en) * | 2014-06-09 | 2015-12-10 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
| US20180166540A1 (en) * | 2016-12-13 | 2018-06-14 | Hyundai Motor Company | Semiconductor device and method manufacturing the same |
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