CN101866873B - Slot filling method in multilayer integrated circuit - Google Patents

Slot filling method in multilayer integrated circuit Download PDF

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CN101866873B
CN101866873B CN 200910057076 CN200910057076A CN101866873B CN 101866873 B CN101866873 B CN 101866873B CN 200910057076 CN200910057076 CN 200910057076 CN 200910057076 A CN200910057076 A CN 200910057076A CN 101866873 B CN101866873 B CN 101866873B
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layer
silicon dioxide
trench
step
filling
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CN 200910057076
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CN101866873A (en
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熊涛
罗啸
陈华伦
陈瑜
陈雄斌
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上海华虹Nec电子有限公司
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Abstract

The invention discloses a slot filling method in a multilayer integrated circuit. In the method, slots are etched on the surface of a silicone wafer, and a layer of silicon dioxide is grown by thermal oxidation, and then the following steps are carried out: firstly, depositing a layer of silicon dioxide on the surface of the silicon wafer with the slots, wherein the layer of the silicon dioxide is a laying layer; secondly, depositing a layer of silicon dioxide mixed with p type or n type impurities on the laying layer, wherein the silicon dioxide mixed with the impurities fills the slots and is the material of the interlayer media of the first layer; and thirdly, carrying out planarization treatment on the silicon dioxide on the surface of the silicon wafer by a chemical mechanical polishing process until the required thickness of the interlayer media of the first layer is met. In the invention, the filling of the slots and the preparation of ILD-1 are skillfully integrated, and the material of the ILD-1 is determined as the silicon dioxide mixed with the impurities simultaneously. The silicon dioxide mixed with the impurities has good fluidity, and therefore, the requirements forfilling deep slots with different widths can be completely met.

Description

多层集成电路中沟槽的填充方法 Filling the trench multilayer integrated circuit

技术领域 FIELD

[0001 ] 本发明涉及一种半导体集成电路的制造工艺。 [0001] The present invention relates to a manufacturing process of a semiconductor integrated circuit. 背景技术 Background technique

[0002] 现代的半导体集成电路都采用多层结构(至少二层),最下方是硅,硅之上有一层或多层金属,各层金属之间以及第一层金属与硅之间都具有层间介质(ILD)。 [0002] Modern integrated circuits are semiconductor multi-layer structure (at least two layers), the bottom silicon, silicon on one or more layers of metal, having a first layer and between the layers between the metal and silicon metal The interlayer dielectric (ILD).

[0003] 最下方的硅的制造工艺中,经常需要使用隔离介质(例如二氧化硅)填充沟槽。 [0003] The manufacturing process of the lowermost silicon is often necessary to use separation medium (e.g., silica) filled trenches. 浅槽隔离(STI)工艺就是一种常见的沟槽的填充方法,但是其只适用于浅沟槽(深度在Iym以下)。 Shallow trench isolation (STI) process is a common method of filling the trench, but it only applies to shallow trench (depth Iym less). 对于深沟槽(深度在I μ m到10 μ m之间),通常采用多次填充的方法,其具体步骤如下: For deep trenches (depth between I μ m to 10 μ m), by methods generally multiple filling, the following steps:

[0004] 开始时的状态,硅片表面刚刻蚀出沟槽10,并在具有沟槽10的硅片表面热氧化生长一层二氧化硅(未图示),这一层二氧化硅的厚度在50〜1000 A之间。 [0004] The state at the start, just silicon surface etched groove 10, and a silicon wafer having a thermally oxidized surface layer of silicon dioxide grown trench 10 (not shown), this layer of silica thickness between 50~1000 A. 这一步称为热氧修复,在半导体集成电路制造工艺中,热氧修复是沟槽刻蚀后必不可少的步骤,用于修复沟槽刻蚀后的硅的表面状态。 This step is called hot fix oxygen, in the semiconductor integrated circuit manufacturing process, the thermal-oxidative repair trench etch is an essential step for the surface state of the silicon trench etch repaired.

[0005] 第I步,请参阅图la,在具有沟槽10的硅片表面淀积一层二氧化硅,这一层二氧化硅是衬垫层21,厚度在500〜5000 A之间,用来改善硅与沟槽填充物(例如二氧化硅)之间的粘附性。 [0005] Step I, see FIG La, a silicon wafer having a surface layer of silicon dioxide is deposited in the groove 10, which is the pad layer of silicon dioxide layer 21, a thickness of between 500~5000 A, to improve silicon and trench fill (e.g., silica) adhesion between. 这一步是可选步骤,可以省略。 This step is an optional step, you can be omitted.

[0006] 第2步,请参阅图lb,在硅片表面再淀积一层二氧化硅,厚度在5000〜30000 A之间,这是对沟槽10进行第一次填充的第一填充层22。 [0006] Step 2, see FIG LB, the silicon wafer surface and then depositing a layer of silicon dioxide thickness between 5000~30000 A, which is the first trench filling layer 10 is filled for the first time twenty two. 第一填充层22与衬垫层21融为一体,因此两者之间的界限以虚线表示。 First filling layer 22, the line between the pad shown in phantom and the integration layer 21.

[0007] 第3步,请参阅图lc,采用干法刻蚀工艺反刻二氧化硅(包括第一填充层22与衬垫层21),直至露出沟槽10侧壁的上表面(硅)。 [0007] step 3, see FIG. LC, a dry etching process using anti-engraved silica (filler layer comprises a first layer 22 and the pad 21) until the upper surface of the sidewall of the trench 10 (silicon) is exposed . 此时沟槽10的底部和侧面还残留有二氧化硅,残留部分的厚度不大于10000 A。 In this case bottom and sides of the trench 10 is also silica remains, the thickness of the residual portion is not greater than 10000 A. 这一步中在反刻后还可以进行硅片表面的清洗工作。 This step may also carry out the washing of the wafer surface after the anti-engraved.

[0008] 第4步,请参阅图ld,在硅片表面又淀积一层二氧化硅,厚度在5000〜30000 A之间,这是对沟槽10进行第二次填充的第二填充层23。 [0008] The first step 4, see FIG LD, and the silicon surface layer of silicon dioxide is deposited, a thickness of between 5000~30000 A, which is the second trench filling layer 10 is filled with a second twenty three. 第二填充层23与第一次填充层22、衬垫层21融为一体,因此三者之间的界限以虚线表示。 The second layer 23 is filled with the first filler layer 22, spacer layer 21 is integrated, thus the boundaries between the three shown in phantom. 需要注意的是,对于深沟槽来说,这一步往往会在沟槽内部形成空洞30。 It should be noted that, for the deep trench, this step will often form a cavity 30 inside the trench.

[0009] 第5步,请参阅图Ie或图If,以化学机械研磨工艺对硅片表面进行平坦化处理,也可以在化学机械研磨之后增加干法刻蚀工艺反刻二氧化硅(第二填充层23),直至露出沟槽10侧壁的上表面。 [0009] Step 5, see FIG. FIG. Ie or If, chemical mechanical polishing process is performed on the wafer surface planarization treatment may also increase the dry etch process silica anti-engraved after chemical mechanical polishing (second filling layer 23) until the upper surface of the sidewall of the trench 10 is exposed.

[0010] 此时可能出现两种情况,对于一些宽度较小的沟槽10,空洞30完全封闭在硅片表面(沟槽10侧壁的上表面)以下,具有较好的填充效果,如图Ie所示。 [0010] At this point two things can occur, for some of the smaller width of the groove 10, the cavity 30 is completely enclosed in the wafer surface (the upper surface 10 of the sidewall of the trench) or less, preferably having a filling effect, FIG. Ie in FIG. 而对于一些宽度较大的沟槽10,打磨或反刻时空洞30被打通,即空洞30有通道连接到硅片表面之上,填充效果较差,如图If所示。 For some of the larger width of the groove 10, when the cavity 30 is polished or engraved anti-open, i.e., with a channel connected to the cavity 30 on the silicon surface, poor filling effect, as shown in FIG If.

[0011] 上述五步所示的深沟槽的填充方法,通过调整工艺参数,可以确保对某一具体宽度的沟槽具有较好的填充效果,但对不同宽度沟槽却总是具有不一致的填充能力,这就对半导体产品的设计和制造工艺带来了限制。 [0011] The method of filling the deep trench shown in five steps, by adjusting the process parameters, can be ensured with better results trench fill a particular width, but having a different width of the groove is always inconsistent filling capacity, which the semiconductor product design and manufacturing processes has brought restrictions. 通常的CMOS制造工艺中,在沟槽填充的步骤之后必然包括一个或多个光刻步骤(例如多晶硅栅极刻蚀、轻掺杂漏注入、源漏注入、局部互连等工艺),光刻步骤需要在硅片表面覆盖一层光刻胶。 In conventional CMOS fabrication process, after the step of filling the trench necessarily includes one or more photolithographic steps (e.g. polysilicon gate etching, lightly doped drain implantation, source and drain implantation, local interconnect technology, etc.), photolithography steps required to cover a layer of photoresist on the wafer surface. 一旦沟槽的填充不彻底,沟槽内部的空洞与外界连通,光刻胶就会残留在空洞或者空洞与外界连通的结构而无法去除,残留的光刻胶会对后续工艺带来污染。 Once the trench is not completely filled, an internal cavity communicating with the outside groove, the photoresist will remain in the cavity or void structure connected to the outside and can not be removed, the remaining photoresist will bring a subsequent process contamination.

[0012] 由于沟槽的填充都是发生在多层集成电路的最下方的硅,因此在沟槽的填充之后必然具有形成层间介质的步骤,第一层层间介质位于第一层金属与硅之间,通常称为ILD-I。 [0012] Since the filling of the trench in the silicon occurs are lowermost layer IC, thus necessarily have a step formed between the layer of the media after filling the trench, a first inter-layer dielectric between the first layer and the metal between the silicon, commonly referred to as ILD-I.

[0013] 目前制备ILD-I的具体步骤为: [0013] It was prepared ILD-I specific steps are:

[0014] 第I步,在硅片表面淀积一层二氧化硅,这一层二氧化硅是衬垫层; [0014] Step I, depositing a layer of silicon dioxide on the silicon surface, this layer is silicon dioxide pad layer;

[0015] 第2步,在衬垫层之上再淀积一层二氧化硅,这一层二氧化硅是ILD-I的材料; [0015] Step 2, above the pad layer of silicon dioxide layer was deposited, a silica layer which is a material of the ILD-I;

[0016] 第3步,以化学机械研磨工艺对硅片表面的ILD-I进行平坦化处理,也可以在化学机械研磨之后增加干法刻蚀工艺反刻二氧化硅,直至ILD-I层达到预定的厚度。 [0016] Step 3., chemical mechanical polishing process on the planarized surface of the wafer ILD-I, can also increase the dry etch process silica anti-engraved after the chemical mechanical polishing, until the layer reaches the ILD-I predetermined thickness.

发明内容 SUMMARY

[0017] 本发明所要解决的技术问题是提供一种多层集成电路中沟槽的填充方法,该方法对于不同宽度的沟槽都具有良好的填充效果。 [0017] The present invention solves the technical problem is to provide a method of filling trenches in a multilayer integrated circuit, the method for different groove widths are of good filling effect.

[0018] 为解决上述技术问题,本发明多层集成电路中沟槽的填充方法在硅片表面刻蚀出沟槽、且热氧化生长一层二氧化硅之后紧接进行如下步骤: [0018] In order to solve the above technical problems, a multilayer integrated circuit of the present invention, filling the trench etching trenches in the wafer surface, and the thermally grown layer of silicon dioxide immediately after the following steps:

[0019] 第I步,在具有沟槽的硅片表面淀积一层二氧化硅,这一层二氧化硅是衬垫层; [0019] Step I, depositing a layer of silicon dioxide on the silicon wafer surface having a groove, which is the pad layer of silicon dioxide layer;

[0020] 第2步,在衬垫层之上再淀积一层掺杂有P型或η型杂质的二氧化硅,所述有掺杂的二氧化硅既填充所述沟槽,又是第一层层间介质的材料; [0020] Step 2, and then deposited on the backing layer a layer of silica doped with P-type or η-type impurities, said doped silicon dioxide filling the trench both, is a first inter-layer dielectric material;

[0021] 第3步,以化学机械研磨工艺对硅片表面的二氧化硅进行平坦化处理,直至达到第一层层间介质所要求的厚度。 [0021] Step 3., CMP process to planarize the surface of the silica wafers until the desired thickness of the medium reaches a first interlayer.

[0022] 本发明巧妙地将沟槽的填充与ILD-I的制备合二为一,同时将ILD-I的材料确定为掺杂有P型杂质(例如硼)或η型杂质(例如磷、砷、锑)的二氧化硅。 [0022] The present invention is filled trench skillfully prepared and combined ILD-I, while determined to be doped with a P-type impurity (e.g., boron) or η-type impurity (e.g. phosphorous material of the ILD-I, arsenic, antimony) silica. 由于掺杂有杂质的二氧化硅具有非常好的流动性,因此完全可以满足不同宽度的深沟槽填充要求。 Since the impurity-doped silica having a very good flowability, thus fully meet the requirements of the trench fill different widths.

附图说明 BRIEF DESCRIPTION

[0023] 图Ia〜图If是目前LCTVS管制造方法的第5步之中的填充沟槽的各步示意图; [0023] FIG Ia~ FIG If is a schematic view in each step of filling the trench Step 5 LCTVS pipe manufacturing method;

[0024] 图2a〜图2c是本发明多层集成电路中沟槽的填充方法的各步示意图。 [0024] FIG 2a~ Figure 2c is a schematic view in each step of the filling method of the present invention, a multilayer integrated circuit trench.

[0025] 图中附图标记说明: [0025] FIG REFERENCE NUMERALS:

[0026] 10为沟槽;21为衬垫层;22为第一填充层;23为第二填充层;30为空洞;41为衬垫层;42为ILD-I。 [0026] The trench 10; 21 a pad layer; a first filling layer 22; 23 of a second filler layer; cavity 30; 41 a pad layer; 42 ILD-I. 具体实施方式 Detailed ways

[0027] 本发明多层集成电路中沟槽的填充方法包括如下步骤: [0027] The method of filling a trench in a multilayer integrated circuit of the present invention comprises the steps of:

[0028] 开始时的状态,硅片表面刚刻蚀出沟槽10,并在具有沟槽10的硅片表面热氧化生长一层二氧化硅(未图示),这一层二氧化硅的厚度在50〜1000 A之间。 [0028] The state at the start, just silicon surface etched groove 10, and a silicon wafer having a thermally oxidized surface layer of silicon dioxide grown trench 10 (not shown), this layer of silica thickness between 50~1000 A.

[0029] 第I步,请参阅图2a,在具有沟槽10的硅片表面淀积一层二氧化硅,这一层二氧化硅是衬垫层41,不掺杂P型或η型杂质,厚度在500〜5000 A之间。 [0029] Step I, see FIG. 2a, the groove 10 having a silicon surface layer of silicon dioxide is deposited, this layer is silicon dioxide pad layer 41, an undoped type or P type impurities η , a thickness of between 500~5000 A.

[0030] 第2步,请参阅图2b,在硅片表面再淀积一层掺杂有P型或η型杂质的二氧化硅,厚度在5000〜50000 A之间,这一层二氧化硅一方面对沟槽10进行填充,另一方面作为第一层层间介质42的材料。 [0030] Step 2, please refer to Figure 2b, the surface and then depositing a layer of silicon doped with a P-type impurity or η-type silica, a thickness of between 5000~50000 A, this layer of silicon dioxide in one aspect of the trench 10 is filled, on the other hand between the first layer 42 of dielectric material. 第一层层间介质42的材料与衬垫层21融为一体,因此两者之间的界限以虚线表示。 A first inter-layer dielectric material 42 integrated with the liner layer 21, and therefore the boundaries between the two shown in phantom. 需要注意的是,对于深沟槽来说,这一步往往会在沟槽内部形成空洞30。 It should be noted that, for the deep trench, this step will often form a cavity 30 inside the trench.

[0031] 第3步,请参阅图2c,以化学机械研磨工艺对硅片表面进行平坦化处理,也可以在化学机械研磨之后增加干法刻蚀工艺反刻二氧化硅(第一层层间介质42的材料),直至第一层层间介质42达到要求的厚度。 [0031] Step 3. Refer to Figure 2c, chemical mechanical polishing process is performed on the wafer surface planarization treatment may also increase the dry etch process silica anti-engraved after chemical mechanical polishing (first inter-layer dielectric material 42) until the first inter-layer dielectric 42 to achieve the required thickness. 例如,ILD-I层预定为8000 A,则无论采用化学机械研磨,还是化学机械研磨加干法刻蚀,最终的停止侦测点就是沟槽10的侧墙上表面之上的二氧化硅层达到8000 A。 For example, ILD-I is a predetermined layer 8000 A, regardless of the chemical mechanical polishing, chemical mechanical polishing or dry etching addition, the final stopping point is detected dioxide layer 10 on the sidewalls of the trench above the surface reach 8000 A.

[0032] 由于第一层层间介质42掺杂有杂质,具有非常好的流动性,因此不论对任何宽度的沟槽10而言,空洞30都能保证完全封闭在硅片表面(沟槽10侧壁的上表面)以下。 [0032] Since the dielectric layer 42 between the first doped with impurities, having a very good flowability, so regardless of the groove width for any of 10, the cavity 30 can be completely closed to ensure that the wafer surface (the trench 10 on the surface of the sidewall) or less.

[0033] 下面以一个具体的器件的制造工艺对本发明作详细的介绍。 [0033] In the following a specific manufacturing process for the device description of the present invention in detail.

[0034] 瞬态(瞬变、瞬间)电压抑制器件(TVS,Transient Voltage Suppressor)是一种二极管,并联在电路中实现电路过压保护。 [0034] transients (transient, instantaneous) voltage suppressor (TVS, Transient Voltage Suppressor) is a diode connected in parallel to achieve overvoltage protection circuit in the circuit. 低电容瞬态电压抑制(LCTVS, low-capacitanceTransient Voltage Suppressor)是TVS管的一种,LCTVS管的传统制造方法为: Low capacitance transient voltage suppression (LCTVS, low-capacitanceTransient Voltage Suppressor) is a TVS diode, the conventional method of manufacturing a tube is LCTVS:

[0035] 第I步,在硅片(晶圆、晶片)的特定位置作出标记,例如刻蚀出沟槽等,这些标记作为后续工艺步骤的对准之用。 [0035] Step I, in a particular position to a silicon wafer (wafer, wafer) markers, e.g. etched trenches, etc., which is used as indicia for the alignment of the subsequent process steps.

[0036] 第2步,采用离子注入工艺在硅片内形成一个埋层,注入的杂质可以是P型或η型。 [0036] Step 2, an ion implantation process for forming a buried layer within the silicon wafer, an impurity may be implanted η-type or P-type.

[0037] 第3步,在硅片表面淀积一层外延层(P型或η型单晶硅,与埋层杂质的类型相反)。 [0037] Step 3., a layer of the epitaxial layer is deposited on the surface of the silicon wafer (P-type single crystal silicon or η-type, with the opposite type buried layer impurity).

[0038] 第4步,在外延层内进行离子注入,注入的杂质与外延层杂质的类型相同,用来调整外延层内的杂质浓度,形成LCTVS管的P区或η区中的一个。 [0038] Step 4, in the epitaxial layer ion implantation, the implanted impurities of the same type with the impurity of the epitaxial layer, for adjusting the impurity concentration in the epitaxial layer, forming a P region or regions η LCTVS the tube.

[0039] 第5步,在LCTVS管的四周(若工艺需要,还包括LCTVS管内部)刻蚀出沟槽并进行热氧修复,向沟槽内填充介质材料(例如二氧化硅)作为隔离之用。 [0039] step 5, around LCTVS tube (if the process requires, further comprising an internal tube LCTVS) and thermally etched trenches repair oxygen, into the dielectric trench fill material (e.g. silicon dioxide) as a separator of use.

[0040] 第6步,在外延层内进行源漏注入(中高掺杂离子注入),形成LCTVS管的P区或η区中的另一个。 [0040] Step 6, a source and drain implantation (high ion implantation) in the epitaxial layer, a further P region forming region or η in LCTVS tube.

[0041] 第7步,在硅片表面淀积一层二氧化硅,作为ILD-1。 [0041] Step 7, a layer of silicon dioxide is deposited on the silicon surface, as ILD-1. 淀积之前还可以包括淀积衬垫层二氧化硅的步骤,淀积之后还可以包括化学机械研磨的平坦化处理步骤。 May further comprise prior to deposition step of depositing silicon dioxide pad layer, after depositing a planarization process may further comprise the step of chemical mechanical polishing.

[0042] 上述方法的第5步中,对于沟槽的填充步骤,目前均如背景技术所述采用多次填充的方法,但是对不同宽度沟槽却总是存在填充能力不一致的缺陷。 [0042] Step 5 of the above method, the step for filling the trench, as are currently employed in the background art method of filling a plurality of times, but there is always inconsistent filling capacity defects trenches of different widths. 如采用本发明所述沟槽的填充方法,则保持第I步〜第4步不变,将第5步〜第7步改为: The filling method of the present invention using the trench, the holding step I ~ Step 4 unchanged, the step 5 to step 7 should read:

[0043] 第5'步,在外延层内进行源漏注入(中高掺杂离子注入),形成LCTVS管的ρ区或η区中的另一个。 [0043] 5 'step for source and drain implantation (high ion implantation) in the epitaxial layer, forming a further zone or η ρ LCTVS region of the tube.

[0044] 第6'步,在LCTVS管的四周(若工艺需要,还包括LCTVS管内部)刻蚀出沟槽并进行热氧修复。 [0044] 6 'step around LCTVS tube (process if necessary, further comprises an inner tube LCTVS) etching trenches and repair thermal oxidation.

[0045] 第7'步,在硅片表面淀积一层掺杂有P型或η型杂质的二氧化硅,作为ILD-1,这一层ILD-I兼具填充沟槽的作用。 [0045] Step 7 ', is deposited on the silicon surface layer of silica doped with a P-type or η-type impurity, as ILD-1, which combines the role of a layer of ILD-I fill the trenches. 淀积之前还包括淀积衬垫层二氧化硅的步骤,淀积之后还包括化学机械研磨的平坦化处理步骤。 Before depositing further comprises the step of depositing silicon dioxide pad layer, after depositing a planarization process further comprising the step of chemical mechanical polishing.

[0046] 需要注意的是,本发明所述方法在沟槽刻蚀步骤(包括热氧修复)完成之后,必须紧跟着进行ILD-I的淀积步骤。 [0046] It should be noted that the method of the present invention, after the trench etching step (including heat fixes oxygen) is completed, steps must be followed by deposition of ILD-I. 这样就需要将原来位于这两个步骤之间的步骤(例如例如多晶硅栅极刻蚀、轻掺杂漏注入、源漏注入、局部互连等工艺)全部改为在沟槽刻蚀步骤之前进行。 This step needs to be originally located between the two steps (e.g. etch such as polysilicon gate, lightly doped drain implantation, source and drain implantation, local interconnect technology, etc.) prior to all of trench etch step .

Claims (5)

1. 一种多层集成电路中沟槽的填充方法,其特征是,所述方法在硅片表面刻蚀出沟槽、且热氧化生长一层二氧化硅之后紧接进行如下步骤: 第I步,在具有沟槽的娃片表面淀积一层二氧化娃,这一层二氧化娃是衬垫层; 第2步,在衬垫层之上再淀积一层掺杂有P型或η型杂质的二氧化硅,所述有掺杂的二氧化硅既填充所述沟槽,又是第一层层间介质的材料; 第3步,以化学机械研磨工艺对硅片表面的二氧化硅进行平坦化处理,直至达到第一层层间介质所要求的厚度。 A method of filling trenches in a multilayer integrated circuit, wherein the method trenches etched in the silicon surface, and a layer of thermally grown silicon dioxide immediately after the following steps: I, step, deposited on the sheet surface having a trench baby doll dioxide layer, this layer is a cushion layer baby dioxide; step 2, and then deposited on the liner layer with a layer of doped P-type or η-type impurity is silica, the silica doped only filling the trench, and a material layer between the first medium; step 3, a chemical mechanical polishing process of the wafer surface two pairs silicon oxide planarization process, until the desired thickness of the dielectric between the first layer.
2.根据权利要求I所述的多层集成电路中沟槽的填充方法,其特征是,所述热氧化生长的二氧化硅的厚度为50〜1000人。 I 2. The method of filling the trench multilayer integrated circuit according to claim, characterized in that the thickness of the thermally grown silicon dioxide is 50~1000 people.
3.根据权利要求I所述的多层集成电路中沟槽的填充方法,其特征是,所述方法第I步中,淀积二氧化硅的厚度为500〜5000人。 I 3. The method of filling the trench multilayer integrated circuit according to claim, characterized in that the method step I, the thickness of the deposited silica is 500~5000 people.
4.根据权利要求I所述的多层集成电路中沟槽的填充方法,其特征是,所述方法第2步中,淀积有掺杂的二氧化硅的厚度为5000〜50000入。 The filling method of claim I multilayer integrated circuit as claimed in claim trench, characterized in that the method step 2, doped silicon dioxide is deposited to a thickness of the 5000~50000.
5.根据权利要求I所述的多层集成电路中沟槽的填充方法,其特征是,所述方法第3步中,还包括以干法刻蚀工艺反刻硅片表面的二氧化硅,直至达到第一层层间介质所要求的厚度。 The filling method of claim I in multilayer integrated circuit as claimed in claim trench, characterized in that the method step 3, further comprising a dry etching process to the silica anti-engraved wafer surface, until the desired thickness of the dielectric between the first layer.
CN 200910057076 2009-04-16 2009-04-16 Slot filling method in multilayer integrated circuit CN101866873B (en)

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US5956598A (en) 1998-07-02 1999-09-21 United Microelectronics Corp. Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit
CN1860251A (en) 2003-07-07 2006-11-08 微米技术有限公司 Methods of forming a phosphorus doped silicon dioxide comprising layer, and methods of forming trench isolation in the fabrication of integrated circuitry
CN101246842A (en) 2007-02-16 2008-08-20 中微半导体设备(上海)有限公司 Method for forming shallow plough groove isolation area in semiconductor integrated circuit technique

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956598A (en) 1998-07-02 1999-09-21 United Microelectronics Corp. Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit
CN1860251A (en) 2003-07-07 2006-11-08 微米技术有限公司 Methods of forming a phosphorus doped silicon dioxide comprising layer, and methods of forming trench isolation in the fabrication of integrated circuitry
CN101246842A (en) 2007-02-16 2008-08-20 中微半导体设备(上海)有限公司 Method for forming shallow plough groove isolation area in semiconductor integrated circuit technique

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