CN102315093B

CN102315093B - Process method for flattening filled trench

Info

Publication number: CN102315093B
Application number: CN 201010221597
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-07-08
Filing date: 2010-07-08
Publication date: 2013-04-24
Anticipated expiration: 2030-07-08
Also published as: CN102315093A

Abstract

The invention discloses a process method for flattening a filled trench. The process method comprises the following steps of: growing a layer of epitaxial layer on a substrate silicon sheet; growing a hard mask on the epitaxial layer; forming the trench in the epitaxial layer; epitaxially growing silicon in the trench so as to fill the trench; preliminarily flattening the surface of the trench by grinding by using chemical machinery; performing high-temperature thermal oxidation on the silicon on the surface of the trench; and removing an oxidized layer and the hard mask from the surface of the trench by using wet etching or dry etching. By the process method, flattening of the surface of the trench can be realized, and the surface of the trench can be flattened well; and the process method is applicable to super junction metal-oxide-semiconductor field effect transistor (MOSFET) devices.

Description

The process of flattening filled trench

Technical field

The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of process of flattening filled trench.

Background technology

The structure of super junction MOSFET device as shown in Figure 1, the groove-shaped epitaxial loayer 3 that films of opposite conductivity is filled that has is arranged in the N epitaxial loayer 2 on silicon substrate (N+ substrate) 1, and this top, zone is surrounded by P well region 5, N+ well region 6, P+ implanted layer 7 from outside to inside successively.Between two groove-shaped epitaxial loayers 3, be provided with polysilicon 4 on the N epitaxial loayer 2, polysilicon 4 is provided with inter-level dielectric 8, and then source metal electrode 9 covers whole inter-level dielectric 8 and epitaxial loayers 3.There is back metal electrode (drain electrode) 10 at N+ substrate 1 back side.

The main difficult point of this device is the formation of P type and the N type semiconductor laminate structure of alternative arrangement.This structure forms process two kinds, and the first (seeing Fig. 2) is: at silicon substrate 21 growth one deck epitaxial loayers 22, suitable position is carried out dopant implant and is formed ion implanted region 23 in epitaxial loayer 22; Regrowth one deck epitaxial loayer 22 on original epitaxial loayer 22; In last time identical dopant implant position, the epitaxial loayer 22 that is positioned at rear growth carries out dopant implant again and forms ion implanted region 23.Like this through repeatedly circulation epitaxial growth and dopant implant, until epitaxial thickness reaches needed channel depth.Carry out the diffusion of dopant implant district at boiler tube and make a plurality of ion implanted regions form a doped region of finishing 25, complete like this P (or N) type thin layer is just finished.The problem that the method exists is: at first, cost is higher, extension and to inject all be that semiconductor is made cost higher technique, particularly extension, in general semiconductor is made generally for once; Next is that technique is difficult to control, and epitaxial growth several times requires identical resistivity, and identical film quality is had relatively high expectations to the stable aspect of technique; Each injection all requires in identical position in addition, all requires very high to aligning, the precision aspect of injecting.

Another method of manufacturing technology is at first at the silicon epitaxy layer 32 of silicon substrate 31 growth thick layers, then at these epitaxial loayer 32 formation grooves 35, to use silicon epitaxy 33 filling grooves 35 (seeing Fig. 3) that the phase contra-doping is arranged with epitaxial loayer 32 again.After filling, extension because the surplus of extension is grown, generally to carry out planarization to flute surfaces.The method of planarization generally has two kinds, and the one, cmp, the 2nd, dry etching.Two kinds of methods all need to have hard mask as the barrier layer, but the etching selection ratio of the bi-material of dry etching generally is lower than the grinding ratio of cmp, so usually select chemical and mechanical grinding method to carry out planarization.But chemical and mechanical grinding method also has limitation, and namely milling time is long, has certain thickness silicon residual at hard mask easily, in case produce the residual then cmp of silicon then be difficult to get rid of.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of process of flattening filled trench,

Can obtain the good flute surfaces of planarization.

For solving the problems of the technologies described above, the process of flattening filled trench of the present invention comprises the steps:

Step 1, at silicon substrate growth one deck epitaxial loayer;

Step 2, carry out the growth of hard mask at described epitaxial loayer;

Step 3, in described epitaxial loayer, form groove;

Step 4, in described groove, carry out growing epitaxial silicon and fill this groove;

Step 5, with cmp described flute surfaces is carried out preliminary planarization;

Step 6, the silicon of described flute surfaces is carried out high-temperature thermal oxidation;

Step 7, remove oxide layer and the hard mask of flute surfaces with wet etching or dry etching.

Adopt method of the present invention, behind etching groove, keep hard mask, then use the growing epitaxial silicon filling groove, with cmp groove is carried out preliminary planarization again, remove with the silicon thin layer of high-temperature thermal oxidation method after with cmp at last.Because the silicon layer to flute surfaces carries out high-temperature thermal oxidation, can make the silicon layer on the hard mask be converted into oxide layer fully; Can thoroughly remove oxide layer and hard mask with wet etching or dry etching again.Therefore, the present invention can effectively solve the planarization problem after the trench fill, obtains the good flute surfaces of planarization.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is super junction MOSFET device cell schematic diagram;

Fig. 2 is P type and the N type semiconductor laying manufacture method schematic diagram of the first alternative arrangement;

Fig. 3 is P type and the N type semiconductor laying manufacture method schematic diagram of the second alternative arrangement;

Fig. 4-the 10th, method one embodiment process flow diagram of the present invention;

Figure 11 is method one embodiment control flow chart of the present invention.

Embodiment

In conjunction with shown in Figure 11, in one embodiment, the process of described flattening filled trench comprises the steps:

Step 1, epitaxial growth.Referring to shown in Figure 4, adopt to have highly doped N-type silicon substrate 51, at the low-doped N-type thick epitaxial layer 52 of these silicon substrate 51 growths, the thickness of epitaxial loayer 52 and has the first doping type between 10.0 μ m-100.0 μ m.

Step 2, hard mask growth.Referring to Fig. 5, adopt the methods such as epitaxial growth, thermal oxidation or deposit to form one deck or a few layer dielectric on the surface of described epitaxial loayer 52, as the hard mask 56 of etching groove.Described hard mask is at least a in silica, silicon nitride and the silicon oxynitride, and thickness is

Step 3, etching groove.Referring to shown in Figure 6, etching the degree of depth in described epitaxial loayer 52 is 10.0-100.0 μ m, and width is the groove 55 of 1.0-10.0 μ m.Groove 55 etchings can with photoresist as etching barrier layer, after the etching be removed photoresist; Also available hard mask 56 is as etching barrier layer, hard mask 56 all or part of reservations after groove 55 etchings.

Step 4, extension are filled.Referring to Fig. 7, in described groove 55, carry out P type growing epitaxial silicon and form silicon epitaxy layer 53, groove 55 is filled fully.Certainly, the epitaxial loayer 52 that is grown on the silicon substrate 51 also can be the P type, and what carry out the growing epitaxial silicon filling this moment in groove 55 then should be N-type.The silicon epitaxy layer 53 of groove 55 interior growths has the second doping type.

Step 5, groove is carried out preliminary planarization.Referring to Fig. 8, behind the complete filling groove 55 of growing epitaxial silicon, because superfluous growth, the silicon epitaxy layer 53 at groove 55 tops can be higher than hard mask 56, and also has certain thickness silicon layer formation on the hard mask 56 of groove 55 both sides.With chemical and mechanical grinding method preliminary planarization is carried out on groove 55 surfaces.The thickness of the silicon layer after the preliminary planarization on the hard mask 56 exists

Between.

Step 6, high-temperature thermal oxidation.Referring to Fig. 9, the silicon layer on groove 55 surfaces is carried out high-temperature thermal oxidation, make the silicon layer on the hard mask 56 be converted into oxide layer 57 fully through behind the high-temperature oxydation.

Step 7, referring to shown in Figure 10, adopt wet etching or dry etching to remove oxide layer 57 and the hard mask 56 on epitaxial loayer 52 and groove 55 surfaces.

More than by embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. the process of a flattening filled trench is characterized in that, may further comprise the steps:

Step 1, at silicon substrate growth one deck epitaxial loayer;

Step 2, carry out the growth of hard mask at described epitaxial loayer;

Step 3, in described epitaxial loayer, form groove;

2. process as claimed in claim 1, it is characterized in that: the thickness of epitaxial loayer described in the step 1 is 10.0-100.0 μ m, and has the first doping type.

3. process as claimed in claim 1 is characterized in that: hard mask described in the step 2 is at least a in silica, silicon nitride and the silicon oxynitride, and thickness is

4. process as claimed in claim 1, it is characterized in that: the width of groove described in the step 3 is 1.0-10.0 μ m, the degree of depth is 10.0-100.0 μ m; The hard at least part of reservation of mask behind the etching groove.

5. process as claimed in claim 1 is characterized in that: behind the complete filling groove of growing epitaxial silicon described in the step 4, the height of silicon is higher than hard mask in its groove, and on the hard mask in groove both sides certain thickness silicon layer growth is arranged; Silicon epitaxy layer in the groove has the second doping type.

6. process as claimed in claim 1 is characterized in that: described in the step 5 behind the cmp on the hard mask remaining silicon layer thickness be

7. process as claimed in claim 1 is characterized in that: the silicon layer behind the high-temperature thermal oxidation described in the step 6 on the hard mask is converted into oxide layer fully.