CN101860430B - Device and method for implementing optical network unit switching clock source - Google Patents
Device and method for implementing optical network unit switching clock source Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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Abstract
The invention discloses a device and a method for implementing an optical network unit switching clock source. The device comprises a clock source detection module and a clock source switching module which are connected in turn, wherein the clock source detection module detects current valid clock sources from all to-be-detected multi-path clock sources of an optical network unit, and the current valid clock sources mean that signal frequency errors of the clock sources at the current moment are smaller than a preset valid threshold value; and the clock source switching module compares the priorities of all the valid clock sources, specifies the clock source with the highest priority as the current active clock source, and switches the clock source into the current active clock source when the priority of the clock source used at the previous moment is lower than that of the current active clock source. The device and the method overcome the defects that the conventional ONU system has higher cost and is complex, and greatly improve the reliability of the ONU system.
Description
Technical field
The Clock Synchronization Technology that the present invention relates to communication, relates in particular to the device and method of realizing optical network unit (ONU, Optical Network Unit) switching clock source.
Background technology
Along with the continuous growth of various communication services, in order to meet the demand of user to different communication business, ONU needs to switch multiple clock sources, and common clock source is as 1PPS(pulse per second (PPS)) clock source, 8K light path clock source, 25M synchronous Ethernet clock source etc.ONU user can forbid or enable one or more clock sources, distributes a priority also can to each clock source, offers ONU and automatically select the foundation of clock source.Clock source after ONU switches is sent to follow-up clock synchronization circuit, as digital phase-locked loop (DPLL, Digital Phase Locked Loop), and the signal of the various frequencies that generation user needs.
And ONU is in the time realizing the switching of multiple clock sources, can not simply indiscriminately imitate the operation method of single clock source.The mode disunity that ONU detects and switches multiple clock sources at present, some ONU stacking single clock source adopts simply chip or circuit, cause the cost of ONU to improve, and the complexity of system increases, and the reliability of system reduces.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method and device of realizing optical network unit switching clock source, can reliably switch multiple clock sources, reduces system cost and complexity.
In order to solve the problems of the technologies described above, the invention provides a kind of device of realizing optical network unit switching clock source, comprise the clock source detection module and the clock source switching module that connect successively; Wherein:
Clock source detection module, for detecting current effective clock source from all multipath clock sources that will detect of optical network unit, described current effective clock source refers to that the signal frequency error of current time clock source is less than default effective threshold value;
Clock source switching module, for the priority of more all effective clock sources, clock source the highest priority is appointed as to the clock source of current active, the priority of the clock source using in previous moment during lower than the priority of the clock source of current active, is switched to the clock source of current active.
In clock source detection module, each clock source detection sub-module of multiple clock source detection sub-module correspondingly detects each the road clock source in multipath clock source;
Clock source detection sub-module further comprises frequency error detection unit, holding unit and state indication unit, wherein:
Whether effectively frequency error detection unit, for according to the frequency error of the current time clock source detecting and described effective threshold value of discovering and seizing according to the call number of clock source, export this clock source of current time level signal;
Holding unit, for the effective level signal of this clock source of current time of frequency error detection unit output is remained to after the shortest stabilizing time of this clock source, exports a triggering signal;
State indication unit, under the effect of triggering signal, according to the effective level signal of clock source of frequency error detection unit output, the signal that output telltable clock source is effective status.
Further, holding unit is realized by a timer units, and state indication unit is realized by an inverter module and a d type flip flop unit, wherein:
Timer units, counts as enable signal for the effective level signal of this clock source of current time taking frequency error detection unit output, waits to count down to the shortest stabilizing time of this clock source then, exports a rising edge signal;
Inverter module, for the whether effective anti-phase output of level signal of current time clock source that frequency error detection unit is exported;
D type flip flop unit, under the effect for the rising edge signal of the output at timer units, triggers input signal and is mapped to output Q end, the signal that output telltable clock source is effective status using the signal of inverter module output as D.
Further, clock source switching module further comprises the valid clock source collector unit, movable clock source determining unit and the clock source switch unit that connect successively, wherein:
Valid clock source collector unit, collects all effective clock sources for the current state of each the road clock source from the output of clock source detection module, and the call number of corresponding clock source is exported to priority comparing unit;
Priority comparing unit, for discover and seize priority and the weights priority of corresponding clock source according to the call number of clock source of input, the row major level of going forward side by side comparison, is appointed as the highest clock source of priority comparing the clock source of current active; If the priority of clock source that the weights priority of the clock source of this current active is used higher than previous moment, is carried at the call number of the clock source of this current active and exports to clock source switch unit in switching command;
Clock source switch unit, for discovering and seizing the frequency signal of corresponding clock source according to the switching command of input, and switches to the clock source of previous moment activity the clock source of current active.
Further, also comprise the clock synchronization module being connected with clock source switching module, wherein:
Clock synchronization module, for switching the clock source of exporting as benchmark taking clock source switching module, synchronous clock signal.
In order to solve the problems of the technologies described above, the invention provides a kind of method that realizes optical network unit switching clock source, comprising:
From all clock sources that will detect of optical network unit, detect current effective clock source, current effective clock source refers to that the frequency error of current time clock source is less than the clock source of default effective threshold value;
The priority of more all effective clock sources, is appointed as clock source the highest priority the clock source of current active, and the priority of the clock source using as previous moment during lower than the priority of the clock source of current active, is switched to the clock source of current active;
From all clock sources that will detect of optical network unit, detect current effective clock source, specifically comprise:
To each clock source in all clock sources that will detect, the frequency error of this clock source of current time detected, discover and seize the effective threshold value default into this clock source according to the call number of this clock source, comparison frequency error and effectively threshold value, whether effectively level signal of this clock source of output current time; The effective level signal of this clock source of the current time of output is remained to after the shortest stabilizing time of this clock source to the current effective signal of output this clock source of instruction.
Further,
When clock source the highest priority is appointed as to the clock source of current active, the weights priority of clock source the highest priority is defined as to the priority of the clock source of current active.
Further, be switched to after the clock source of current active, taking the clock source of current active as benchmark, synchronous clock signal.
The present invention is due to the unified mode of ONU is judged clock source validity, therefore do not need chip or the circuit of ONU polytype clock source to carry out the various clock sources of processing selecting, overcome the higher and more complicated defect of original ONU system cost, greatly improved the reliability of ONU system.
Brief description of the drawings
Fig. 1 is the structural representation of the device embodiment that realizes optical network unit switching clock source of the present invention;
Fig. 2 is the electrical block diagram of clock source detection module embodiment in Fig. 1 shown device embodiment;
Fig. 3 is the electrical block diagram of clock source switching module embodiment in Fig. 1 shown device embodiment;
Fig. 4 is the state flow schematic diagram that the clock source switching module embodiment shown in Fig. 3 carries out clock source switching;
Fig. 5 is the flow chart of the embodiment of the method that realizes optical network unit switching clock source of the present invention.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, technical scheme of the present invention is at length set forth.The embodiment below exemplifying is only for description and interpretation the present invention, and do not form the restriction to technical solution of the present invention.
As shown in Figure 1, this device 10 comprises the clock source detection module 11 and the clock source switching module 12 that connect successively to its structure of device embodiment that realizes optical network unit switching clock source provided by the invention; Wherein:
Clock source detection module 11, for detecting current effective clock source from all clock sources that will detect of ONU system, current effective clock source refers to that the signal frequency error of current time clock source is less than default effective threshold value;
Clock source detection module 11 correspondingly detects multipath clock source by multiple clock source detection sub-module (clock source detection sub-module 1～clock source detection sub-module M), as shown in Figure 1, each the road clock source that converges to ONU is all furnished with an independent clock source detection sub-module and detects its validity.
Clock source switching module 12, for the priority of more all effective clock sources, clock source the highest priority is appointed as to the clock source of current active, the priority of the clock source using in previous moment during lower than the priority of the clock source of current active, is switched to the clock source of current active.
The above-mentioned device embodiment that realizes optical network unit switching clock source also comprises the clock synchronization module 13 being connected with clock source switching module 12, is benchmark for the clock source of exporting taking clock source switching module 12, synchronous clock signal.
The clock source that clock source switching module 12 is exported also can be sent to DPLL circuit, the signal of the various frequencies that generation user needs.
Fig. 2 has represented the circuit structure of each the clock source detection sub-module embodiment in the clock source detection module 11 shown in Fig. 1, comprising: frequency error detection unit 111, timer units 112, inverter module 113, d type flip flop unit 114; Wherein:
Frequency error detection unit 111, for effective threshold value and the invalid threshold value with this clock source of presetting according to the frequency error in the input clock source detecting, whether effectively level signal of this clock source of output current time;
Output low level 0 in the time that frequency error detection unit 111 detects that the frequency error of clock source is less than effective threshold value of setting, represents that this moment clock source is effective; In the time that frequency error detection unit 111 detects that the frequency error of clock source is more than or equal to the invalid threshold value of setting, export high level 1, represent that this moment clock source is invalid.
Timer units 112, for the effective level signal of instruction current time clock source exported with frequency error detection unit 111 enable under (EN), count, clock source the shortest stabilizing time to be count down to then, is exported a rising edge signal at T end (overtime TIMEOUT pin);
The effect of timer units 112 be prevent the state of clock source between effective status and disarmed state, switch continually and cause d type flip flop unit 114 export (be whole clock source detection sub-module output) unstable.
Inverter module 113, for the anti-phase output of the effective level signal of instruction current time clock source that frequency error detection unit 111 is exported;
For example when frequency error detection unit 111 detect clock source this moment effectively and output low level 0, just anti-phase output high level 1 of inverter module 113.
D type flip flop unit 114, under the effect of the rising edge signal of exporting for the T end at timer units 112, the signal that inverter module 113 is exported triggers input signal as D and is mapped to the output of Q end, represents that whether present clock source is effective.
For example d type flip flop unit 114 is under the effect of the rising edge signal of the T end output at timer units 112, and the high level 1 that inverter module 113 is exported copies to the output of Q end, represents that current time clock source is effective.
To the clock source detection sub-module embodiment shown in Fig. 2, the testing process expansion of the clock source validity to input is explained below.
First frequency error detection unit 111 according to the call number of the clock source of input, finds corresponding configuration attribute call number, as shown in table 1; Then according to the configuration attribute call number of discovering and seizing, find clock signal frequency and configuration attribute that this clock source is corresponding, as shown in table 2, wherein the configuration attribute of clock source comprises: priority, weights priority, effective threshold value (inner tolerance), the shortest stabilizing time (validation timer) and invalid threshold value (outer tolerance).
The configuration attribute index of table 1 clock source
| Clock source index | Clock source title | Whether clock source is enabled | Configuration attribute index |
| 0 | GPS1 clock source | Be | 0 |
| 1 | GPS2 clock source | Be | 1 |
| 2 | Light path clock source | Be | 2 |
| 3 | Synchronous Ethernet clock source | Be | 3 |
The configuration attribute of table 2 clock source
Note: in table 2, " PPS " represents pulse per second (PPS), " ppm " expression 1,000,000/.
The difference of the invalid threshold value of effective threshold value of the explained later clock source that once the present embodiment provides and its effect.At previous moment clock source be invalid in the situation that, when the signal frequency error of this moment clock source must be less than effective threshold value of clock source, just can think that this moment clock source is effectively (no-faulted); And be in effective situation at previous moment clock source, when the signal frequency error of this moment clock source must be greater than the invalid threshold value of clock source, just can think that this moment clock source is invalid (faulted).
The invalid threshold value of clock source that the embodiment of the present invention provides is greater than the effective threshold value of clock source.
For example, when the clock source of input is the GPS1 clock source shown in table 1, its clock source call number is 0, finding accordingly its configuration attribute call number is also 0, finding the signal frequency of this clock source according to configuration attribute call number is 1PPS(pulse per second (PPS)), effective threshold value of this clock source, invalid threshold value are respectively 100ppm and 1000ppm, and the shortest stabilizing time of this clock source is 5S.
Suppose that this clock source frequency error that frequency error detection unit 111 measured in this moment is 750ppm, if previous moment GPS1 clock source is effective, be less than so the invalid threshold value 1000ppm of clock source due to frequency error 750ppm, this moment GPS1 clock source or effective; And if previous moment GPS1 clock source is invalid, because frequency error 750ppm is greater than effective threshold value 100ppm of clock source, this moment GPS1 clock source will be also invalid.
Frequency error detection unit 111 detects that the clock source of input is invalid at any one time, just export high level 1, when frequency error detection unit 111 at any one time becomes high level 1(clock source from effectively to invalid from low level 0) or output high level 1, timer units 112 all can reset.
Frequency error detection unit 111 detects that the clock source of input is effective at any one time, just output low level 0, make thus timer units 112 start counting, count down to after clock source the shortest stabilizing time (as 5S), the T end of timer units 112 can be exported a rising edge signal from low level 0 to high level 1; And inverter module 113 is exported high level 1 in the time of frequency error detection unit 111 output low level 0, finally make output (Q pin) the output high level of d type flip flop unit 114, represent that present clock source is effective.
Clock source detection sub-module shown in Fig. 2 is only one of embodiment, and it is all realized by hardware circuit substantially.In fact, the present invention, except above-described embodiment, also can exemplify out other embodiment.For example, what the timer units 112 shown in Fig. 2 played is the effect of a holding unit, after the frequency error detection unit 111 effective level signals in output clock source being remained to clock source the shortest stabilizing time, export a triggering signal, it also can be realized by the mode of software delay certainly.Again for example, inverter module 112 and d type flip flop unit 114 are combined, play the effect of a state indication unit, it exports the state through keeping the clock source of processing under the effect of the triggering signal of holding unit, certainly it also can consist of other form, for example passes through the trigger of other form etc.In a word, effect the essence any and circuit shown in Fig. 2 other circuit identical but retouching distortion a little all should be within protection scope of the present invention.
Fig. 3 is the circuit structure of clock source switching module 12 embodiment in Fig. 1 shown device embodiment, comprises the valid clock source collector unit 121, movable clock source determining unit 122 and the clock source switch unit 123 that connect successively, wherein:
Valid clock source collector unit 121, collects all clock sources in effective status for the current state of each road clock source of exporting from clock source detection module 11, and the call number of corresponding clock source is exported to priority comparing unit 122;
Priority comparing unit 122, for discover and seize priority and the weights priority of corresponding clock source according to the call number of the clock source of input, the row major level of going forward side by side comparison, is appointed as the highest clock source of priority comparing (active) clock source of current active; If the priority of clock source that the weights priority of the clock source of this current active is used higher than previous moment, is carried at the call number of movable clock source and exports to clock source switch unit 123 in switching command;
In the configuration attribute of the clock source of priority comparing unit 122 from table 2, discover and seize priority and the weights priority of corresponding clock source.
Clock source switch unit 123, for discovering and seizing the frequency signal of corresponding clock source according to the switching command of input, and switches to the clock source of previous moment activity the clock source of current active.
In the configuration attribute of clock source switch unit 123 clock source from table 2 according to the call number of the clock source carrying in switching command, discover and seize the frequency signal of corresponding clock source.
Fig. 4 is the clock source state flow-chart that the clock source switching module embodiment shown in Fig. 3 determines and switch current time activity, the current time state of each road clock source that clock source switching module receive clock source detection module 11 is exported, therefrom collects all clock sources in effective status.
The explained later clock source priority that once embodiment of the present invention provides and difference and the effect of weights priority.The scope of the priority of clock source and weights priority is all from 0 to 3.Wherein, 0 represents that priority is the highest, and 3 represent that priority is minimum.In all clock sources in effective status, the clock source that priority is the highest will be designated as the clock source of current time activity.In the time that a clock source is designated as movable clock source, its priority is just set to its weights priority.The effect of weights priority is, in the time that a certain road clock source is designated as movable clock source, can be that this clock source is set a more higher leveled priority, and object is for fear of switching clock source continually equally.
In all valid clock sources, a certain moment only has a movable clock source, and this movable clock source can be outputed to clock source synchronization module by clock source switching module and carry out follow-up processing.
For example, in Fig. 4, A is GPS1 clock source, and B is GPS2 clock source, and C is light path clock source, and D is synchronous Ethernet clock source.The priority of each clock source is respectively 0,1,2,3, and weights priority should be 0,0,1,2 mutually.Suppose a certain moment, A, B clock source are all invalid, and C is designated as movable clock source; Again after a period of time, B clock source has become effective status from disarmed state, if there is no weights priority, B clock source can be designated as movable clock source, because the priority 1 of B is higher than the priority 2 of C.But because C is current time activity (in use) clock source, its weights priority is 1, it equates with the priority 1 of B, so C or movable clock source.Fig. 4 has at length drawn having weights priority and corresponding state transition diagram during without weights priority.
The present invention is directed to said apparatus embodiment, a kind of embodiment of the method that realizes optical network unit switching clock source is correspondingly provided, its flow process as shown in Figure 5, comprises the steps:
110, from all clock sources that will detect of ONU system, detect current effective clock source;
Current effective clock source refers to, the signal frequency error of current time clock source is less than default effective threshold value.
120, the priority of more all effective clock sources, is appointed as clock source the highest priority the clock source of current active;
130, judge whether the priority of the clock source of previous moment use is less than the priority of the clock source of current active, is to carry out next step, otherwise process ends;
In the time specifying the clock source of current active, the weights priority of this appointed clock source is decided to be its priority, if judge, the priority of the clock source of previous moment use is less than the priority of the clock source of this current active, determines the switching of carrying out clock source.
140, the clock source that previous moment is used is switched on the clock source of current active.
After step 140, also comprise:
To switch the clock source of exporting as benchmark, synchronous clock signal.
One of ordinary skill in the art will appreciate that all or part of step in said method can carry out instruction related hardware by program and complete, described program can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits.Correspondingly, the each module/unit in above-described embodiment can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. realize a device for optical network unit switching clock source, comprise the clock source detection module and the clock source switching module that connect successively; Wherein:
Described clock source detection module, for detecting current effective clock source from all multipath clock sources that will detect of optical network unit, described current effective clock source refers to that the signal frequency error of current time clock source is less than default effective threshold value;
Described clock source switching module, for the priority of more all effective clock sources, clock source the highest priority is appointed as to the clock source of current active, the priority of the clock source using in previous moment during lower than the priority of the clock source of current active, is switched to the clock source of current active;
In described clock source detection module, each clock source detection sub-module of multiple clock source detection sub-module correspondingly detects each the road clock source in described multipath clock source;
Described clock source detection sub-module further comprises frequency error detection unit, holding unit and state indication unit, wherein:
Whether effectively described frequency error detection unit, for according to the frequency error of the described current time clock source detecting and described effective threshold value of discovering and seizing according to the call number of described clock source, export this clock source of current time level signal;
Described holding unit, for the effective level signal of this clock source of described current time of described frequency error detection unit output is remained to after the shortest stabilizing time of this clock source, exports a triggering signal;
Described state indication unit, under the effect of described triggering signal, according to the effective level signal of described clock source of described frequency error detection unit output, the signal that the described clock source of output instruction is effective status.
2. according to device claimed in claim 1, it is characterized in that, described holding unit is realized by a timer units, and described state indication unit is realized by an inverter module and a d type flip flop unit, wherein:
Described timer units, counts as enable signal for the effective level signal of this clock source of current time taking described frequency error detection unit output, waits to count down to the shortest stabilizing time of this clock source then, exports a rising edge signal;
Described inverter module, for the whether effective anti-phase output of level signal of current time clock source that described frequency error detection unit is exported;
Described d type flip flop unit, under the effect for the rising edge signal of the output at described timer units, triggers input signal and is mapped to output Q end, the signal that the described clock source of output instruction is effective status using the signal of described inverter module output as D.
3. according to device claimed in claim 1, it is characterized in that, described clock source switching module further comprises the valid clock source collector unit, movable clock source determining unit and the clock source switch unit that connect successively, wherein:
Described valid clock source collector unit, collects all effective clock sources for the current state of each the road clock source from described clock source detection module output, and the call number of corresponding clock source is exported to described priority comparing unit;
Described priority comparing unit, for discover and seize priority and the weights priority of corresponding clock source according to the call number of clock source of input, the row major level of going forward side by side comparison, is appointed as the highest clock source of priority comparing the clock source of current active; If the priority of clock source that the described weights priority of the clock source of this current active is used higher than previous moment, is carried at the call number of the clock source of this current active and exports to described clock source switch unit in switching command;
Described clock source switch unit, for discovering and seizing the frequency signal of corresponding clock source according to the switching command of input, and switches to the clock source of previous moment activity the clock source of described current active.
4. according to the device described in claims 1 to 3 any one, it is characterized in that, also comprise the clock synchronization module being connected with described clock source switching module, wherein:
Described clock synchronization module, for switching the clock source of exporting as benchmark taking described clock source switching module, synchronous clock signal.
5. a method that realizes optical network unit switching clock source, comprising:
From all clock sources that will detect of described optical network unit, detect current effective clock source, described current effective clock source refers to that the frequency error of current time clock source is less than the clock source of default effective threshold value;
The priority of more all effective clock sources, clock source the highest priority is appointed as to the clock source of current active, the priority of the clock source using as previous moment lower than as described in when the priority of clock source of current active, be switched to the clock source of described current active;
From all clock sources that will detect of described optical network unit, detect current effective clock source, specifically comprise:
To each clock source in all clock sources that will detect, the frequency error of this clock source of current time detected, discover and seize the effective threshold value default into this clock source according to the call number of this clock source, more described frequency error and effectively threshold value, whether effectively level signal of this clock source of output current time; The effective level signal of this clock source of the current time of output is remained to after the shortest stabilizing time of this clock source to the current effective signal of output this clock source of instruction.
6. in accordance with the method for claim 5, it is characterized in that,
When clock source the highest priority is appointed as to the clock source of current active, the weights priority of clock source the highest priority is defined as to the priority of the clock source of described current active.
7. according to the method described in claim 5 to 6 any one, it is characterized in that, be switched to after the clock source of described current active, taking the clock source of described current active as benchmark, synchronous clock signal.
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| CN201010213111.2A CN101860430B (en) | 2010-06-24 | 2010-06-24 | Device and method for implementing optical network unit switching clock source |
| PCT/CN2010/077419 WO2011160351A1 (en) | 2010-06-24 | 2010-09-28 | Clock source switching device and method for optical network unit |
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| CN201010213111.2A CN101860430B (en) | 2010-06-24 | 2010-06-24 | Device and method for implementing optical network unit switching clock source |
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| CN101192913A (en) * | 2007-08-08 | 2008-06-04 | 中兴通讯股份有限公司 | A system and method for clock synchronization and clock switch over optical transmission network |
| CN101272255A (en) * | 2007-03-21 | 2008-09-24 | 乐金电子（昆山）电脑有限公司 | Method and device for proxy response to equipment connected to network |
| CN101707505A (en) * | 2008-08-13 | 2010-05-12 | 华为技术有限公司 | Method and device for time synchronization in passive optical network and passive optical network |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101272215B (en) * | 2007-03-20 | 2012-07-04 | 中兴通讯股份有限公司 | Optical transmission unit frame generating method and device, method and device for transmitting clock rank |
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2010
- 2010-06-24 CN CN201010213111.2A patent/CN101860430B/en not_active Expired - Fee Related
- 2010-09-28 WO PCT/CN2010/077419 patent/WO2011160351A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101272255A (en) * | 2007-03-21 | 2008-09-24 | 乐金电子（昆山）电脑有限公司 | Method and device for proxy response to equipment connected to network |
| CN101192913A (en) * | 2007-08-08 | 2008-06-04 | 中兴通讯股份有限公司 | A system and method for clock synchronization and clock switch over optical transmission network |
| CN101707505A (en) * | 2008-08-13 | 2010-05-12 | 华为技术有限公司 | Method and device for time synchronization in passive optical network and passive optical network |
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| Publication number | Publication date |
|---|---|
| WO2011160351A1 (en) | 2011-12-29 |
| CN101860430A (en) | 2010-10-13 |
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