CN101860430A - Device and method for implementing optical network unit switching clock source - Google Patents
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Abstract
The invention discloses a device and a method for implementing an optical network unit switching clock source. The device comprises a clock source detection module and a clock source switching module which are connected in turn, wherein the clock source detection module detects current valid clock sources from all to-be-detected multi-path clock sources of an optical network unit, and the current valid clock sources mean that signal frequency errors of the clock sources at the current moment are smaller than a preset valid threshold value; and the clock source switching module compares the priorities of all the valid clock sources, specifies the clock source with the highest priority as the current active clock source, and switches the clock source into the current active clock source when the priority of the clock source used at the previous moment is lower than that of the current active clock source. The device and the method overcome the defects that the conventional ONU system has higher cost and is complex, and greatly improve the reliability of the ONU system.
Description
Technical field
The Clock Synchronization Technology that the present invention relates to communicate by letter relates in particular to the device and method of realizing optical network unit (ONU, Optical Network Unit) switching clock source.
Background technology
Continuous growth along with various communication services, in order to satisfy the demand of user to the different communication business, ONU needs to switch common clock source such as 1PPS (pulse per second (PPS)) clock source, 8K light path clock source, 25M synchronous Ethernet clock source etc. to a plurality of clocks source.ONU user can forbid or enable one or more clocks source, distributes a priority also can for each clock source, offers the foundation that ONU selects the clock source automatically.Follow-up clock synchronization circuit is sent in clock source after ONU switches, as digital phase-locked loop (DPLL, Digital Phase Locked Loop), and the signal of the various frequencies that the generation user needs.
And ONU can not simply indiscriminately imitate the operation method in single clock source when the switching that realizes a plurality of clocks source.ONU is to the mode disunity of detection of a plurality of clocks source and switching at present, and the ONU that has piles up chip or the circuit that single clock source is adopted simply, causes the cost of ONU to improve, and the complexity of system increases, and the reliability of system reduces.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method and device of realizing optical network unit switching clock source, can reliably switch a plurality of clocks source, reduces system cost and complexity.
In order to solve the problems of the technologies described above, the invention provides a kind of device of realizing optical network unit switching clock source, comprise the clock source detection module and the clock source switching module that connect successively; Wherein:
Clock source detection module is used for from optical network unit that all the multipath clock sources that will detect detect current effective clock source, and described current effective clock source is meant that the signal frequency error in current time clock source is less than default effective threshold value;
Clock source switching module, be used for the relatively priority in all effective clock sources, the clock source of current active is appointed as in the clock source that priority is the highest, when the priority in the clock source that previous moment is used is lower than the priority in clock source of current active, switches to the clock source of current active.
Further, each clock source detection sub-module of a plurality of clocks source detection sub-module correspondingly detects each clock source, road in the multipath clock source in the detection module of clock source.
Further, clock source detection sub-module further comprises frequency error detection unit, holding unit and state indicating member, wherein:
The frequency error detection unit is used for according to the frequency error in detected current time clock source and described effective threshold value of discovering and seizing according to the call number in clock source, and effectively whether this clock source of output current time level signal;
Holding unit after being used for this effective level signal in clock source of current time to frequency error detection unit output and remaining to the shortest stabilization time in this clock source, is exported a triggering signal;
The state indicating member is used under the effect of triggering signal, and according to the effective level signal in clock source of frequency error detection unit output, output telltable clock source is the signal of effective status.
Further, holding unit realizes that by a timer units state indicating member is by an inverter module and a d type flip flop unit realization, wherein:
Timer units, this effective level signal in clock source of current time that is used for frequency error detection unit output is that enable signal is counted, then export a rising edge signal the shortest stabilization time of waiting to count down to this clock source;
Inverter module is used for the whether effectively anti-phase output of level signal of the current time clock source of frequency error detection unit output;
The d type flip flop unit is used under the effect of the rising edge signal of the output of timer units, the signal of inverter module output is triggered input signal as D be mapped to output Q end, and output telltable clock source is the signal of effective status.
Further, clock source switching module further comprises valid clock source collector unit, movable clock source determining unit and the clock source switch unit that connects successively, wherein:
The valid clock source collector unit is used for from all effective clock sources of current state collection in each clock source, road of clock source detection module output, and the call number in corresponding clock source is exported to the priority comparing unit;
The priority comparing unit is used for discovering and seizing the priority and the weights priority in corresponding clock source according to the call number in the clock source of importing, and the row major level of going forward side by side relatively is appointed as the highest clock source of priority that compares in the clock source of current active; If the weights priority in the clock source of this current activity is higher than the priority in the clock source of previous moment use, the call number in clock source that then will this current activity is carried at exports to clock source switch unit in the switching command;
Clock source switch unit is used for discovering and seizing the frequency signal in corresponding clock source according to the switching command of input, and the clock source of previous moment activity is switched to the clock source of current active.
Further, also comprise the clock synchronization module that is connected with clock source switching module, wherein:
Clock synchronization module, being used for switching the clock source of exporting with clock source switching module is benchmark, synchronously clock signal.
In order to solve the problems of the technologies described above, the invention provides a kind of method that realizes optical network unit switching clock source, comprising:
Detect current effective clock source from optical network unit all the clock sources that will detect, current effective clock source is meant the clock source of the frequency error in current time clock source less than default effective threshold value;
The priority in all effective clock sources relatively, the clock source of current active is appointed as in the clock source that priority is the highest, when the priority in the clock source of using as previous moment is lower than the priority in clock source of current active, switches to the clock source of current active.
Further, detect current effective clock source all the clock sources that will detect, specifically comprise from optical network unit:
To each the clock source in all the clock sources that will detect, detect the frequency error in this clock source of current time, discovering and seizing according to the call number in this clock source is effective threshold value that preset in this clock source, the effective threshold value of comparison frequency sum of errors, effectively whether this clock source of output current time level signal; After this effective level signal in clock source of current time of output remained to the shortest stabilization time in this clock source, this clock source current effective signal of output indication.
Further,
When the clock source of current active was appointed as in the clock source that priority is the highest, the weights priority in the clock source that priority is the highest was defined as the priority in the clock source of current active.
Further, switch to the clock source of current active after, be benchmark with the clock source of current active, clock signal synchronously.
The present invention is owing to make ONU judge clock source validity with uniform way, therefore do not need ONU to use the chip or the circuit in polytype clock source to come the various clocks of processing selecting source, overcome the higher and complicated defective of conventional ONU system cost, improved the reliability of ONU system greatly.
Description of drawings
Fig. 1 is the structural representation of the device embodiment of realization optical network unit switching clock source of the present invention;
Fig. 2 is the electrical block diagram of clock source detection module embodiment among the device embodiment shown in Figure 1;
Fig. 3 is the electrical block diagram of clock source switching module embodiment among the device embodiment shown in Figure 1;
Fig. 4 carries out the state flow schematic diagram that switch in the clock source for clock source switching module embodiment shown in Figure 3;
Fig. 5 is the flow chart of the method embodiment of realization optical network unit switching clock source of the present invention.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment technical scheme of the present invention is at length set forth.The embodiment that below exemplifies only is used for description and interpretation the present invention, and does not constitute the restriction to technical solution of the present invention.
Its structure of device embodiment of realization optical network unit switching clock source provided by the invention as shown in Figure 1, this device 10 comprises successively clock source detection module 11 and the clock source switching module 12 that connects; Wherein:
Clock source detection module 11 is used for from the ONU system that all the clock sources that will detect detect current effective clock source, and current effective clock source is meant that the signal frequency error in current time clock source is less than default effective threshold value;
Clock source detection module 11 correspondingly detects the multipath clock source by a plurality of clocks source detection sub-module (detection sub-module 1～clock source, clock source detection sub-module M), as shown in Figure 1, each the clock source, road that promptly converges to ONU all is furnished with an independent clock source detection sub-module and detects its validity.
Clock source switching module 12, be used for the relatively priority in all effective clock sources, the clock source of current active is appointed as in the clock source that priority is the highest, when the priority in the clock source that previous moment is used is lower than the priority in clock source of current active, switches to the clock source of current active.
The device embodiment of above-mentioned realization optical network unit switching clock source also comprises the clock synchronization module 13 that is connected with clock source switching module 12, and the clock source that is used for clock source switching module 12 outputs is a benchmark, synchronously clock signal.
The DPLL circuit also can be sent in the clock source of clock source switching module 12 outputs, the signal of the various frequencies that the generation user needs.
Fig. 2 has represented the circuit structure of each the clock source detection sub-module embodiment in the clock source detection module 11 shown in Figure 1, comprising: frequency error detection unit 111, timer units 112, inverter module 113, d type flip flop unit 114; Wherein:
Frequency error detection unit 111 is used for according to the frequency error in detected input clock source and the effective threshold value and the invalid threshold value in this clock source of presetting, and effectively whether this clock source of output current time level signal;
The frequency error that detects the clock source when frequency error detection unit 111 output low level 0 during less than effective threshold value of setting represents that this moment clock source is effective; The frequency error that detects the clock source when frequency error detection unit 111 is output high level 1 during more than or equal to the invalid threshold value set, represents that this moment clock source is invalid.
The effect of timer units 112 is to prevent that the state in clock source from switching between effective status and disarmed state continually and cause d type flip flop unit 114 outputs (being the detection sub-module output of whole clock source) instability.
For example detect the clock source at this moment effective and output low level 0, the then just anti-phase output high level 1 of inverter module 113 when frequency error detection unit 111.
D type flip flop unit 114 is used under the effect of the rising edge signal that the T of timer units 112 end is exported, and the signal that inverter module 113 is exported is mapped to the output of Q end as D triggering input signal, represents whether the present clock source is effective.
For example d type flip flop unit 114 is under the effect of the rising edge signal of exporting at the T of timer units 112 end, and the high level 1 that inverter module 113 is exported copies to the output of Q end, and expression current time clock source is effective.
Below clock source detection sub-module embodiment shown in Figure 2 is explained the testing process expansion of the clock source validity of input.
Frequency error detection unit 111 finds corresponding configuration attribute call number at first according to the call number in the clock source of importing, and is as shown in table 1; Then according to the configuration attribute call number of discovering and seizing, find the clock signal frequency and the configuration attribute of this clock source correspondence, as shown in table 2, wherein the configuration attribute in clock source comprises: priority, weights priority, effective threshold value (inner tolerance), the shortest stabilization time (validation timer) and invalid threshold value (outer tolerance).
The configuration attribute index in table 1 clock source
| Clock source index | The clock source name | Whether the clock source is enabled | The configuration attribute index |
| ??0 | GPS1 clock source | Be | ??0 |
| ??1 | GPS2 clock source | Be | ??1 |
| ??2 | Light path clock source | Be | ??2 |
| ??3 | The synchronous Ethernet clock source | Be | ??3 |
The configuration attribute in table 2 clock source
| The configuration attribute index | Signal frequency | Priority | Weights priority | Effective threshold value | The shortest stabilization time | Invalid threshold value |
| ??0 | ??1PPS | ??0 | ??0 | ??100ppm | ??5S | ??1000ppm |
| ??1 | ??1PPS | ??1 | ??0 | ??100ppm | ??5S | ??1000ppm |
| The configuration attribute index | Signal frequency | Priority | Weights priority | Effective threshold value | The shortest stabilization time | Invalid threshold value |
| ??2 | ??8K | ??2 | ??1 | ??50ppm | ??5S | ??150ppm |
| ??3 | ??25M | ??3 | ??2 | ??50ppm | ??5S | ??150ppm |
Annotate: " PPS " expression pulse per second (PPS) in the table 2, " ppm " expression 1,000,000/.
Explained later is difference and its effect of the invalid threshold value of effective threshold value in the clock source that provides of present embodiment once.Under previous moment clock source is invalid situation, when the signal frequency error in this moment clock source must be less than effective threshold value in clock source, can think that just this moment clock source is effectively (no-faulted); And be under the effective situation in previous moment clock source, when the signal frequency error in this moment clock source must be greater than the invalid threshold value in clock source, can think that just this moment clock source is invalid (faulted).
The invalid threshold value in clock source that the embodiment of the invention provides is greater than the effective threshold value in clock source.
For example, when the clock source of input is the GPS1 clock source shown in the table 1, its clock source call number is 0, finding its configuration attribute call number in view of the above also is 0, finding the signal frequency in this clock source according to the configuration attribute call number is 1PPS (pulse per second (PPS)), effective threshold value in this clock source, invalid threshold value are respectively 100ppm and 1000ppm, and be 5S the shortest stabilization time in this clock source.
Suppose that frequency error detection unit 111 is 750ppm in this clock source frequency error that this measures constantly, if previous moment GPS1 clock source is effective, owing to the invalid threshold value 1000ppm of frequency error 750ppm less than the clock source, then this moment GPS1 clock source still effectively so; And if previous moment GPS1 clock source is invalid, owing to the effective threshold value 100ppm of frequency error 750ppm greater than the clock source, then this moment GPS1 clock source also will be invalid.
It is invalid that frequency error detection unit 111 detects the clock source of input at any one time, just export high level 1, when frequency error detection unit 111 at any one time becomes high level 1 (clock source from effectively to invalid) or output high level 1 by low level 0, timer units 112 all can reset.
It is effective that frequency error detection unit 111 detects the clock source of input at any one time, just output low level 0, make timer units 112 begin counting thus, after counting down to clock source the shortest stabilization time (as 5S), the T of timer units 112 end can output one from low level 0 to high level 1 rising edge signal; And inverter module 113 is exported high level 1 when frequency error detection unit 111 output low levels 0, finally makes the output (Q pin) of d type flip flop unit 114 export high level, and expression present clock source is effective.
Clock source detection sub-module shown in Figure 2 only is one of embodiment, and it is all realized by hardware circuit basically.In fact, the present invention also can exemplify out other embodiment except the foregoing description.For example, what the timer units 112 shown in Fig. 2 played is the effect of a holding unit, promptly the effective level signal in 111 output clock sources, frequency error detection unit is remained to the clock source and export a triggering signal after the shortest stabilization time, it also can be realized by the mode of software delay certainly.Again for example, inverter module 112 and d type flip flop unit 114 are combined, played the effect of a state indicating member, it exports the state through the clock source that keeps handling under the effect of the triggering signal of holding unit, certainly it also can constitute by other form, for example passes through the trigger of other form etc.In a word, the effect essence of circuit any with shown in Figure 2 is identical but other circuit retouching distortion a little all should be within protection scope of the present invention.
Fig. 3 is the circuit structure of clock source switching module 12 embodiment among the device embodiment shown in Figure 1, comprises the valid clock source collector unit 121, movable clock source determining unit 122 and the clock source switch unit 123 that connect successively, wherein:
Valid clock source collector unit 121 is used for collecting all from the current state in each clock source, road that clock source detection module 11 is exported and is in the clock source of effective status, and the call number in corresponding clock source is exported to priority comparing unit 122;
Priority comparing unit 122 is used for discovering and seizing the priority and the weights priority in corresponding clock source according to the call number in the clock source of importing, and the row major level of going forward side by side relatively is appointed as the highest clock source of priority that compares in (active) clock source of current active; If the weights priority in the clock source of this current activity is higher than the priority in the clock source of previous moment use, then the call number in the clock source of activity is carried at and exports to clock source switch unit 123 in the switching command;
Discover and seize the priority and the weights priority in corresponding clock source in the configuration attribute in the clock source of priority comparing unit 122 from table 2.
Clock source switch unit 123 is used for discovering and seizing the frequency signal in corresponding clock source according to the switching command of input, and the clock source of previous moment activity is switched to the clock source of current active.
Discover and seize the frequency signal in corresponding clock source in the configuration attribute of clock source switch unit 123 according to the clock source of call number from table 2 in the clock source of carrying in the switching command.
Fig. 4 is that clock source switching module embodiment shown in Figure 3 determines and switch the clock source state flow graph of current time activity, the current time state in each clock source, road of clock source switching module receive clock source detection module 11 outputs is therefrom collected the clock source that all are in effective status.
The explained later clock source priority that provides of the embodiment of the invention and the difference and the effect of weights priority once.The scope of the priority in clock source and weights priority all is from 0 to 3.Wherein, 0 expression priority is the highest, and 3 expression priority are minimum.Be in the clock source of effective status at all, the clock source that priority is the highest will be designated as the clock source of current time activity.When a clock source was designated as movable clock source, its priority just was set to its weights priority.The effect of weights priority is, when clock source, a certain road is designated as movable clock source, can be that a more higher leveled priority is set in this clock source, and purpose is for fear of switching clock source continually equally.
In all valid clock sources, a certain moment has only the clock source of an activity, and this movable clock source can be outputed to clock source synchronization module by clock source switching module and carry out follow-up processing.
For example among Fig. 4, A is GPS1 clock source, and B is GPS2 clock source, and C is light path clock source, and D is the synchronous Ethernet clock source.The priority in each clock source is respectively 0,1,2,3, and weights priority should be 0,0,1,2 mutually.Suppose a certain moment, A, B clock source all are invalid, and then C is designated as movable clock source; Again after a period of time, B clock source has become effective status from disarmed state, if there is not weights priority, then B clock source can be designated as movable clock source, because the priority 1 of B is higher than the priority 2 of C.But because C is current time activity (in the use) clock source, its weights priority is 1, and it equates with the priority 1 of B, so the still movable clock source of C.Fig. 4 has at length drawn the corresponding state transition diagram when weights priority and no weights priority are arranged.
The present invention is directed to said apparatus embodiment, a kind of method embodiment that realizes optical network unit switching clock source correspondingly is provided, its flow process comprises the steps: as shown in Figure 5
110, detect current effective clock source from the ONU system all the clock sources that will detect;
Current effective clock source is meant that the signal frequency error in current time clock source is less than default effective threshold value.
120, the priority in all effective clock sources relatively, the clock source of current active is appointed as in the clock source that priority is the highest;
130, whether the priority of judging the clock source that previous moment is used less than the priority in the clock source of current active, is then to carry out next step, otherwise process ends;
When specifying the clock source of current active, the weights priority in this appointed clock source is decided to be its priority, if judge the priority of the priority in the clock source that previous moment is used less than the clock source of this current activity, then determines to carry out the switching in clock source.
140, the clock source that previous moment is used switches on the clock source of current active.
After step 140, also comprise:
To switch the clock source of exporting is benchmark, synchronously clock signal.
One of ordinary skill in the art will appreciate that all or part of step in the said method can instruct related hardware to finish by program, described program can be stored in the computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of the foregoing description also can use one or more integrated circuits to realize.Correspondingly, each the module/unit in the foregoing description can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. a device of realizing optical network unit switching clock source comprises the clock source detection module and the clock source switching module that connect successively; Wherein:
Described clock source detection module is used for from optical network unit that all the multipath clock sources that will detect detect current effective clock source, and described current effective clock source is meant that the signal frequency error in current time clock source is less than default effective threshold value;
Described clock source switching module, be used for the relatively priority in all effective clock sources, the clock source of current active is appointed as in the clock source that priority is the highest, when the priority in the clock source that previous moment is used is lower than the priority in clock source of current active, switch to the clock source of current active.
2. according to the described device of claim 1, it is characterized in that each clock source detection sub-module of a plurality of clocks source detection sub-module correspondingly detects each the clock source, road in the described multipath clock source in the detection module of described clock source.
3. according to the described device of claim 2, it is characterized in that described clock source detection sub-module further comprises frequency error detection unit, holding unit and state indicating member, wherein:
Described frequency error detection unit is used for according to the frequency error in detected described current time clock source and described effective threshold value of discovering and seizing according to the call number in described clock source, and effectively whether this clock source of output current time level signal;
Described holding unit after being used for this effective level signal in clock source of described current time to described frequency error detection unit output and remaining to the shortest stabilization time in this clock source, is exported a triggering signal;
Described state indicating member is used under the effect of described triggering signal, and according to the effective level signal in described clock source of described frequency error detection unit output, the described clock of output indication source is the signal of effective status.
4. according to the described device of claim 3, it is characterized in that described holding unit realizes that by a timer units described state indicating member is by an inverter module and a d type flip flop unit realization, wherein:
Described timer units, this effective level signal in clock source of current time that is used for described frequency error detection unit output is that enable signal is counted, then export a rising edge signal the shortest stabilization time of waiting to count down to this clock source;
Described inverter module is used for the whether effectively anti-phase output of level signal of the current time clock source of described frequency error detection unit output;
Described d type flip flop unit is used under the effect of the rising edge signal of the output of described timer units, the signal of described inverter module output is triggered input signal as D be mapped to output Q end, and the described clock of output indication source is the signal of effective status.
5. according to the described device of claim 1, it is characterized in that described clock source switching module further comprises valid clock source collector unit, movable clock source determining unit and the clock source switch unit that connects successively, wherein:
Described valid clock source collector unit is used for from all effective clock sources of current state collection in each clock source, road of described clock source detection module output, and the call number in corresponding clock source is exported to described priority comparing unit;
Described priority comparing unit is used for discovering and seizing the priority and the weights priority in corresponding clock source according to the call number in the clock source of importing, and the row major level of going forward side by side relatively is appointed as the highest clock source of priority that compares in the clock source of current active; If the described weights priority in the clock source of this current activity is higher than the priority in the clock source of previous moment use, the call number in clock source that then will this current activity is carried at exports to described clock source switch unit in the switching command;
Described clock source switch unit is used for discovering and seizing the frequency signal in corresponding clock source according to the switching command of input, and the clock source of previous moment activity is switched to the clock source of described current active.
6. according to each described device of claim 1 to 5, it is characterized in that, also comprise the clock synchronization module that is connected with described clock source switching module, wherein:
Described clock synchronization module, being used for switching the clock source of exporting with described clock source switching module is benchmark, synchronously clock signal.
7. method that realizes optical network unit switching clock source comprises:
Detect current effective clock source from described optical network unit all the clock sources that will detect, described current effective clock source is meant the clock source of the frequency error in current time clock source less than default effective threshold value;
The priority in all effective clock sources relatively, the clock source of current active is appointed as in the clock source that priority is the highest, as described in being lower than, the priority in the clock source of using as previous moment during the priority in the clock source of current active, switches to the clock source of described current active.
8. in accordance with the method for claim 7, it is characterized in that, detect current effective clock source all the clock sources that will detect, specifically comprise from described optical network unit:
To each the clock source in all the clock sources that will detect, detect the frequency error in this clock source of current time, discovering and seizing according to the call number in this clock source is effective threshold value that preset in this clock source, more described frequency error and effective threshold value, effectively whether this clock source of output current time level signal; After this effective level signal in clock source of current time of output remained to the shortest stabilization time in this clock source, this clock source current effective signal of output indication.
9. in accordance with the method for claim 7, it is characterized in that,
When the clock source of current active was appointed as in the clock source that priority is the highest, the weights priority in the clock source that priority is the highest was defined as the priority in the clock source of described current active.
10. according to each described method of claim 7 to 9, it is characterized in that, switch to the clock source of described current active after, be benchmark with the clock source of described current active, clock signal synchronously.
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| CN201010213111.2A CN101860430B (en) | 2010-06-24 | 2010-06-24 | Device and method for implementing optical network unit switching clock source |
| PCT/CN2010/077419 WO2011160351A1 (en) | 2010-06-24 | 2010-09-28 | Clock source switching device and method for optical network unit |
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| CN201010213111.2A CN101860430B (en) | 2010-06-24 | 2010-06-24 | Device and method for implementing optical network unit switching clock source |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263633A (en) * | 2011-08-29 | 2011-11-30 | 杭州华三通信技术有限公司 | Clock synchronization method and stacking controller for switch stacking system |
| CN102833026A (en) * | 2012-08-31 | 2012-12-19 | 华为技术有限公司 | Clock tracking method, system and network element |
| CN103135709A (en) * | 2012-05-15 | 2013-06-05 | 北京泛华恒兴科技有限公司 | PXI (PCI eXtensions for Instrumentation) machine case and PXI testing system |
| CN103684733A (en) * | 2013-09-28 | 2014-03-26 | 国家电网公司 | Automatic verification method and special-purpose equipment for clock synchronization |
| CN104682362A (en) * | 2015-03-06 | 2015-06-03 | 南方电网科学研究院有限责任公司 | Control method for automatically selecting effective signal |
| CN106685566A (en) * | 2016-12-31 | 2017-05-17 | 上海远景数字信息技术有限公司 | Clock source selection method and clock server |
| CN106712880A (en) * | 2015-11-12 | 2017-05-24 | 上海远景数字信息技术有限公司 | Communication management system |
| CN107070579A (en) * | 2017-05-16 | 2017-08-18 | 中国船舶重工集团公司第七0九研究所 | Three-level time server is controlled and fault-tolerance approach |
| CN107749787A (en) * | 2017-09-27 | 2018-03-02 | 全球能源互联网研究院有限公司 | Synchronizing signal generating method, apparatus and system |
| CN107861412A (en) * | 2017-09-27 | 2018-03-30 | 全球能源互联网研究院有限公司 | Signal acquisition method, apparatus and system |
| WO2018161282A1 (en) * | 2017-03-08 | 2018-09-13 | 华为技术有限公司 | Clock synchronization method and apparatus and passive optical network system |
| CN114448398A (en) * | 2020-11-02 | 2022-05-06 | 圣邦微电子（北京）股份有限公司 | Battery protection chip, multi-delay clock chain multiplexing circuit and method thereof |
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| CN101272255A (en) * | 2007-03-21 | 2008-09-24 | 乐金电子（昆山）电脑有限公司 | Method and device for proxy response to equipment connected to network |
| CN101192913A (en) * | 2007-08-08 | 2008-06-04 | 中兴通讯股份有限公司 | A system and method for clock synchronization and clock switch over optical transmission network |
| CN101707505A (en) * | 2008-08-13 | 2010-05-12 | 华为技术有限公司 | Method and device for time synchronization in passive optical network and passive optical network |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263633B (en) * | 2011-08-29 | 2014-10-22 | 杭州华三通信技术有限公司 | Clock synchronization method and stacking controller for switch stacking system |
| CN102263633A (en) * | 2011-08-29 | 2011-11-30 | 杭州华三通信技术有限公司 | Clock synchronization method and stacking controller for switch stacking system |
| CN103135709A (en) * | 2012-05-15 | 2013-06-05 | 北京泛华恒兴科技有限公司 | PXI (PCI eXtensions for Instrumentation) machine case and PXI testing system |
| CN103135709B (en) * | 2012-05-15 | 2016-03-30 | 北京泛华恒兴科技有限公司 | PXI cabinet and PXI test macro |
| CN102833026A (en) * | 2012-08-31 | 2012-12-19 | 华为技术有限公司 | Clock tracking method, system and network element |
| CN102833026B (en) * | 2012-08-31 | 2015-09-09 | 华为技术有限公司 | A kind of clock tracing method, system and network element |
| CN103684733A (en) * | 2013-09-28 | 2014-03-26 | 国家电网公司 | Automatic verification method and special-purpose equipment for clock synchronization |
| CN104682362A (en) * | 2015-03-06 | 2015-06-03 | 南方电网科学研究院有限责任公司 | Control method for automatically selecting effective signal |
| CN106712880B (en) * | 2015-11-12 | 2019-06-04 | 上海东土远景工业科技有限公司 | A kind of communication management system |
| CN106712880A (en) * | 2015-11-12 | 2017-05-24 | 上海远景数字信息技术有限公司 | Communication management system |
| CN106685566A (en) * | 2016-12-31 | 2017-05-17 | 上海远景数字信息技术有限公司 | Clock source selection method and clock server |
| WO2018161282A1 (en) * | 2017-03-08 | 2018-09-13 | 华为技术有限公司 | Clock synchronization method and apparatus and passive optical network system |
| CN107070579A (en) * | 2017-05-16 | 2017-08-18 | 中国船舶重工集团公司第七0九研究所 | Three-level time server is controlled and fault-tolerance approach |
| CN107749787A (en) * | 2017-09-27 | 2018-03-02 | 全球能源互联网研究院有限公司 | Synchronizing signal generating method, apparatus and system |
| CN107861412A (en) * | 2017-09-27 | 2018-03-30 | 全球能源互联网研究院有限公司 | Signal acquisition method, apparatus and system |
| CN114448398A (en) * | 2020-11-02 | 2022-05-06 | 圣邦微电子（北京）股份有限公司 | Battery protection chip, multi-delay clock chain multiplexing circuit and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101860430B (en) | 2014-08-13 |
| WO2011160351A1 (en) | 2011-12-29 |
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