CN114448398A - Battery protection chip, multi-delay clock chain multiplexing circuit and method thereof - Google Patents
Battery protection chip, multi-delay clock chain multiplexing circuit and method thereof Download PDFInfo
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- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 7
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 4
- 229910052744 lithium Inorganic materials 0.000 description 4
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- 229910001416 lithium ion Inorganic materials 0.000 description 1
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- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
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Abstract
The invention discloses a battery protection chip, a multi-delay clock chain multiplexing circuit and a method thereof, wherein the circuit comprises: the clock selection and reset module is used for outputting an effective reset signal when a new trigger protection item with higher corresponding priority is effective, and selecting and outputting one of a plurality of basic clock signals according to corresponding delay requirements; the delay clock chain multiplexing module is used for resetting the delay clock chain when an effective reset signal is received, controlling the delay clock chain to carry out delay timing according to the received basic clock signal, and outputting an execution signal with a first level state when a timing value reaches a corresponding threshold value; and the protection detection module is used for detecting the level states of the trigger execution signals and the release execution signals and outputting a plurality of protection signals according to the detection result. The invention can realize the time delay timing of triggering and releasing a plurality of protection items based on the same time delay clock link, and is beneficial to reducing power consumption and realizing the miniaturization of a chip.
Description
Technical Field
The invention relates to the technical field of batteries, in particular to a battery protection chip, a multi-delay clock chain multiplexing circuit and a multi-delay clock chain multiplexing method.
Background
With the development of society and the continuous consumption of petrochemical energy, people are actively searching for new energy to replace the petrochemical energy which is exhausted in the whole day. Electric energy is one of ideal substitutes for petrochemical energy, so the demand of people for electric energy is higher and higher in recent years. With the development and popularization of unmanned electronic equipment, portable digital equipment, electric tools, electric vehicles and the like, the power core, namely a storage battery, is receiving more and more attention. The lithium battery is favored by manufacturers due to the advantages of high specific energy, long cycle life, small self-discharge, no memory effect, environmental protection and the like, and is one of the hot spots of power battery research.
In the normal use process of a battery (such as a lithium ion battery), the internal part of the battery performs chemical positive reaction of mutual conversion of electric energy and chemical energy, but under certain conditions, such as overcharge and overdischarge of the battery can cause chemical side reactions in the battery, the side reactions can seriously affect the performance and the service life of the battery after being aggravated, and a large amount of gas can be generated, so that the internal pressure of the battery is rapidly increased and then explodes to cause safety problems, therefore, a protection circuit needs to be configured for effectively monitoring the charging and discharging states of the battery, and a charging and discharging loop is turned off under certain conditions to prevent the battery from being damaged.
In the lithium battery protection chip, certain delay time is required for detection and release of protection states, in order to ensure independence of protection trigger delay, an original clock is generally generated inside a circuit, preliminary frequency division is carried out to generate basic clocks with different frequencies, each protection judgment module respectively adopts different frequency basic clocks which are required by each protection judgment module, and frequency division delay timing is carried out inside the module again. Although the method can effectively ensure that the timing of each protection judgment module is discrete and does not influence each other, certain area overhead and power consumption waste exist.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a battery protection chip, a multi-delay clock chain multiplexing circuit and a multi-delay clock chain multiplexing method thereof, which can realize delay timing of triggering and releasing a plurality of protection items based on the same delay clock chain, and are beneficial to reducing power consumption and realizing chip miniaturization.
In one aspect, the present invention provides a multi-delay clock chain multiplexing circuit for a battery protection chip, including: the clock selection and reset module is used for receiving a protection trigger indication signal, a plurality of basic clock signals, a plurality of trigger indication signals corresponding to a plurality of protection items and a plurality of release indication signals, comparing the priority of the currently started protection item with the priority of the newly triggered protection item when the protection trigger indication signal is effective based on the priorities of the protection items, outputting a reset signal according to the comparison result, and selecting one of the basic clock signals meeting the delay requirement according to the detection result to output; a delay clock chain multiplexing module, connected to the clock selecting and resetting module, for receiving the reset signal and one of the plurality of basic clock signals, resetting the delay clock chain when receiving the valid reset signal, controlling the delay clock chain to perform delay timing according to the one of the plurality of basic clock signals meeting the delay requirement, and outputting an execution signal with a first level state when a timing value reaches a corresponding threshold value; a protection detection module, connected to the clock selection and reset module and the delayed clock chain multiplexing module respectively, for receiving an enable signal, the protection trigger indication signal, and a plurality of trigger signals, a plurality of release signals, a plurality of trigger execution signals and a plurality of release execution signals corresponding to the plurality of protection items, to detect the level states of the plurality of trigger signals, the plurality of release signals, the plurality of trigger execution signals, and the plurality of release execution signals when the enable signal and the protection trigger indication signal are valid, and outputs the plurality of trigger indication signals, the plurality of release indication signals and the plurality of protection signals according to the detection result, the clock selection and reset module outputs an effective reset signal when the priority of the newly triggered protection item is higher than that of the currently started protection item.
Optionally, the clock selection and reset module is further configured to trigger to output the valid reset signal on a previous rising edge or a falling edge on which the protection trigger indication signal is valid.
Optionally, the clock selecting and resetting module includes: the first priority judging subunit is used for comparing the priority of the currently opened protection item with the priority of the newly triggered protection item under the condition that the protection triggering indication signal is effective, and generating an interrupt signal when the priority of the newly triggered protection item is higher than the priority of the currently opened protection item; a pulse generating subunit, connected to the first priority determining subunit, and configured to generate the valid reset signal when receiving the interrupt signal; the second priority judging subunit is used for comparing the priority of the currently started protection item with the priority of the newly triggered protection item under the condition that the protection triggering indication signal is effective, and generating a selection signal according to the delay requirement corresponding to the newly triggered protection item when the priority of the newly triggered protection item is higher than the priority of the currently started protection item; and the one-out-of-multiple selector is connected with the second priority judging subunit and used for selecting the basic clock signal corresponding to the delay requirement of the newly triggered protection item to output when the selection signal is received.
Optionally, the delay clock chain multiplexing module includes: the clock end of each D flip-flop in the x D flip-flops receives one of the plurality of basic clock signals meeting the delay requirement, the reset end of each D flip-flop receives the reset signal, and the output end of the ith D flip-flop in the x D flip-flops outputs the execution signal, wherein x and i are positive integers, and i is greater than or equal to 1 and less than or equal to x.
Optionally, each of the plurality of trigger execution signals and the plurality of release execution signals corresponding to the plurality of protection items is output at an output terminal of a different D flip-flop among the x D flip-flops.
Optionally, at least a part of the execution signals of the trigger execution signals and the de-execution signals corresponding to the protection items are output from the output end of the same D flip-flop of the x D flip-flops.
Optionally, the protection detection module includes: and each protection detection unit receives a trigger signal, a release signal, a trigger execution signal and a release execution signal corresponding to a protection item, detects the level states of the trigger signal, the release signal, the trigger execution signal and the release execution signal when the enable signal and the protection trigger indication signal are effective, and outputs the trigger indication signal, the release indication signal and the protection signal corresponding to the protection item according to the detection result.
In another aspect, the present invention provides a battery protection chip, including: the multi-delay clock chain multiplexing circuit of the battery protection chip is disclosed.
In another aspect, a method for multiplexing a multi-delay clock chain of a battery protection chip according to the present invention includes: under the condition that the battery or the chip triggers protection, comparing the priority of the protection item which is started currently with the priority of the protection item which is triggered newly; when the priority of the newly triggered protection item is lower than that of the currently started protection item, continuing to perform delay timing on the currently started protection item based on the delay clock chain; when the priority of the newly triggered protection item is higher than that of the currently started protection item, resetting the delay clock chain, selecting a basic clock signal corresponding to the newly triggered protection item, and controlling the reset delay clock chain to perform delay timing according to the selected basic clock signal; and after the timing value reaches the corresponding threshold value, controlling to realize triggering or releasing of the corresponding protection item.
Optionally, before triggering protection, the method further includes: resetting the delayed clock chain.
The invention has the beneficial effects that: the invention discloses a battery protection chip, a multi-delay clock chain multiplexing circuit and a multi-delay clock chain multiplexing method thereof.A clock selection and reset module is adopted to reset a delay clock chain according to the priorities of a plurality of trigger indication signals and a plurality of release indication signals in a plurality of protection items before the release or trigger switching of different protection items, and a corresponding basic clock is selected as required, so that the delay timing of the triggering and release of the plurality of protection items can be realized based on the same delay clock chain in the delay clock chain multiplexing module. Because the same time delay clock chain is adopted for the time delay timing of triggering and releasing a plurality of protection items, and the time delay timing of triggering and releasing a plurality of protection items is not required to be respectively carried out through a plurality of time delay clock chains, the number of components required by the chip is effectively reduced, the power consumption and the cost are reduced, the occupation of the chip area is reduced, the miniaturization of the chip is favorably realized, and the requirements of low power consumption and area reduction of the lithium battery protection chip are met.
The reset of the delay clock chain is carried out before the protection triggering indication signal is effective (namely, protection triggering exists currently), so that inaccurate timing caused by the error of an initial timing position when the delay clock chain is adopted for carrying out long-time delay timing can be avoided, and the reliability of triggering or releasing all protection items is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 illustrates an exemplary operating circuit diagram of a battery protection chip provided according to an embodiment of the present disclosure;
fig. 2 shows a block diagram of a multi-delay clock chain multiplexing circuit of a battery protection chip according to an embodiment of the present disclosure;
fig. 3 is a block diagram illustrating a structure of a clock selection and reset module in a multi-delay clock chain multiplexing circuit according to an embodiment of the disclosure;
fig. 4 is a schematic diagram illustrating a circuit structure of a delay clock chain multiplexing module in a multi-delay clock chain multiplexing circuit according to an embodiment of the disclosure;
fig. 5 is a flowchart illustrating a multi-delay clock chain multiplexing method for a battery protection chip according to an embodiment of the disclosure.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 illustrates an exemplary operating circuit diagram of a battery protection chip provided according to an embodiment of the present disclosure.
As shown in fig. 1, the positive electrode of the battery is connected to the positive terminal EB + of the external charging source, and the positive electrode of the battery is connected to the power pin VDD of the battery protection chip 10 through the first resistor R1 to supply power to the battery protection chip 10; the pin VDD is grounded through a capacitor C1, and the first resistor R1 and the capacitor C1 form a low-pass filter to filter out high-frequency noise in the battery. The negative electrode of the battery is connected with a ground pin VSS of the battery protection chip 10 and then grounded, the negative electrode of the battery is connected with the source electrode of the discharge switch FET1, the drain electrode of the discharge switch FET1 is connected with the drain electrode of the charge switch FET2, the source electrode of the charge switch FET2 is connected with the negative electrode end EB-of the external charge source, and the positive electrode end EB + and the negative electrode end EB-of the external charge source are also power interfaces of an external circuit. The discharging switch control pin DO of the battery protection chip 10 is connected to the gate of the discharging switch FET1, and the charging switch control pin CO of the battery protection chip 10 is connected to the gate of the charging switch FET 2.
It is understood that the battery protection chip 10 further includes other components such as a voltage detection pin, a current detection pin, etc., which are respectively connected to corresponding locations of the circuit, and when the battery protection chip 10 detects that the chip or the circuit is triggered or released by protection through the voltage detection pin, a corresponding control signal is generated to control the discharge switch FET1 and/or the charge switch FET2 to be turned on or off according to the protection status.
Further, in the battery protection chip 10, since a certain delay time is required for triggering and releasing the protection state, a corresponding delay circuit (corresponding to the multi-delay clock chain multiplexing circuit herein) is further disposed inside the battery protection chip 10 to assist in generating the control signal. The multi-delay clock chain multiplexing circuit is described in detail with reference to specific embodiments.
Fig. 2 shows a block diagram of a multi-delay clock chain multiplexing circuit of a battery protection chip according to an embodiment of the present disclosure, fig. 3 shows a block diagram of a clock selection and reset module in the multi-delay clock chain multiplexing circuit according to the embodiment of the present disclosure, and fig. 4 shows a schematic circuit structure diagram of a delay clock chain multiplexing module in the multi-delay clock chain multiplexing circuit according to the embodiment of the present disclosure.
As shown in fig. 2, in the present embodiment, the multi-delay clock chain multiplexing circuit (for convenience of description, referred to as the multi-delay clock chain multiplexing circuit herein) of the battery protection chip includes: a clock selection and reset module 110, a delayed clock chain multiplexing module 120, and a protection detection module 130.
The input end of the clock selecting and resetting module 110 receives the protection trigger indication signal Prot, the plurality of basic clock signals, the plurality of trigger indication signals corresponding to the plurality of protection items, and the plurality of release indication signals, the clock selecting and resetting module 110 is configured to compare the priority of the currently turned-on protection item with the priority of the newly triggered protection item when the protection trigger indication signal Prot is valid based on the priorities of the plurality of protection items (including the priorities of the plurality of trigger indication signals and the plurality of release indication signals), output the reset signal rst at the first output end of the clock selecting and resetting module 110 according to the comparison result, and select one of the plurality of basic clock signals meeting the delay requirement as the target clock signal clk _ in to be output at the second output end of the clock selecting and resetting module 110 according to the detection result. When the priority of the newly triggered protection item is higher than the priority of the currently opened protection item, the clock selection and reset module 110 outputs an active reset signal rst.
In this embodiment, referring to fig. 3, the clock selecting and resetting module 110 includes a resetting control unit 111 and a clock selecting unit 112. The reset control unit 111 is configured to output an active or inactive reset signal rst at a first output terminal of the clock selection and reset module 110 based on a comparison result between a priority of a currently activated protection item and a priority of a newly triggered protection item when the protection trigger indication signal Prot is active. And the clock selecting unit 112 is configured to select, when the protection trigger indication signal Prot is valid, a basic clock signal meeting the delay requirement as the target clock signal clk _ in at the second output terminal of the clock selecting and resetting module 110 based on a comparison result of the priority of the currently turned-on protection item and the priority of the newly triggered protection item.
Further, the reset control unit 111 includes a first priority determination subunit 1111 and a pulse generation subunit 1112. The first priority determining subunit 1111 is configured to, in a case where the protection trigger indication signal Prot is valid, compare the priority of the currently-opened protection item with the priority of the newly-triggered protection item, and generate an interrupt signal when the priority of the newly-triggered protection item is higher than the priority of the currently-opened protection item. The pulse generating subunit 1112 is connected to the first priority determining subunit 1111 and configured to generate an active reset signal when receiving the interrupt signal.
The clock selection unit 112 includes a second priority determination subunit 1121 and a one-out-of-multiple selector 1122. The second priority determining subunit 1121 is configured to, under the condition that the protection triggering indication signal Prot is valid, compare the priority of the currently started protection item with the priority of the newly triggered protection item, and generate a selection signal according to the delay requirement of the corresponding newly triggered protection item when the priority of the newly triggered protection item is higher than the priority of the currently started protection item; the one-out-of-multiple selector 1122 is connected to the second priority determining subunit 1121, and is configured to select the basic clock signal corresponding to the delay requirement of the newly triggered protection item for output when receiving the selection signal.
Specifically, after a certain external protection item is triggered, the protection trigger indication signal Prot is switched to an active state, and the first priority determining subunit 1111 determines whether to interrupt the current count by comparing the priority of the currently-started delayed protection item with the priority of the newly-triggered protection item. If the interrupt is needed, an interrupt signal with a high level is output to the pulse generation subunit 1112, and an effective reset signal rst is generated to reset the delay clock chain, and the delay timing of the protection item with the delay started is ended. Meanwhile, the second priority determining subunit 1121 determines whether the basic clock signal needs to be adjusted by comparing the priorities of the currently-started delayed protection item and the newly-triggered protection item, and if the basic clock signal needs to be adjusted, generates a corresponding selection signal to instruct the one-out-of-multiple selector 1122 to close the basic clock channel corresponding to the currently-started protection item, and selects the basic clock channel corresponding to the protection item with the higher priority to be connected, and the newly-connected basic clock channel selects the target clock signal clk _ in meeting the requirement to control the reset delay clock chain to perform delay timing on the trigger indication signal or the release indication signal of the newly-triggered protection item with the higher priority. It can be understood that, if the priority of the currently-started delayed protection item is higher than the priority of the newly-triggered protection item, the pulse generation subunit 1112 outputs the reset signal rst in the inactive state, and the one-out-of-multiple selector 1122 also continues to communicate with the basic clock channel corresponding to the currently-started protection item, so that the delayed clock chain continues to perform the delayed timing on the currently-started protection item.
Further, the reset control unit 111 in the clock selection and reset module 110 is further configured to trigger to output the active reset signal rst on a previous rising edge or a falling edge where the protection trigger indication signal Prot is active. That is, when new protection is triggered after all protection items are released, the delay clock chain needs to be reset again, so that the reliability and accuracy of triggering or releasing all protection items can be ensured.
For example, for the convenience of understanding, the technical solution of the present disclosure will be described herein by taking three base clock signals (clk _ A, clk _ B, clk _ C) and five protection terms (ovp, uvp, occ, ocd, scp) as examples. But it is understood that:
1) in the present disclosure, the plurality of base clock signals includes, but is not limited to, a first base clock signal clk _ a, a second base clock signal clk _ B, and a third base clock signal clk _ C. In other embodiments of the present disclosure, two basic clock signals or more than three basic clock signals may also be used, which should be comprehensively considered according to different delay time requirements of different protection items, chip design requirements, cost requirements, and the like, which is not limited in the present disclosure. Meanwhile, the time precision (i.e., the period of each basic clock signal) corresponding to each basic clock signal in the plurality of basic clock signals is different, and the period selection of each basic clock signal is set according to specific actual requirements, which is not limited in the present invention. Further, the multiple basic clock signals may be generated simultaneously by an oscillator inside the chip, or one or a portion of the basic clock may be generated by the oscillator, and then the one or the portion of the basic clock may be divided to generate the remaining basic clock, which is not limited in the present invention.
2) In the present disclosure, the plurality of protection items include, but are not limited to, an overvoltage protection item ovp, an undervoltage protection item uvp, a charging overcurrent protection item occ, a discharging overcurrent protection item ocd, and a short-circuit protection item scp. In other embodiments of the present disclosure, a temperature protection item, such as a minimum temperature protection item, a maximum temperature protection item, and several protection items, such as power, operation time, and the like, may be further included, which is not limited by the present invention.
Further, in the present disclosure, an X _ en signal represents a trigger indication signal of a corresponding protection item in a plurality of protection items, and when the X _ en signal is in an active level state, it represents that the protection item is triggered and trigger delay timing is required; the X _ rls signal indicates a release instruction signal for a corresponding one of the plurality of protection items, and when the X _ rls signal is active, it indicates that the protection item is released, and a release delay timer is required. After the time delay reaches the corresponding threshold, the corresponding control signal is triggered and generated, and the on-off of the corresponding switch in the discharging switch FET1 and the charging switch FET2 shown in fig. 1 is controlled, so that the corresponding protection triggering or releasing is completed. For example, a trigger indication signal corresponding to the overvoltage protection item ovp is designated as ovp _ en, and a release indication signal corresponding to the overvoltage protection item ovp is designated as ovp _ rls; marking a trigger indicating signal corresponding to the undervoltage protection item uvp as uvp _ en, and marking a release indicating signal corresponding to the undervoltage protection item uvp as uvp _ rls; a trigger indication signal corresponding to the charging overcurrent protection item occ is recorded as occ _ en, and a release indication signal corresponding to the charging overcurrent protection item occ is recorded as occ _ rls; recording a trigger indicating signal corresponding to the discharging overcurrent protection item ocd as ocd _ en, and recording a release indicating signal corresponding to the discharging overcurrent protection item ocd as ocd _ rls; the trigger indication signal corresponding to the short-circuit protection term scp is denoted as scp _ en, and the release indication signal corresponding to the short-circuit protection term scp is denoted as scp _ rls. Similarly, in other embodiments of the present disclosure, similar expressions may be used for the trigger indication signal and the release indication signal of other protection items. Herein, X represents one of a plurality of protection items.
In this disclosure, except for special descriptions, optionally, the active level state of each signal may be all the first level state or a part of the first level state may be the first level state and a part of the first level state may be the second level state, and the first level state may be any one of the high level state and the low level state, and the corresponding second level is the other one of the high level state and the low level state, which is not limited in this disclosure.
The delay clock chain multiplexing module 120 is connected to the clock selecting and resetting module 110, and receives a reset signal and one of the plurality of basic clock signals, and is configured to reset the delay clock chain when receiving a valid reset signal, control the delay clock chain to perform delay timing according to the one of the plurality of basic clock signals meeting the delay requirement, and output an execution signal having a first level state when a timing value reaches a corresponding threshold value.
Referring to fig. 4, in this embodiment, the delay clock chain multiplexing module 120 includes: x D flip-flops (U1, U2,. eta., Ux-2, Ux-1, Ux) connected in series. The clock end CLK of each D flip-flop in the x D flip-flops receives one of a plurality of basic clock signals meeting the delay requirement, namely a target clock signal CLK _ in, the reset end RST of each D flip-flop receives a reset signal RST, and the input end D of each D flip-flop is connected with the output end Q of the previous D flip-flop. The input of the first D flip-flop receives a reference signal F0 (the reference signal F0 may be provided by any node voltage or signal in the chip that meets the level requirement), and the output of the ith D flip-flop Ui of the X D flip-flops outputs an execution signal X _ dly. Wherein x and i are both positive integers, and i is greater than or equal to 1 and less than or equal to x.
Further, in one embodiment of the present disclosure, in the multiple trigger execution signals and the multiple de-execution signals corresponding to the multiple protection items, each execution signal is output at an output terminal of a different D flip-flop of the x D flip-flops. Therefore, the independent triggering of a plurality of triggering execution signals and a plurality of releasing execution signals can be realized by reasonably setting the number of the D triggers and the output node position of the execution signal corresponding to each protection item, and the number of required basic clocks can be reduced.
In another embodiment of the present invention, at least a portion of the execution signals of the trigger execution signals and the de-execution signals corresponding to the protection items are output from the output terminal of the same D flip-flop of the x D flip-flops. Therefore, independent triggering of a plurality of trigger execution signals and a plurality of release execution signals can be realized by reasonably setting the number of the basic clocks and the period duration of each basic clock, and the number of the required D triggers can be further reduced.
It can be understood that, when the delay clock chain multiplexing module 120 delays the trigger indication signal corresponding to a protection item, the execution signal X _ dly output by the delay clock chain multiplexing module is the trigger execution signal X _ det _ dly corresponding to the protection item; when the delayed clock chain multiplexing module 120 delays the release indication signal corresponding to a protection item, the output execution signal X _ dly is the release execution signal X _ rls _ dly corresponding to the protection item. For example, the trigger execution signal corresponding to the over-voltage protection item ovp is denoted as V _ det _ dly, and the release execution signal corresponding to the over-voltage protection item ovp is denoted as ovp _ rls _ dly; marking the trigger execution signal corresponding to the under-voltage protection item uvp as V _ det _ dly, and marking the release execution signal corresponding to the under-voltage protection item uvp as uvp _ rls _ dly; recording a trigger execution signal corresponding to the charging overcurrent protection item occ as C _ det _ dly, and recording a release execution signal corresponding to the charging overcurrent protection item occ as occ _ rls _ dly; recording a trigger execution signal corresponding to the discharging overcurrent protection term ocd as C _ det _ dly, and recording a release execution signal corresponding to the discharging overcurrent protection term ocd as ocd _ rls _ dly; the trigger execution signal corresponding to the short-circuit protection term scp is denoted as scp _ det _ dly, and the release execution signal corresponding to the short-circuit protection term scp is denoted as scp _ rls _ dly. Similarly, in other embodiments of the present disclosure, similar expressions may be used for the trigger execution signal and the de-execution signal of other protection items. And when the execution signal X _ dly output by the delayed clock chain multiplexing module 120 is in the first level state (e.g., in the active high state), the target indication signal representing the target protection item has satisfied the delay requirement.
It should be noted that, in the present disclosure, the number of the D flip-flops included in the delay clock chain multiplexing module 120 is not specifically limited, and specifically, a delay time requirement corresponding to a plurality of protection items of an actual chip can be implemented as a basic requirement.
Optionally, a corresponding logic gate circuit may be further disposed in the delayed clock chain multiplexing module 120 at an input or an output of the corresponding D flip-flop to control and implement functions such as level flipping, multi-signal triggering, and the like.
The protection detection module 130 is connected to the clock selection and reset module 110 and the delayed clock chain multiplexing module 120, and receives the enable signal En, the protection trigger indication signal Prot, and the plurality of trigger signals, the plurality of release signals, the plurality of trigger execution signals, and the plurality of release execution signals corresponding to the plurality of protection items, so as to detect the level states of the plurality of trigger signals, the plurality of release signals, the plurality of trigger execution signals, and the plurality of release execution signals when the enable signal En and the protection trigger indication signal Prot are valid, and output the plurality of trigger indication signals, the plurality of release indication signals, and the plurality of protection signals according to the detection result.
Further, the protection detection module 130 includes a plurality of protection detection units (including, but not limited to, an OVP protection detection unit 131, a UVP protection detection unit 132, an OCC protection detection unit 133, an OCD protection detection unit 134, and an SCP protection detection unit 135). Each protection detection unit in the plurality of protection detection units receives a trigger signal, a release signal, a trigger execution signal and a release execution signal corresponding to a protection item, and when the enable signal En and the protection trigger indication signal Prot are effective, the level states of the trigger signal, the release signal, the trigger execution signal and the release execution signal are detected, and then the trigger indication signal, the release indication signal and the protection signal corresponding to the protection item are output according to the detection result.
Specifically, when the trigger signal corresponding to a certain protection item is in an effective state, an effective trigger indication signal corresponding to the protection item is correspondingly output; when the release signals corresponding to a certain protection item are all in an effective state, correspondingly outputting effective release indication signals corresponding to the protection item; when the trigger signal and the trigger execution signal corresponding to a certain protection item are both in an active state, the protection signal corresponding to the protection item with the first level state is correspondingly output, so as to control the corresponding switches in the discharge switch FET1 and the charge switch FET2 shown in fig. 1 to be turned off, and thus, the corresponding protection triggering is completed; when the release signal and the release execution signal corresponding to a protection item are both in an active state, the protection signal corresponding to the protection item with the second level state is correspondingly output, and then the corresponding switches of the discharge switch FET1 and the charge switch FET2 shown in fig. 1 are controlled to be turned on, so that the corresponding protection release is completed. If the trigger signal or the release signal corresponding to a protection item is detected to be in an effective level state, but the corresponding execution signal is in an ineffective level state, the protection item can be judged not to meet the delay requirement.
Therefore, in the protection detection module 130 of the present disclosure, a first logic gate circuit and a second logic gate circuit are disposed at the input end of each protection detection unit, and the first logic gate circuit is configured to trigger the output of the protection signal with the first level state only when the trigger signal corresponding to the protection item and the trigger execution signal are both valid; the second logic gate circuit is used for triggering and realizing the output of the protection signal with the second level state only when the cancellation signal and the cancellation execution signal corresponding to the protection item are both effective. Therefore, false triggering caused when the trigger execution signals or release execution signals of different protection items are output at the same output node (namely the output end of the same D trigger) in the delay clock chain can be avoided, and the detection accuracy is improved. The specific circuit structure of the first logic gate circuit and the second logic gate circuit should be set according to the actual active level state of each signal, which is not limited by the present invention.
In the present disclosure, the trigger signal and the release signal corresponding to the same protection item may be different level states of the same pulse signal; or the trigger signal and the release signal corresponding to the same protection item are respectively different pulse signals with the same or different effective level states. The present invention is not limited by this comparison.
Further, in the present disclosure, the trigger signal of the corresponding protection item in the plurality of protection items is represented by an X _ t signal, and the release signal of the corresponding protection item in the plurality of protection items is represented by an X _ r signal (both the X _ t signal and the X _ r signal are provided by an external detection circuit). For example, the trigger signal corresponding to the over-voltage protection item ovp is designated as ovp _ t, and the release signal corresponding to the over-voltage protection item ovp is designated as ovp _ r; marking the trigger signal corresponding to the under-voltage protection item uvp as uvp _ t, and marking the release signal corresponding to the under-voltage protection item uvp as uvp _ r; a trigger signal corresponding to the charging overcurrent protection item occ is recorded as occ _ t, and a release signal corresponding to the charging overcurrent protection item occ is recorded as occ _ r; recording a trigger signal corresponding to the discharging overcurrent protection item ocd as ocd _ t, and recording a release signal corresponding to the discharging overcurrent protection item ocd as ocd _ r; and recording a trigger signal corresponding to the short-circuit protection term scp as scp _ t, and recording a release signal corresponding to the short-circuit protection term scp as scp _ r. Similarly, in other embodiments of the present disclosure, similar expressions can be used for the trigger signal and the release signal of other protection items. In the present disclosure, for example, the protection signal corresponding to the overvoltage protection term OVP is referred to as OVP, the protection signal corresponding to the undervoltage protection term UVP is referred to as UVP, the protection signal corresponding to the charging overcurrent protection term OCC is referred to as OCC, the protection signal corresponding to the discharging overcurrent protection term OCD is referred to as OCD, and the protection signal corresponding to the short-circuit protection term SCP is referred to as SCP.
For example, it is assumed that the discharging over-current protection item ocd of a chip has a higher priority than the over-voltage protection item ovp, and the delay time required by the trigger indication signal ocd _ en corresponding to the discharging over-current protection item ocd is 256us, the delay time required by the trigger indication signal ovp _ en corresponding to the over-voltage protection item ovp is 128ms, and the clock cycle of the first base clock signal clk _ a among the plurality of base clock signals is 1s, the clock cycle of the second base clock signal clk _ B is 1ms, the clock cycle of the third base clock signal clk _ C is 1us, and each of the indication signal and the execution signal is in the first level state, such as the high level state, as the active state.
If the overvoltage protection of the chip is triggered at a certain moment, that is, both the signal ovp _ t and the signal Prot become high level at this moment, the clock selection and reset module 110 is triggered to output an effective reset signal rst at the previous rising edge when the signal Prot becomes high level, so as to reset the delay clock chain in the delay clock chain multiplexing module 120. Meanwhile, the protection detection module 130 outputs a high-level trigger indication signal ovp _ en based on the signal ovp _ t, and the clock selection and reset module 110 selects the second basic clock signal clk _ B as the target clock signal to be output to the delayed clock chain multiplexing module 120 based on the trigger indication signal ovp _ en, so as to control the delayed clock chain in the delayed clock chain multiplexing module 120 to perform timing based on the second basic clock signal clk _ B. If the OCD _ t is changed to high level at the timing of 100ms, the protection detection module 130 outputs a high-level trigger indication signal OCD _ en based on the OCD _ t, the clock selection and reset module 110 compares the priorities of the protection items corresponding to the OCD _ en and the signal ovp _ en, outputs an effective reset signal rst based on the OCD _ en, resets the delayed clock chain in the delayed clock chain multiplexing module 120, selects the third basic clock signal clk _ C as the target clock signal and outputs the target clock signal to the delayed clock chain multiplexing module 120, controls the delayed clock chain in the delayed clock chain multiplexing module 120 to count time based on the third basic clock signal clk _ C, and outputs a trigger execution signal C _ det _ dly to the protection detection module 130 when the timing value reaches 256us, the OCD protection detection unit 134 in the protection detection module 130 detects that both the signal C _ det _ dly and the OCD _ t are in an effective high-level state, and outputting a low-level protection signal OCD, and further controlling to turn off a discharge switch FET1 in the circuit diagram of FIG. 1, so as to complete the discharge overcurrent protection of the chip.
Based on the above description, the whole chip, on the basis of the original clock generated by the internal oscillator, adopts a simple clock frequency division chain, combines with the selection of the basic clock, the judgment of the priorities of a plurality of protection items and the reset of the delay clock chain, and completes the triggering and timing release of all protection items.
Fig. 5 is a flowchart illustrating a multi-delay clock chain multiplexing method for a battery protection chip according to an embodiment of the disclosure.
As shown in fig. 5, in the present embodiment, the method for multiplexing the multi-delay clock chain of the battery protection chip includes steps S1 to S4.
Specifically, in step S1, in the case of protection being triggered, the priority of the currently opened protection item is compared with the priority of the newly triggered protection item.
Under the condition that the chip triggers protection, if the chip triggers a plurality of protection items at the same time, the priority of the currently opened protection item is compared with the priority of the newly triggered protection item one by one according to the sequence of the triggered protection items and the preset priorities of the plurality of protection items. After the comparison, if the priority of the newly triggered protection item is lower than the priority of the currently opened protection item, executing step S2; if the priority of the newly triggered protection item is higher than that of the currently opened protection item, step S3 is executed. For example, priority comparison may be performed by using a software program according to the corresponding indicators of the different protection items, and priority comparison may be performed by using a software and hardware combination manner for amber, which is not limited in this disclosure.
Further, before triggering protection, the method further comprises: the delayed clock chain is reset. That is, the valid reset signal is triggered and output at the previous rising edge or falling edge of the protection trigger indication signal, and the delay clock chain is reset.
In step S2, when the priority of the newly triggered protection item is lower than the priority of the currently opened protection item, the currently opened protection item continues to be delayed and clocked based on the delayed clock chain.
Referring to fig. 2 and 3, when the priority of the newly triggered protection item is lower than the priority of the currently opened protection item, the clock selecting and resetting module 110 outputs an invalid reset signal rst while maintaining the output channel connected state of the current basic clock signal, so that the delayed clock chain multiplexing module 120 continues to perform delayed timing on the currently opened protection item until the timing is interrupted after the protection item with higher priority is triggered or the current timing value reaches the threshold value, and then step S4 is performed.
In step S3, when the priority of the newly triggered protection item is higher than the priority of the currently opened protection item, the delay clock chain is reset, and the basic clock signal corresponding to the newly triggered protection item is selected, and the reset delay clock chain is controlled to perform delay timing according to the selected basic clock signal.
Referring to fig. 2 and 3, when the priority of the newly triggered protection item is higher than the priority of the currently opened protection item, the clock selection and reset module 110 outputs an effective reset signal rst to reset the delay clock chain, simultaneously disconnects the output channel of the current basic clock signal, connects the output channel of the basic clock signal corresponding to the delay requirement of the newly triggered protection item, and controls the reset delay clock chain to perform delay timing according to the selected basic clock signal. Until the timing is interrupted after the protection item with higher priority is triggered, or the current timing value reaches the threshold value, step S4 is executed.
In step S4, after the timing value reaches the corresponding threshold, control implements triggering or releasing of the corresponding protection item.
After the timing value reaches the threshold corresponding to the protection item of the current time delay timing, an effective execution signal is output, and the discharging switch FET1 and/or the charging switch FET2 in fig. 1 are triggered to be turned on or off, so that the triggering or the releasing of the currently turned-on protection item is completed.
Based on the same inventive concept, the present disclosure also relates to a battery protection chip, which includes the multi-delay clock chain multiplexing circuit of the battery protection chip as described in fig. 2 to fig. 4, and the same delay clock chain is adopted to realize the timing of different delay times of the plurality of trigger indication signals and the plurality of release indication signals based on the current state of the circuit where the battery protection chip is located, the plurality of trigger indication signals and the plurality of release indication signals corresponding to the plurality of protection items, the priorities of the plurality of protection items, and the plurality of basic clock signals.
In summary, according to the present disclosure, the clock selection and reset module is adopted to reset the clock according to the priorities of the plurality of protection items before the release or trigger switching of different protection items, and select the corresponding basic clock as needed, so that the delay timing of the trigger and release of the plurality of protection items can be realized based on the same delay clock link. Because the same time delay clock chain is adopted for the time delay timing of triggering and releasing a plurality of protection items, and the time delay timing of triggering and releasing a plurality of protection items is not required to be respectively carried out through a plurality of time delay clock chains, the number of components required by the chip is effectively reduced, the power consumption and the cost are reduced, the occupation of the chip area is reduced, the miniaturization of the chip is favorably realized, and the requirements of low power consumption and area reduction of the lithium battery protection chip are met.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A multi-delay clock chain multiplexing circuit of a battery protection chip comprises:
the clock selection and reset module is used for receiving a protection trigger indication signal, a plurality of basic clock signals, a plurality of trigger indication signals corresponding to a plurality of protection items and a plurality of release indication signals, comparing the priority of the currently started protection item with the priority of the newly triggered protection item when the protection trigger indication signal is effective based on the priorities of the protection items, outputting a reset signal according to the comparison result, and selecting one of the basic clock signals meeting the delay requirement according to the detection result to output;
a delay clock chain multiplexing module, connected to the clock selecting and resetting module, for receiving the reset signal and one of the plurality of basic clock signals, resetting the delay clock chain when receiving the valid reset signal, controlling the delay clock chain to perform delay timing according to the one of the plurality of basic clock signals meeting the delay requirement, and outputting an execution signal with a first level state when a timing value reaches a corresponding threshold value;
a protection detection module, respectively connected to the clock selection and reset module and the delayed clock chain multiplexing module, for receiving an enable signal, the protection trigger indication signal, and a plurality of trigger signals, a plurality of release signals, a plurality of trigger execution signals, and a plurality of release execution signals corresponding to the plurality of protection items, for detecting level states of the plurality of trigger signals, the plurality of release signals, the plurality of trigger execution signals, and the plurality of release execution signals when the enable signal and the protection trigger indication signal are valid, and outputting the plurality of trigger indication signals, the plurality of release indication signals, and the plurality of protection signals according to a detection result,
the clock selection and reset module outputs an effective reset signal when the priority of the newly triggered protection item is higher than that of the currently started protection item.
2. The multi-delay clock chain multiplexing circuit of claim 1, wherein the clock select and reset module is further configured to trigger an output of the reset signal that is active on a previous rising or falling edge on which the protection trigger indication signal is active.
3. The multi-delay clock chain multiplexing circuit of any of claims 1 and 2, wherein the clock selection and reset module comprises:
the first priority judging subunit is used for comparing the priority of the currently opened protection item with the priority of the newly triggered protection item under the condition that the protection triggering indication signal is effective, and generating an interrupt signal when the priority of the newly triggered protection item is higher than the priority of the currently opened protection item;
a pulse generating subunit, connected to the first priority determining subunit, and configured to generate the valid reset signal when receiving the interrupt signal;
a second priority judging subunit, configured to, in a case that the protection trigger indication signal is valid, compare a priority of a currently-activated protection item with a priority of a newly-activated protection item, and generate a selection signal according to a delay requirement corresponding to the newly-activated protection item when the priority of the newly-activated protection item is higher than the priority of the currently-activated protection item;
and the one-out-of-multiple selector is connected with the second priority judging subunit and used for selecting the basic clock signal corresponding to the delay requirement of the newly triggered protection item to output when the selection signal is received.
4. The multi-delay clock chain multiplexing circuit of claim 1, wherein the delay clock chain multiplexing module comprises:
x D flip-flops connected in series, wherein a clock terminal of each D flip-flop in the x D flip-flops receives one of the plurality of basic clock signals meeting the delay requirement, a reset terminal of each D flip-flop receives the reset signal, and an output terminal of an ith D flip-flop in the x D flip-flops outputs the execution signal,
wherein x and i are both positive integers, and i is greater than or equal to 1 and less than or equal to x.
5. The multi-delay clock chain multiplexing circuit of claim 3, wherein each of the plurality of trigger execute signals and the plurality of de-execute signals corresponding to the plurality of protection entries is output at an output of a different one of the x D flip-flops.
6. The multi-delay clock chain multiplexing circuit according to claim 3, wherein at least some of the trigger execution signals and the de-execution signals corresponding to the protection entries are output from the output of the same D flip-flop among the x D flip-flops.
7. The multi-delay clock chain multiplexing circuit of claim 1, wherein the protection detection module comprises:
and each protection detection unit receives a trigger signal, a release signal, a trigger execution signal and a release execution signal corresponding to a protection item, detects the level states of the trigger signal, the release signal, the trigger execution signal and the release execution signal when the enable signal and the protection trigger indication signal are effective, and outputs the trigger indication signal, the release indication signal and the protection signal corresponding to the protection item according to the detection result.
8. A battery protection chip, comprising:
the multi-delay clock chain multiplexing circuit of the battery protection chip of any one of claims 1 to 7.
9. A multi-delay clock chain multiplexing method of a battery protection chip comprises the following steps:
under the condition of triggering protection, comparing the priority of the currently opened protection item with the priority of the newly triggered protection item;
when the priority of the newly triggered protection item is lower than that of the currently started protection item, continuing to perform delay timing on the currently started protection item based on the delay clock chain;
when the priority of the newly triggered protection item is higher than that of the currently started protection item, resetting the delay clock chain, selecting a basic clock signal corresponding to the newly triggered protection item, and controlling the reset delay clock chain to perform delay timing according to the selected basic clock signal;
and after the timing value reaches the corresponding threshold value, controlling to realize triggering or releasing of the corresponding protection item.
10. The method of claim 9, further comprising, before triggering protection:
resetting the delayed clock chain.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117272879A (en) * | 2023-09-19 | 2023-12-22 | 武汉泰朴半导体有限公司 | All-digital clock generation circuit and all-digital clock generation method |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538272A (en) * | 1983-12-22 | 1985-08-27 | Gte Automatic Electric Incorporated | Prioritized clock selection circuit |
| US5459419A (en) * | 1993-02-03 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Synchronizing pulse generating circuit |
| US6215837B1 (en) * | 1998-12-24 | 2001-04-10 | Hyundai Electronics Industries Co., Ltd. | Pipe counter signal generator processing double data in semiconductor device |
| US7071738B1 (en) * | 2004-06-24 | 2006-07-04 | Xilinx, Inc. | Glitchless clock selection circuit using phase detection switching |
| KR20080097546A (en) * | 2007-05-02 | 2008-11-06 | 충북대학교 산학협력단 | A signal collision prevention circuit |
| CN101860430A (en) * | 2010-06-24 | 2010-10-13 | 中兴通讯股份有限公司 | Device and method for implementing optical network unit switching clock source |
| US20110214003A1 (en) * | 2010-02-26 | 2011-09-01 | Renesas Electronics Corporation | Clock control signal generation circuit, clock selector, and data processing device |
| CN103532106A (en) * | 2013-11-04 | 2014-01-22 | 武汉大学 | Single lithium battery protection chip with accurate delay and dormancy functions |
| CN104380606A (en) * | 2012-06-14 | 2015-02-25 | 阿海珐有限公司 | Digital sensing circuit for a secondary clock signal to be monitored for clock failure with the aid of a primary clock signal |
| CN206894262U (en) * | 2017-03-14 | 2018-01-16 | 圣邦微电子（北京）股份有限公司 | Battery charging and discharging and protection control device for heated filament driving |
-
2020
- 2020-11-02 CN CN202011202360.1A patent/CN114448398A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4538272A (en) * | 1983-12-22 | 1985-08-27 | Gte Automatic Electric Incorporated | Prioritized clock selection circuit |
| US5459419A (en) * | 1993-02-03 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Synchronizing pulse generating circuit |
| US6215837B1 (en) * | 1998-12-24 | 2001-04-10 | Hyundai Electronics Industries Co., Ltd. | Pipe counter signal generator processing double data in semiconductor device |
| US7071738B1 (en) * | 2004-06-24 | 2006-07-04 | Xilinx, Inc. | Glitchless clock selection circuit using phase detection switching |
| KR20080097546A (en) * | 2007-05-02 | 2008-11-06 | 충북대학교 산학협력단 | A signal collision prevention circuit |
| US20110214003A1 (en) * | 2010-02-26 | 2011-09-01 | Renesas Electronics Corporation | Clock control signal generation circuit, clock selector, and data processing device |
| CN101860430A (en) * | 2010-06-24 | 2010-10-13 | 中兴通讯股份有限公司 | Device and method for implementing optical network unit switching clock source |
| CN104380606A (en) * | 2012-06-14 | 2015-02-25 | 阿海珐有限公司 | Digital sensing circuit for a secondary clock signal to be monitored for clock failure with the aid of a primary clock signal |
| CN103532106A (en) * | 2013-11-04 | 2014-01-22 | 武汉大学 | Single lithium battery protection chip with accurate delay and dormancy functions |
| CN206894262U (en) * | 2017-03-14 | 2018-01-16 | 圣邦微电子（北京）股份有限公司 | Battery charging and discharging and protection control device for heated filament driving |
Non-Patent Citations (2)
| Title |
|---|
| 任先文等: "基于ARM的嵌入式系统在直流系统接地故障定位中的研究", 继电器, vol. 36, no. 02, 16 January 2008 (2008-01-16), pages 10 - 13 * |
| 顾春明: "基于FPGA的高压变频器脉冲信号编码技术的算法实现", 变频器世界, no. 11, 15 November 2009 (2009-11-15), pages 95 - 98 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117272879A (en) * | 2023-09-19 | 2023-12-22 | 武汉泰朴半导体有限公司 | All-digital clock generation circuit and all-digital clock generation method |
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