CN102833026B - A kind of clock tracing method, system and network element - Google Patents
A kind of clock tracing method, system and network element Download PDFInfo
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- CN102833026B CN102833026B CN201210319108.8A CN201210319108A CN102833026B CN 102833026 B CN102833026 B CN 102833026B CN 201210319108 A CN201210319108 A CN 201210319108A CN 102833026 B CN102833026 B CN 102833026B
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Abstract
The present invention relates to network communication field, specifically disclose a kind of clock tracing method, comprising: according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection; If the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is added one; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If selected outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.The embodiment of the invention also discloses a kind of clock tracing system and network element.
Description
Technical field
The present invention relates to the network communications technology, particularly relate to a kind of clock tracing method, system and network element.
Background technology
SDH (Synchronous Digital Hierarchy, SDH (Synchronous Digital Hierarchy)) in network, usually require that SDH network element is operated in synchronous or quasi synchronous network environment, to avoid the loss of data between pointer regulation, inferior equipment function or network element.But timing reference input is in network transfer process, may due to transfer equipment failure and other reasons, cause the excessive or performance degradation of the frequency departure of timing reference input.If network element continues to follow the tracks of this timing reference input, a large amount of pointer regulation may be caused, even occur the major accident such as error code and service disconnection.
In prior art, by carrying out frequency deviation monitoring to present clock tracing source, switching or the switching of master/backup clock veneer with shot clock tracing source, making network element follow the tracks of clock source working properly, ensure the normal transmission of business between network element.
But, once present clock tracing source produces frequency deviation fault, then direct clock tracing source is switched to the system clock source that priority is the highest, clock tracing source after switching may also have frequency deviation fault, detection speed is slow, cause the long period clock tracing source could be switched to available system clock source, affect quality of service.
In prior art, only carry out frequency deviation detection for present clock tracing source, once present clock tracing source produces frequency deviation fault, then direct clock tracing source is switched to the system clock source that priority is the highest, but the clock tracing source after switching may also have frequency deviation fault, then clock tracing source could be switched to available system clock source by the long period, and detection speed is slow, affects quality of service.
The clock tracing method that the embodiment of the present invention provides, by carrying out frequency deviation detection to outside input clock source poll in advance, assess all outside input clock sources in advance and whether have frequency deviation fault, therefore, when clock tracing source needs can select available system clock source timely and effectively when switching, reduce the impact on quality of service.
Further, based on above-mentioned steps S201 to step S202, can also comprise:
Step S203, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
In different transmission networks, the clock quality grade that can be exported by network element by different modes is set to unavailable.Such as, SDH (Synchronous Digital Hierarchy, SDH (Synchronous Digital Hierarchy)) in, S 1 byte can be set to QL DNU (Quality Level_Do Not Use), the clock quality grade exported in order to indicate network element is unavailable; In OTN (Optical Transport Network, optical transfer network), the clock quality grade that can be exported by the reserved field instruction network element in SSM is unavailable; In PTN (Packet Transport Network, Packet Transport Network), the clock quality grade that can be exported by synchronous Ethernet message instruction network element is unavailable.
All outside input clock sources are frequency deviation fault and may cause due to underlying cause: all clock sources that upstream network element exports all have frequency deviation fault, or this network element internal clock source has frequency deviation fault.Network element cannot judge specifically cause all outside input clock sources to be frequency deviation fault by which kind of reason above-mentioned.
In real network, some network element is supported or enable frequency deviation measuring ability, and some network element is not supported or not enable frequency deviation measuring ability.For not supporting or the network element of not enable frequency deviation measuring ability, himself cannot carry out the judgement of offset frequency situation to external clock reference.
In the present embodiment, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, the clock quality grade then exported by this network element is set to unavailable, downstream do not support or the network element of not enable frequency deviation measuring ability unavailable according to clock quality grade, then can not follow the tracks of the clock of this network element, then isolate frequency deviation fault.
Do not isolate frequency deviation fault in prior art, then the frequency deviation fault of single network element may diffuse to the whole network, causes the clock deterioration of other network element.
The clock tracing method that the embodiment of the present invention provides, by carrying out frequency deviation detection to outside input clock source poll in advance, assess all outside input clock sources in advance and whether have frequency deviation fault, therefore, when clock tracing source needs can select available system clock source timely and effectively when switching, reduce the impact on quality of service.
In addition, adopt the technical scheme of the embodiment of the present invention, without available Foreign input clock source on network element, and all outside input clock sources are when being frequency deviation fault, downstream network element sends the disabled instruction of clock quality grade that this network element exports, frequency deviation fault pervasion can also be prevented, avoid the clock deterioration causing network others network element.
Further, the master clock veneer of network element performs the step S201 of above-described embodiment to step S202, or the master clock veneer of network element performs the step S201 of above-described embodiment to step S203, and the standby clock veneer of network element does not carry out frequency deviation detection, can also comprise:
Step S204, all for epicycle outside input clock sources testing result is sent to standby clock veneer by master clock veneer.
In prior art, the frequency deviation that active and standby clock veneer carries out clock tracing source separately detects, and then testing result is informed to the other side, then adjudicates separately, and using the trigger condition one of of frequency deviation testing result as masterslave switchover.Therefore, when internal clock source fault, the frequency deviation of active and standby clock veneer detects judges different results, causes master/backup clock veneer frequently to switch, and causes network clocking unstable.
The clock tracing method that the embodiment of the present invention provides, the frequency deviation only having master clock veneer to carry out outside input clock source detects, then frequency deviation testing result is sent to standby clock veneer, synchronous master/backup clock veneer, frequency deviation fault is not as the condition of clock single-board host-slave switching, simplify handling process, ensure the stability of network clocking.
Summary of the invention
The embodiment provides a kind of clock tracing method, system and network element, solve prior art frequency deviation detection speed slow, cause the long period clock tracing source could be switched to available system clock source, affect the problem of quality of service.
Embodiments of the invention adopt following technical scheme:
First aspect present invention provides a kind of clock tracing method, comprising:
According to priority choose outside input clock source from high to low successively and carry out frequency deviation detection;
If the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is added one; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If selected outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element;
If the frequency deviation in selected outside input clock source does not exceed described a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available.
In the implementation that the first is possible, described method also comprises:
If without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
In conjunction with the first possible implementation of first aspect, in the implementation that the second is possible, described downstream network element sends the disabled indication information of clock quality grade that this network element exports, and specifically comprises:
In SDH (Synchronous Digital Hierarchy), sent the disabled indication information of clock quality grade of this network element output by S1 byte downstream network element; In optical transfer network, sent the disabled indication information of clock quality grade of this network element output by Synchronization Status Message downstream network element; In Packet Transport Network, sent the disabled indication information of clock quality grade of book network element output by synchronous Ethernet message downstream network element.
In conjunction with the first possible implementation of first aspect, first aspect or the possible implementation of the second of first aspect, in the implementation that the third is possible, describedly according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection, specifically comprise:
For the disabled outside input clock source that non-frequency deviation fault causes, do not carry out frequency deviation detection.
In conjunction with the first possible implementation of first aspect, first aspect or the possible implementation of the second of first aspect, in the 4th kind of possible implementation, describedly according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection, specifically comprise:
The master clock veneer of this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
Second aspect present invention provides a kind of network element, comprises the first detecting unit, the first determining unit and the first switch unit:
First detecting unit, carries out frequency deviation detection for according to priority choosing outside input clock source from high to low successively;
First determining unit, if exceed a reference source frequency deviation detection range for the frequency deviation in selected outside input clock source, adds one by the frequency deviation error count in selected outside input clock source; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If the frequency deviation in selected outside input clock source does not exceed described a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available;
First switch unit, if unavailable and be the current clock tracing source of this network element for selected outside input clock source, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
In the implementation that the first is possible, described network element also comprises:
First setting unit, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the second is possible, described first detecting unit specifically comprises:
First detection sub-unit, carrying out frequency deviation detection for according to priority choosing outside input clock source from high to low successively, for the disabled outside input clock source that non-frequency deviation fault causes, not carrying out frequency deviation detection.
In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the third is possible, described first detecting unit specifically comprises:
Second detection sub-unit, master clock veneer for this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
Third aspect present invention provides a kind of network element, comprises the second determining unit and the second switch unit:
Second determining unit, the indication information for sending according to upstream network element determines that the clock quality grade in the outside input clock source that described upstream network element is corresponding is unavailable;
Second switch unit, if be the current clock tracing source of this network element for the outside input clock source that described upstream network element is corresponding, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
Fourth aspect present invention provides a kind of clock tracing system, the first network element that the first possible implementation that described system at least comprises first aspect provides and the second network element that the third aspect provides, described second network element is the downstream network element of described first network element.
A kind of clock tracing method, system and network element that the embodiment of the present invention provides, by carrying out frequency deviation detection to outside input clock source poll in advance, assess all outside input clock sources in advance and whether have frequency deviation fault, therefore, when clock tracing source needs can select available system clock source timely and effectively when switching, reduce the impact on quality of service.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The flow chart of a kind of clock tracing method that Fig. 1 provides for one embodiment of the invention;
The network topology schematic diagram that Fig. 2 provides for embodiments of the invention;
Another network topology schematic diagram that Fig. 3 provides for embodiments of the invention;
The structured flowchart of a kind of network element that Fig. 4 provides for embodiments of the invention;
The structured flowchart of the another kind of network element that Fig. 5 provides for embodiments of the invention;
The structured flowchart of another node device that Fig. 6 provides for embodiments of the invention;
A kind of clock tracing system schematic that Fig. 7 provides for embodiments of the invention.
Embodiment
Embodiments provide a kind of method of clock tracing, system and node device.Technical scheme for a better understanding of the present invention, is described in detail the embodiment of the present invention below in conjunction with accompanying drawing.
Should be clear and definite, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention, as shown in Figure 1, the method comprises the following steps a kind of flow process of clock tracing method:
Step S101, according to priority chooses outside input clock source from high to low successively and carries out frequency deviation detection;
Step S102, if the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, adds one by the frequency deviation error count in selected outside input clock source; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If selected outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element;
If the frequency deviation in selected outside input clock source does not exceed a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available.
Further, the method can also comprise:
Step S103, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
Further, downstream network element sends the disabled indication information of clock quality grade that this network element exports, and specifically comprises:
In SDH (Synchronous Digital Hierarchy), sent the disabled indication information of clock quality grade of this network element output by S1 byte downstream network element; In optical transfer network, sent the disabled indication information of clock quality grade of this network element output by SSM (Synchronization Status Message, Synchronization Status Message) downstream network element; In Packet Transport Network, sent the disabled indication information of clock quality grade of this network element output by synchronous Ethernet message downstream network element.
Further, according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection, specifically comprise: the disabled outside input clock source that non-frequency deviation fault is caused, can not frequency deviation detection be carried out.
Further, according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection, specifically comprise:
The master clock veneer of this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
Below in conjunction with accompanying drawing, a kind of clock tracing method, system and the network element that the embodiment of the present invention provides is described in detail.
Should be clear and definite, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one, the embodiment of the present invention provides a kind of clock tracing method, and the method comprises the following steps:
Step S201, according to priority chooses outside input clock source from high to low successively and carries out frequency deviation detection.
In the present embodiment, frequency deviation, the frequency-splitting between namely selected external input sources and internal clock source.Internal clock source can be the clock source that the crystal oscillator of network element internal, chip or VCO (Voltage-ontrolled Oscillator, voltage controlled oscillator) etc. produce.The detection mode of frequency deviation is unrestricted, can be detected by hardware or software.System clock source comprises outside input clock source and network element internal clock source.
Network element according to priority can be chosen outside input clock source from high to low successively and carry out frequency deviation detection.Because clock tracing source is according to priority selected, the problem in the outside input clock source that priority is high therefore can be detected in advance, carry out the switching in clock tracing source in time.
Further, in step s 201, to outside input clock source poll, frequency deviation periodically in real time can be carried out and detects.
Further, in step s 201, for the disabled outside input clock source that non-frequency deviation fault causes, frequency deviation detection can not be carried out.Various faults can cause outside input clock source unavailable, comprises frequency deviation fault, clock quality grade declines, the unavailable or physical detection fault of clock source veneer uploaded state etc.Wherein, physical detection fault can comprise the fault such as phase-locked loop losing lock, light mouth LOS (Loss Of Signal, dropout).
Step S202, if the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, adds one by the frequency deviation error count in this outside input clock source; If be greater than frequency deviation threshold value after the frequency deviation error count in this outside input clock source adds one, determine that this outside input clock source produces frequency deviation fault, this outside input clock source is set to unavailable; If this outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, then the clock tracing source of this network element is switched to the internal clock source of this network element;
If the frequency deviation in selected outside input clock source does not exceed a reference source frequency deviation detection range, the frequency deviation error count in this outside input clock source is reset, this outside input clock source is set to available.
In the present embodiment, a reference source frequency deviation detection range can pre-set, and such as, this scope can be set to +/-4.6PPM, exceeds this scope and then thinks that frequency deviation is excessive, the frequency deviation error count in this outside input clock source is added one.
Frequency deviation threshold value can pre-set.If be greater than frequency deviation threshold value after the frequency deviation counting in this outside input clock source adds one, determine that this outside input clock source produces frequency deviation fault, this outside input clock source is set to unavailable, prevents this network element using this outside input clock source as clock tracing source.
If this outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest.Can also report and alarm to webmaster, for further handling failure.
If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
If the frequency deviation in selected outside input clock source does not exceed a reference source frequency deviation detection range, the frequency deviation error count in this outside input clock source is reset, this outside input clock source is set to available.
Embodiment two, the embodiment of the present invention provides a kind of clock tracing method, and as shown in Figure 2, NE1, NE2, NE3, NE4 and NE5 are the network element in network, and NE1, NE2, NE3 are the outside input clock source of NE4, and NE4 is the outside input clock source of NE5.The priority orders in the upper outside input clock source of NE4 is followed successively by NE1, NE2, NE3 from high to low, and the internal clock source 38M crystal oscillator of to be a reference source frequency deviation detection range of NE1, NE4 be the clock tracing source of NE4 +/-4.6PPM, NE1 breaks down.The method specifically comprises the steps:
Step S301, NE4 first choose the highest outside input clock source of priority, and the outside input clock source that namely NE1 is corresponding, carries out frequency deviation detection.
Step S302, supposes that frequency deviation threshold value be the frequency deviation error count in the outside input clock source that 4, NE1 is corresponding is 4, has detected that outside input clock source that NE1 is corresponding is continuous and exceeded a reference source frequency deviation detection range for 4 times namely.
NE4 detects that the outside input clock source that NE1 is corresponding exceeds a reference source frequency deviation detection range, and the frequency deviation error count frequency deviation error count in outside input clock source corresponding for NE1 being added outside input clock source corresponding to one, NE1 is 5, is greater than frequency deviation threshold value 4.NE4 determines that the outside input clock source that NE1 is corresponding produces frequency deviation fault, is set to unavailable by this outside input clock source.
The outside input clock source corresponding due to NE1 is unavailable, and is the current clock tracing source of NE4, by the available Foreign input clock source that the clock tracing source of NE4 switches to priority the highest, and the outside input clock source that namely NE2 is corresponding.
Step S303, NE4 according to priority choose next outside input clock source from high to low, and the outside input clock source that namely NE2 is corresponding, carries out frequency deviation detection.
Step S304, NE4 detect that the outside input clock source that NE2 is corresponding does not exceed a reference source frequency deviation detection range, the frequency deviation error count in outside input clock source corresponding for NE2 are reset, are set to available by outside input clock source corresponding for NE2.
Step S305, NE4 according to priority choose next outside input clock source from high to low, and the outside input clock source that namely NE3 is corresponding, carries out frequency deviation detection.
Step S306, NE4 detect that the outside input clock source that NE3 is corresponding does not exceed a reference source frequency deviation detection range, the frequency deviation error count in outside input clock source corresponding for NE3 are reset, are set to available by outside input clock source corresponding for NE3.
Step S307, if the internal clock source of NE2 and NE3 also breaks down, then NE4 detects that the outside input clock source that NE2 and NE3 is corresponding all produces frequency deviation fault, is all set to unavailable by outside input clock source corresponding for NE2 and NE3.
Due on NE4 without available Foreign input clock source, the clock tracing source of NE4 is switched to the internal clock source 38M crystal oscillator of NE4.
Step S308, due on NE4 without available Foreign input clock source, and all outside input clock sources are frequency deviation fault, are set to unavailable by the clock quality grade that NE4 exports.
Embodiment three, the embodiment of the present invention provides a kind of clock tracing method, and as shown in Figure 3, NE1, NE2, NE3, NE4 and NE5 are the network element in network, NE1 and NE2 supports or enable frequency deviation measuring ability, and NE3, NE4 and NE5 do not support or not enable frequency deviation measuring ability.NE1 is the outside input clock source of NE2, and NE2 is the outside input clock source of NE3, and NE3 is the outside input clock source of NE4 and NE5.The a reference source frequency deviation detection range of to be the clock tracing source of NE1, NE3 be the clock tracing source of NE2 NE2, NE2 and NE3 is that the internal clock source 38M crystal oscillator of +/-4.6PPM, NE2 breaks down.The method specifically comprises the steps:
Step S401, NE2 according to priority choose outside input clock source from high to low successively and carry out frequency deviation detection, NE2 only have an outside input clock source, the outside input clock source that namely NE1 is corresponding.
Step S402, because the internal clock source 38M crystal oscillator of NE2 breaks down, testing result is that the outside input clock source that NE1 is corresponding produces frequency deviation fault, is set to unavailable by outside input clock source corresponding for NE1
The outside input clock source corresponding due to NE1 is unavailable, and is the current clock tracing source of NE2, without available Foreign input clock source on NE2, the clock tracing source of NE2 is switched to the internal clock source 38M crystal oscillator of NE2.
Due on NE2 without available Foreign input clock source, and all outside input clock sources are frequency deviation fault, are set to unavailable by the clock quality grade that NE2 exports.
The clock tracing source of step S403, NE3 is NE2, but the clock quality grade that NE2 exports is unavailable, and its clock tracing source is switched to internal clock source by NE3.Although NE3 does not support or not enable frequency deviation measuring ability, do not carry out frequency deviation detection, NE3 does not continue to follow the tracks of failing clock source, NE4 and NE5 is also uninfluenced simultaneously, and the internal clock source fault of NE2, not to downstream diffusion, has effectively isolated fault.
Embodiment four, embodiments provides a kind of network element, and as shown in Figure 4, this network element comprises:
First detecting unit 410, carries out frequency deviation detection for according to priority choosing outside input clock source from high to low successively;
First determining unit 420, if exceed a reference source frequency deviation detection range for the frequency deviation in selected outside input clock source, adds one by the frequency deviation error count in selected outside input clock source; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If the frequency deviation in selected outside input clock source does not exceed a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available;
First switch unit 430, if unavailable and be the current clock tracing source of this network element for selected outside input clock source, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
Further, this network element can also comprise:
First setting unit 440, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
Further, the first detecting unit 410 can specifically comprise:
First detection sub-unit 411, carrying out frequency deviation detection for according to priority choosing outside input clock source from high to low successively, for the disabled outside input clock source that non-frequency deviation fault causes, not carrying out frequency deviation detection.
Further, the first detecting unit 410 can specifically comprise:
Second detection sub-unit 412, master clock veneer for this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
Embodiment five, embodiments provides a kind of network element, and as shown in Figure 5, this network element comprises:
Receiver 510, for receiving internal clock source and outside input clock source.
Processor 520, carries out frequency deviation detection for according to priority choosing outside input clock source from high to low successively; If the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is added one; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If the frequency deviation in selected outside input clock source does not exceed a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available; If selected outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
Transmitter 530, for sending the clock tracing source of this network element.
Further, this network element can also comprise:
Processor 520, if also on this network element without available Foreign input clock source, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
Transmitter 530, also for exporting the disabled indication information of clock quality grade that this network element exports.
Embodiment six, embodiments provides a kind of network element, and as shown in Figure 6, this network element comprises:
Second determining unit 610, the clock quality grade in the outside input clock source that the indication information determination upstream network element for sending according to upstream network element is corresponding is unavailable;
Second switch unit 620, if be the current clock tracing source of this network element for the outside input clock source that upstream network element is corresponding, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
Embodiment seven, embodiments provides a kind of network element, and as shown in Figure 5, this network element comprises:
Receiver 510, for receiving indication information that upstream network element sends, internal clock source and outside input clock source.
Processor 520, the clock quality grade in the outside input clock source that the indication information determination upstream network element for sending according to upstream network element is corresponding is unavailable; If the clock tracing source that to be this network element current, outside input clock source corresponding to upstream network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
Transmitter 530, for sending the clock tracing source of this network element.
The content such as information interaction, implementation between each unit in above-described embodiment four to seven network element, due to the inventive method embodiment based on same design, particular content can see in the inventive method embodiment describe, repeat no more herein.
A kind of network element that the embodiment of the present invention provides, by carrying out frequency deviation detection to outside input clock source poll in advance, assess all outside input clock sources in advance and whether have frequency deviation fault, therefore, when clock tracing source needs can select available system clock source timely and effectively when switching, reduce the impact on quality of service.
In addition, adopt the network element of the embodiment of the present invention, without available Foreign input clock source on network element, and all outside input clock sources are when being frequency deviation fault, can also downstream network element send this network element export the disabled instruction of clock quality grade, frequency deviation fault pervasion can also be prevented, avoid the clock deterioration causing network others network element.
Embodiment eight, embodiments provides a kind of clock tracing system, and as shown in Figure 7, comprise the first network element and the second network element, the second network element is the downstream network element of the first network element:
First network element 710, comprising: the first detecting unit, the first determining unit and the first switch unit, and particular content, see the first detecting unit 410, first determining unit 420 and the first switch unit 430 of embodiment four, repeats no more herein.
Second network element 720, comprising: the second determining unit and the second switch unit, and particular content, see the second determining unit 610 and the second switch unit 620 of embodiment six, repeats no more herein.
A kind of clock tracing system of above-described embodiment eight, the content such as information interaction between the specific implementation process of its each unit and each unit, due to the inventive method embodiment based on same inventive concept, see embodiment of the method, can be not described in detail here.
The technical scheme that the embodiment of the present invention provides, by carrying out frequency deviation detection to outside input clock source poll in advance, assess all outside input clock sources in advance and whether have frequency deviation fault, therefore, when clock tracing source needs can select available system clock source timely and effectively when switching, reduce the impact on quality of service.
In addition, adopt the network element of the embodiment of the present invention, without available Foreign input clock source on network element, and all outside input clock sources are when being frequency deviation fault, can also downstream network element send this network element export the disabled instruction of clock quality grade, frequency deviation fault pervasion can also be prevented, avoid the clock deterioration causing network others network element.
One of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method, that the hardware that can carry out instruction relevant by computer program has come, described program can be stored in a computer read/write memory medium, this program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (10)
1. a clock tracing method, is characterized in that, comprising:
According to priority choose outside input clock source from high to low successively and carry out frequency deviation detection;
If the frequency deviation in selected outside input clock source exceeds a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is added one; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If selected outside input clock source is unavailable and be the current clock tracing source of this network element, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element;
If the frequency deviation in selected outside input clock source does not exceed described a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available.
2. method according to claim 1, is characterized in that, described method also comprises:
If without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
3. method according to claim 2, is characterized in that, described downstream network element sends the disabled indication information of clock quality grade that this network element exports, and specifically comprises:
In SDH (Synchronous Digital Hierarchy), sent the disabled indication information of clock quality grade of this network element output by S1 byte downstream network element; In optical transfer network, sent the disabled indication information of clock quality grade of this network element output by Synchronization Status Message downstream network element; In Packet Transport Network, sent the disabled indication information of clock quality grade of book network element output by synchronous Ethernet message downstream network element.
4. the method according to claim 1,2 or 3, is characterized in that, describedly according to priority chooses outside input clock source from high to low successively and carries out frequency deviation detection, specifically comprises:
For the disabled outside input clock source that non-frequency deviation fault causes, do not carry out frequency deviation detection.
5. the method according to claim 1,2 or 3, is characterized in that, describedly according to priority chooses outside input clock source from high to low successively and carries out frequency deviation detection, specifically comprises:
The master clock veneer of this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
6. a network element, is characterized in that, comprises the first detecting unit, the first determining unit and the first switch unit:
First detecting unit, carries out frequency deviation detection for according to priority choosing outside input clock source from high to low successively;
First determining unit, if exceed a reference source frequency deviation detection range for the frequency deviation in selected outside input clock source, adds one by the frequency deviation error count in selected outside input clock source; If be greater than frequency deviation threshold value after the frequency deviation error count in selected outside input clock source adds one, determine that selected outside input clock source produces frequency deviation fault, selected outside input clock source is set to unavailable; If the frequency deviation in selected outside input clock source does not exceed described a reference source frequency deviation detection range, the frequency deviation error count in selected outside input clock source is reset, selected outside input clock source is set to available;
First switch unit, if unavailable and be the current clock tracing source of this network element for selected outside input clock source, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
7. network element according to claim 6, is characterized in that, described network element also comprises:
First setting unit, if without available Foreign input clock source on this network element, and all outside input clock sources are frequency deviation fault, and downstream network element sends the disabled indication information of clock quality grade that this network element exports.
8. the network element according to claim 6 or 7, is characterized in that, described first detecting unit specifically comprises:
First detection sub-unit, carrying out frequency deviation detection for according to priority choosing outside input clock source from high to low successively, for the disabled outside input clock source that non-frequency deviation fault causes, not carrying out frequency deviation detection.
9. the network element according to claim 6 or 7, is characterized in that, described first detecting unit specifically comprises:
Second detection sub-unit, master clock veneer for this network element is according to priority chosen outside input clock source from high to low successively and is carried out frequency deviation detection, and the frequency deviation testing result in all outside input clock sources is sent to the standby clock veneer of this network element by the master clock veneer of this network element.
10. a clock tracing system, it is characterized in that, described system at least comprises the first network element according to claim 6, and the second network element, described second network element is the downstream network element of described first network element, and described second network element comprises the second determining unit and the second switch unit:
Second determining unit, the indication information for sending according to upstream network element determines that the clock quality grade in the outside input clock source that described upstream network element is corresponding is unavailable;
Second switch unit, if be the current clock tracing source of this network element for the outside input clock source that described upstream network element is corresponding, by the available Foreign input clock source that the clock tracing source of this network element switches to priority the highest; If without available Foreign input clock source on this network element, the clock tracing source of this network element is switched to the internal clock source of this network element.
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| CN104518839B (en) | 2013-09-30 | 2017-06-27 | 华为技术有限公司 | frequency deviation detection method and device |
| CN104954156A (en) * | 2014-03-26 | 2015-09-30 | 中兴通讯股份有限公司 | Clock synchronous network element abnormity processing method, apparatus and system thereof |
| CN106301744B (en) * | 2015-05-14 | 2020-04-28 | 中兴通讯股份有限公司 | Clock protection switching method and device for clock board |
| CN106301643B (en) * | 2015-05-15 | 2018-10-30 | 华为技术有限公司 | A kind of method and control device for configurable clock generator tracking |
| CN107547232B (en) * | 2016-06-28 | 2021-08-31 | 中兴通讯股份有限公司 | Network element equipment and transmission mode configuration device and method thereof |
| CN106209291B (en) * | 2016-08-30 | 2018-09-14 | 京信通信系统（中国）有限公司 | Clock source list update, clock synchronizing method and the system that base station clock synchronizes |
| CN107579796B (en) * | 2017-09-21 | 2019-04-26 | 烽火通信科技股份有限公司 | A kind of the clock processing unit and method of OTN branch board |
| CN110830137B (en) * | 2019-10-24 | 2021-06-01 | 广东安朴电力技术有限公司 | Multi-node time synchronization control system based on SRIO and synchronization control method thereof |
| CN116074871A (en) * | 2019-11-29 | 2023-05-05 | 华为技术有限公司 | Clock fault positioning method and network equipment |
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