CN101840906B - 高q值芯片集成电感 - Google Patents

高q值芯片集成电感 Download PDF

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CN101840906B
CN101840906B CN2010101461990A CN201010146199A CN101840906B CN 101840906 B CN101840906 B CN 101840906B CN 2010101461990 A CN2010101461990 A CN 2010101461990A CN 201010146199 A CN201010146199 A CN 201010146199A CN 101840906 B CN101840906 B CN 101840906B
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bonding
inductance
chip integrated
integrated inductor
metal routing
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CN101840906A (zh
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陈俊
谢利刚
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RDA MICROELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

本发明公开了一种高Q值芯片集成电感，所述芯片中包括至少两个管芯，所述两个管芯上均设置有一条或多条金属走线，所述金属走线都相互平行，每条金属走线的末端均设置有键合区，多条键合线将两个管芯上的键合区相连接，使得键合线和金属走线组成一条螺旋状的通路。本发明通过上述结构，明显提高了电感的Q值，并克服了传统集成电路中电感的缺点，从而提高产品集成度，优化产品性能，降低产品成本。

Description

高Q值芯片集成电感
技术领域
本发明涉及一种电感，尤其是一种高Q值芯片集成电感。
背景技术
目前，许多射频电路中的匹配网络，滤波网络以及偏置网络都要求其中的电感具有高电感值，低损耗值，即电感要具有高Q的特性。通常情况下，电感值越高，电感尺寸越大，成本越高，同时，电感的精度也与电感的价格成正比，在很多电路设计应用中，电感都扮演着重要的角色。
传统的集成电路中，电感的实现方法一般可以分为以下三种情况：第一种实现方法是在芯片外部加分立电感。这种应用方法并不具有吸引力，因为制造厂要为片外分立电感制作基板，留下装配空间进行贴装，这样会增加装配的成本，同时要用一定长度的片外走线将电路管芯与片外电感进行连接，这样会产生额外的寄生。第二种方法是用键合线来形成键合电感。键合线是一条很细的金属线，一般是用来连接电路管芯键合区和封装管脚的或者进行键合区之间的连接。这种方法的缺点是键合线能实现的电感值受很多因素的影响，只能提供有限的电感值。第三种方法是在电路管芯上制作平面螺旋电感，这种方法会加大电路管芯的面积，从而增加产品的成本，并且这种平面螺旋电感的Q值较低。
因此，我们需要小尺寸，高Q值，易于集成，电感值可以灵活调整的电感去满足无线通信领域中匹配网络，滤波网络以及偏置网络应用的需要。
发明内容
本发明所要解决的技术问题是提供一种高Q值芯片集成电感，能够明显提高电感的Q值，并且提高产品集成度，优化产品性能，降低产品成本。
为解决上述技术问题，本发明高Q值芯片集成电感的技术方案是，所述芯片中包括至少两个管芯，所述两个管芯上均设置有一条或多条金属走线，所述金属走线都相互平行，每条金属走线的末端均设置有键合区，多条键合线将两个管芯上的键合区相连接，使得键合线和金属走线组成一条螺旋状的通路。
本发明通过上述结构，明显提高了电感的Q值，并克服了传统集成电路中电感的缺点，从而提高产品集成度，优化产品性能，降低产品成本。
附图说明
下面结合附图和实施例对本发明作进一步详细的说明：
图1为本发明高Q值芯片集成电感一个实施例的俯视图；
图2为图1所示的实施例的立体图；
图3为本发明高Q值芯片集成电感另一个实施例的示意图。
图中附图标记为，100.管芯；101、102、103.键合区；200.管芯；201、202、203、204.键合区；301、302、303.键合线；401、402、403.金属走线。
具体实施方式
本发明公开了一种高Q值芯片集成电感，所述芯片中包括至少两个管芯，所述两个管芯上均设置有一条或多条金属走线，所述金属走线都相互平行，每条金属走线的末端均设置有键合区，多条键合线将两个管芯上的键合区相连接，使得键合线和金属走线组成一条螺旋状的通路。
所述两个管芯中一个管芯叠放在另一个管芯的上面，并且上面的管芯面积小于下面的管芯，下面的管芯的金属走线和键合区设置在两个管芯非重叠的区域。
所述两个管芯并排设置。
所述金属走线的材料为金、铜或者铝等金属。
所述键合线的材料为金、铜或者铝等金属。
图1为本发明一个实施例的俯视图，图2为该实施例的立体图。100和200分别是两个电路管芯，管芯200通过粘合剂粘贴于管芯100的表面。图3所示的实施例中，管芯100和管芯200分别粘贴于同一表面。上述两个实施例中，管芯100上设计有3个键合区101、102和103，管芯200上设计有3个键合区201、202和203，键合区的数目可根据实际需求进行调整。键合区101与键合区201通过键合线301连接，同理，键合区102与键合区202通过键合线302连接，键合区103与键合区203通过键合线303连接。键合区102和键合区103通过管芯100上的金属走线401连接，键合区201和键合区203通过管芯200上的金属走线403连接。金属走线可以是金、铜或其他金属，键合线可以是金、铜或其他金属，这样便形成了一种三维的空间螺旋电感，其中键合区101为电感的一个端口，电感的另一个端口204通过管芯200上的金属走线402与键合区202连接。这种三维空间螺旋电感中，键合线301与键合线302的电流方向相同，金属走线402与金属走线403的电流方向也相同，从而增强耦合电感，提高电感的Q值。由于键合区的数量和距离以及键合线的高度都可以根据实际电感的大小进行设计调整，使得这种新型高Q电感的应用更加易于集成。
综上所述，本发明通过对封装内电感的结构进行设计处理，解决了传统集成电路中电感应用的一些弊端，例如：电感Q值低，电感值不可控，电感成本高，从而提高产品集成度，优化产品性能，降低产品成本。

Claims (5)

1.一种高Q值芯片集成电感，其特征在于，所述芯片中包括至少两个管芯，所述两个管芯上均设置有一条或多条金属走线，所述金属走线都相互平行，每条金属走线的末端均设置有键合区，多条键合线将两个管芯上的键合区相连接，使得键合线和金属走线组成一条螺旋状的通路。
2.根据权利要求1所述的高Q值芯片集成电感，其特征在于，所述两个管芯中一个管芯叠放在另一个管芯的上面，并且上面的管芯面积小于下面的管芯，下面的管芯的金属走线和键合区设置在两个管芯非重叠的区域。
3.根据权利要求1所述的高Q值芯片集成电感，其特征在于，所述两个管芯并排设置。
4.根据权利要求1所述的高Q值芯片集成电感，其特征在于，所述金属走线的材料为金、铜或者铝。
5.根据权利要求1所述的高Q值芯片集成电感，其特征在于，所述键合线的材料为金、铜或者铝。
CN2010101461990A 2010-04-14 2010-04-14 高q值芯片集成电感 Active CN101840906B (zh)

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US6194774B1 (en) * 1999-03-10 2001-02-27 Samsung Electronics Co., Ltd. Inductor including bonding wires
US6586309B1 (en) * 2000-04-24 2003-07-01 Chartered Semiconductor Manufacturing Ltd. High performance RF inductors and transformers using bonding technique
WO2004025695A2 (en) * 2002-09-10 2004-03-25 Semiconductor Components Industries L.L.C. Semiconductor device with wire bond inductor and method

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