CN101834184B

CN101834184B - Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube

Info

Publication number: CN101834184B
Application number: CN 201010130838
Authority: CN
Inventors: 宋波; 韩雁; 董树荣; 马飞; 黄大海; 李明亮; 苗萌
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2010-03-23
Filing date: 2010-03-23
Publication date: 2011-08-03
Anticipated expiration: 2030-03-23
Also published as: CN101834184A

Abstract

The invention discloses a substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube which is used for ESD (Electro-Static Discharge) protection of a core circuit and comprises a substrate, a source electrode and a ground grid electrode, wherein a drain electrode is connected with the GGNMOS tube of the input end of the core circuit; the drain electrode is connected with the substrate of the GGNMOS tube; the source electrode and the substrate are connected with the input end of the core circuit; and the grid electrode is connected with a PMOS (Positive-channel Metal Oxide Semiconductor ) tube of a VDD power line of the core circuit. The invention makes multiple GGNMOS tubes evenly opened and improves the robustness of devices by replacing Native NMOS with the PMOS and using the VDD as the control signal of the PMOS, the control circuit is greatly simplified by using the VDD as the control signal, and the area is not additionally increased.

Description

A kind of device with grounded-grid NMOS pipe of substrate triggering

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to the grounded-grid NMOS pipe that a kind of substrate triggers.

Background technology

Electrostatic Discharge is under the situation of an integrated circuit suspension joint, a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, about 100ns consuming time of whole process and integrated circuit are interior because friction etc. have been gathered electric charge in inside, the charge discharging resisting of inside is to the process on ground, the about about 1.5ns consuming time of this process when certain pin ground connection of integrated circuit.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very necessary with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic discharge protection circuit to release.

The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.

Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode; controllable silicon SCR (silicon controlled rectifier); GGNMOS (Grounded Gate NMOS; the metal-oxide-semiconductor of grounded-grid), wherein the NMOS of grounded-grid pipe (GGNMOS) is widely adopted.The electrical block diagram of this protective device as shown in Figure 1, the I/O end (I/O) of core circuit is received in the drain electrode 12 of GGNMOS, grid 13, source electrode 14 and substrate 11 all receive ground.For improving the resistance ESD ability of GGNMOS, the general many interdigital structures that adopt as shown in Figure 2.

But this how interdigital GGNMOS structure is because middle interdigital volume resistance maximum prior to other interdigital unlatchings, causes each interdigital can not evenly unlatching of GGNMOS.Cause the decline of the antistatic capacity of integrated circuit like this.Be directed to this, a kind of effective solution triggers GGNMOS by substrate being poured into electric current raising underlayer voltage exactly, as shown in Figure 3.But Native NMOS100 needs negative bias voltage to control in this scheme, has additionally increased a negative bias voltage module 200, has increased the complexity of circuit, and has increased whole area, has increased cost.

Summary of the invention

The invention provides the grounded-grid NMOS pipe that a kind of substrate simple in structure, with low cost and function admirable triggers.

The grounded-grid NMOS pipe that a kind of substrate triggers is used for the ESD protection of core circuit, comprising:

One GGNMOS pipe, substrate, source electrode and grounded-grid, drain electrode connects the input of core circuit;

One PMOS pipe, drain electrode connects the substrate of GGNMOS pipe, and source electrode is connected the input of core circuit with substrate, and grid connects the VDD power line of core circuit.

Described core circuit refers to be needed it is carried out the chip of electrostatic discharge protective.

When GGNMOS pipe for two when interdigital, the concrete structure of its device is as follows:

It comprises P type substrate, be marked with P trap and N trap on the described P type substrate, be provided with a P+ injection region, a N+ injection region, the 2nd N+ injection region, the 2nd P+ injection region, the 3rd N+ injection region, the 4th N+ injection region, the 3rd P+ injection region on the P trap from outside to inside successively, be provided with the 5th N+ injection region, the 5th P+ injection region and the 4th P+ injection region on the N trap 57 from outside to inside successively;

Be covered with stacked SiO on the N trap on the P trap on the P trap between the one N+ injection region and the 2nd N+ injection region, between the 3rd N+ injection region and the 4th N+ injection region, between the 5th P+ injection region and the 4th P+ injection region ₂Oxide layer and polysilicon layer are isolated by shallow trench between all the other injection regions;

Polysilicon layer between the one N+ injection region and the 2nd N+ injection region, a P+ injection region and a N+ injection region common ground; Polysilicon layer between the 3rd N+ injection region and the 4th N+ injection region, the 4th N+ injection region and the 3rd P+ injection region common ground; The 2nd N+ injection region, the 3rd N+ injection region, the 5th N+ injection region and the 5th P+ injection region are connected the input of core circuit; Polysilicon layer between the 5th P+ injection region and the 4th P+ injection region connects the VDD power line; The 2nd P+ injection region is connected by lead with the 4th P+ injection region.

Above-mentioned substrate triggers grounded-grid NMOS pipe and has set up a PMOS pipe on GGNMOS pipe next door, substituted original Native NMOS pipe, the source electrode of PMOS pipe and substrate are received the input of core circuit, drain electrode next door at the NMOS pipe has increased by the 2nd P+ injection region, the 2nd P+ injection region connects substrate, the drain electrode of PMOS pipe simultaneously is connected to the 2nd P+ injection region, and grid connects the VDD power line, and VDD is as control signal.

Under the ESD condition, when the core circuit input has esd pulse over the ground, vdd terminal is in floating dummy status, the grid of PMOS pipe is in floating dummy status, because the source electrode of PMOS pipe has very high esd pulse voltage, both voltage differences before of the grid of PMOS pipe and drain electrode are higher than its threshold voltage, and PMOS manages unlatching, electric current is injected in the substrate of GGNMOS pipe, has improved substrate electric potential and triggers the GGNMOS plumber and do; When operate as normal, VDD is a high potential, and the PMOS pipe ends, and the GGNMOS pipe is not worked.

The present invention with the control signal of VDD as PMOS, can make how interdigital GGNMOS evenly open by replace Native NMOS with PMOS, improves the robustness of device.Utilize VDD as control signal simplified control circuit greatly simultaneously, and additionally do not increase area again.

Description of drawings

Fig. 1 is the circuit theory diagrams of existing GGNMOS pipe;

Fig. 2 is the realization domain of existing how interdigital GGNMOS pipe;

Fig. 3 triggers the circuit theory diagrams of GGNMOS pipe for existing substrate;

Fig. 4 triggers the circuit theory diagrams of GGNMOS pipe for substrate of the present invention;

Fig. 5 is GGNMOS pipe longitudinal sectional drawing of the present invention;

Fig. 6 is the present invention's eight interdigital GGMOS pipes and existing eight interdigital GGMOS TLP test results.

Embodiment

As shown in Figure 4, the grounded-grid NMOS pipe that a kind of substrate triggers is used for the ESD protection of core circuit, comprising:

Many interdigital GGNMOS pipes 101, source electrode and grounded-grid, drain electrode connects the input Input of core circuit;

PMOS pipe 102, drain electrode connect the substrate of GGNMOS pipe 101, and source electrode is connected the input of core circuit with substrate, and grid connects the VDD power line of core circuit.

When GGNMOS pipe during for two interdigital structure, its longitudinal sectional drawing as shown in Figure 5, it comprises P type substrate 50, be marked with P trap 51 and N trap 57 on the P type substrate 50, be provided with P+ injection region 53a, N+ injection region 54a, N+ injection region 54b, P+ injection region 53b, N+ injection region 54c, N+ injection region 54d, P+ injection region 53c from outside to inside on the P trap 51 successively, from outside to inside, be marked with N+ injection region 54e, P+ injection region 53e and P+ injection region 53d on the N trap 57.

Be covered with stacked SiO on the N trap on the P trap on the P trap between N+ injection region 54a and the N+ injection region 54b, between N+ injection region 54c and the N+ injection region 54d, between P+ injection region 53e and the P+ injection region 53d ₂ Oxide layer 55 and polysilicon layer 56 are isolated by shallow trench 52 between all the other injection regions.

When core circuit is carried out electrostatic defending, the polysilicon layer between N+ injection region 54a and the N+ injection region 54b, P+ injection region 53a and N+ injection region 54a common ground; Polysilicon layer between N+ injection region 54c and the N+ injection region 54d, N+ injection region 54d and P+ injection region 53c common ground; N+ injection region 54b, N+ injection region 54c, N+ injection region 54e and P+ injection region 53e are connected the input Input of core circuit, and the polysilicon layer between P+ injection region 53e and the P+ injection region 53d connects the VDD power line of core circuit; P+ injection region 53b is connected with P+ injection region 53d.

N+ injection region 54e, P+ injection region 53d, P+ injection region 53e and the SiO above the corresponding region between the two ₂ PMOS pipe 102 in the common forming circuit of oxide layer and polysilicon layer; Injection region, the SiO of 53b both sides, P+ injection region in P trap 51 ₂The common GGNMOS pipe 101 that constitutes two slotting fingers of oxide layer and polysilicon layer.

The operation principle of foregoing circuit is as follows:

When the core circuit operate as normal, VDD is a high level, and PMOS pipe 102 ends, and the whole protection circuit does not have current path, thereby does not disturb the operate as normal of core circuit.And in the electrostatic signal of danger when input Input comes in, because vdd terminal is floating dummy status, because the source electrode of PMOS pipe 102 has very high esd pulse voltage, both voltage differences before of the grid of PMOS pipe and drain electrode are higher than its threshold voltage, PMOS manages 102 conductings, therefore PMOS pipe 102, P+ injection region 53b, P trap 51 and P+ injection region 53a constitute a current path, and PMOS pipe 102, P+ injection region 53b, P trap 51 and P+ injection region 53d constitute a current path.At this moment can raise the voltage on P trap 51 dead resistance Rpw, improve GGNMOS and manage 101 substrate electric potentials, make and distinguish conducting with the diode that N+ injection region 54d constitutes by P trap 51 and N+ injection region 54a and P trap 51, GGNMOS manages the bipolar transistor of 101 parasitisms and just opens, and at this moment electrostatic charge is just mainly released by GGNMOS pipe 101.By pouring into the whole current potential that improves substrate of electric current, each interdigitally can evenly open the conducting leakage current like this, thereby makes electrostatic charge be unlikely to jeopardize core circuit, has protected the safety of core circuit.

With transmission line pulse generator (TLP) test common eight interdigital GGNMOS pipes and the present invention's eight interdigital GGNMOS pipes, the result as shown in Figure 6.The inefficacy electric current I t2 of common eight interdigital GGNMOS is 4.14A, and the inefficacy electric current I t2 of the present invention eight interdigital GGNMOS brings up to 4.7A, and comparing has increased by 13.6%.

Claims

1. the device with grounded-grid NMOS pipe of substrate triggering is used for the ESD protection of core circuit, it is characterized in that, comprising:

Interdigital grounded-grid NMOS pipe (101) more than one, its substrate, source electrode and grounded-grid, its drain electrode connects the input of core circuit;

One PMOS manages (102), and the drain electrode of this PMOS pipe connects the substrate of how interdigital grounded-grid NMOS pipe (101), and the source electrode of this PMOS pipe is connected the input of core circuit with substrate, and the grid of this PMOS pipe connects the VDD power line of core circuit.

2. the device with grounded-grid NMOS pipe of substrate triggering according to claim 1, it is characterized in that: comprise P type substrate (50), described P type substrate (50) is provided with P trap (51) and N trap (57), P trap (51) is gone up from being provided with a P+ injection region (53a) successively away from N trap one side direction N trap direction, the one N+ injection region (54a), the 2nd N+ injection region (54b), the 2nd P+ injection region (53b), the 3rd N+ injection region (54c), the 4th N+ injection region (54d), go up from being provided with the 5th N+ injection region (54e) successively away from P trap one side direction P trap direction the 3rd P+ injection region (53c), N trap (57), the 5th P+ injection region (53e) and the 4th P+ injection region (53d);

Be covered with stacked SiO on the N trap on the P trap on the P trap between the one N+ injection region (54a) and the 2nd N+ injection region (54b), between the 3rd N+ injection region (54c) and the 4th N+ injection region (54d), between the 5th P+ injection region (53e) and the 4th P+ injection region (53d) ₂Oxide layer and polysilicon layer are isolated by shallow trench (52) between all the other injection regions;

Polysilicon layer between the one N+ injection region (54a) and the 2nd N+ injection region (54b), a P+ injection region (53a) and N+ injection region (54a) common ground;

Polysilicon layer between the 3rd N+ injection region (54c) and the 4th N+ injection region (54d), the 4th N+ injection region (54d) and the 3rd P+ injection region (53c) common ground;

The 2nd N+ injection region (54b), the 3rd N+ injection region (54c), the 5th N+ injection region (54e) and the 5th P+ injection region (53e) are connected the input of core circuit;

Polysilicon layer between the 5th P+ injection region (53e) and the 4th P+ injection region (53d) connects the VDD power line;

The 2nd P+ injection region (53b) is connected by lead with the 4th P+ injection region (53d).