CN101834184B - Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube - Google Patents

Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube Download PDF

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CN101834184B
CN101834184B CN 201010130838 CN201010130838A CN101834184B CN 101834184 B CN101834184 B CN 101834184B CN 201010130838 CN201010130838 CN 201010130838 CN 201010130838 A CN201010130838 A CN 201010130838A CN 101834184 B CN101834184 B CN 101834184B
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substrate
well
connected
implanted region
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CN101834184A (en
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宋波
李明亮
苗萌
董树荣
韩雁
马飞
黄大海
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浙江大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention discloses a substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube which is used for ESD (Electro-Static Discharge) protection of a core circuit and comprises a substrate, a source electrode and a ground grid electrode, wherein a drain electrode is connected with the GGNMOS tube of the input end of the core circuit; the drain electrode is connected with the substrate of the GGNMOS tube; the source electrode and the substrate are connected with the input end of the core circuit; and the grid electrode is connected with a PMOS (Positive-channel Metal Oxide Semiconductor ) tube of a VDD power line of the core circuit. The invention makes multiple GGNMOS tubes evenly opened and improves the robustness of devices by replacing Native NMOS with the PMOS and using the VDD as the control signal of the PMOS, the control circuit is greatly simplified by using the VDD as the control signal, and the area is not additionally increased.

Description

一种具有衬底触发的栅极接地NMOS管的器件 Device having a grounded gate NMOS substrate tube trigger

技术领域 FIELD

[0001] 本发明涉及集成电路技术领域,尤其涉及一种衬底触发的栅极接地NMOS管。 [0001] The present invention relates to integrated circuit technology, and particularly relates to a gate-grounded NMOS transistor substrate triggered. 背景技术 Background technique

[0002] 静电放电(ESD)是在一个集成电路浮接的情况下,大量的电荷从外向内灌入集成电路的瞬时过程,整个过程大约耗时IOOns以及集成电路内由于摩擦等积聚了电荷在内部,当集成电路的某个管脚接地时内部的电荷泄放到地的过程,这个过程大约耗时约1. 5ns。 [0002] Electrostatic discharge (ESD) in the case of a floating IC, large amount of charge transient process poured from the outside of the integrated circuit, the whole process takes approximately IOOns and the like due to friction within an integrated circuit charge accumulation internally, when a ground pin of the integrated circuit of the charge released to the inside of the process, this process takes approximately about 1. 5ns. 此外,在集成电路放电时会产生数百甚至数千伏特的高压,这会打穿集成电路中的输入级的栅氧化层。 Further, when the integrated circuit generates discharge hundreds or even thousands of volts high voltage, the input stage of the gate oxide layer in the integrated circuit which can punch through. 随着集成电路中的MOS管的尺寸越来越小,栅氧化层的厚度也越来越薄,在这种趋势下,使用高性能的静电防护电路来泄放静电放电的电荷以保护栅极氧化层不受损害是十分必要的。 As the size of MOS transistors in integrated circuits become smaller, the thickness of the gate oxide layer is getting thinner, this trend, the use of high-performance ESD protection circuit to bleed charge to the electrostatic discharge protection gate the oxide layer from damage is very necessary.

[0003] 静电放电现象的模式主要有四种:人体放电模式(HBM)、机械放电模式(MM)、器件充电模式(CDM)以及电场感应模式(FIM)。 [0003] Electrostatic discharge phenomenon, there are four modes: the Human Body Model (HBM), machine discharge mode (MM), a charging device mode (CDM), and electric field sensing mode (FIM). 对一般集成电路产品来说,一般要经过人体放电模式,机械放电模式以及器件充电模式的测试。 General IC products, generally through the body discharge mode, the discharge mode mechanical testing device and the charging mode. 为了能够承受如此高的静电放电电压,集成电路产品通常必须使用具有高性能、高耐受力的静电放电保护器件。 To be able to withstand such a high voltage electrostatic discharge, an integrated circuit products typically must use electrostatic discharge protection device having a high performance, high tolerance of.

[0004] 为了达成保护芯片抵御静电袭击的目的,目前已有多种静电防护器件被提出,比如二极管,可控硅SCR(silicon controlled rectifier),GGNMOS(Grounded Gate NMOS,栅极接地的MOS管),其中栅极接地的NMOS管(GGNMOS)被广泛采用。 [0004] In order to achieve the purpose of protecting the chip against the static electricity attack, there have been proposed a variety of electrostatic protection devices, such as a diode, thyristor SCR (silicon controlled rectifier), GGNMOS (Grounded Gate NMOS, the grounded-gate MOS transistor) wherein grounded gate NMOS transistor (the GGNMOSs) are widely used. 该防护器件的电路结构示意图如图1所示,GGNMOS的漏极12接到核心电路的输入/输出端(1/0),栅极13、源极14和衬底11都接到地。 The protective device is a circuit configuration diagram shown in Figure 1, the core circuit 12 to the input / output terminal of the drain GGNMOS (1/0), the gate electrode 13, source electrode 14 and the substrate 11 are connected to ground. 为提高GGNMOS的抗击ESD能力,一般采用如图2所示的多叉指结构。 To improve the ability to fight against ESD GGNMOS generally multi-finger fork structure shown in FIG.

[0005] 但是这种多叉指的GGNMOS结构由于中间的叉指的体电阻最大,先于其他叉指开启,造成GGNMOS的各个叉指不能均勻开启。 [0005] However, this structure GGNMOS plurality of interdigitated interdigital because the volume resistivity of the intermediate maximum, prior to the other interdigital open, causing each fork finger GGNMOS not uniformly opened. 这样造成整体电路的静电防护能力的下降。 Such ability to cause a decline in the overall ESD protection circuit. 针对于此,一种行之有效的解决方案就是通过对衬底灌入电流提高衬底电压来触发GGNM0S, 如图3所示。 For this, an effective solution is poured into a substrate by a substrate voltage triggered current increase GGNM0S, as shown in FIG. 但是这种方案中Native NM0S100需要负偏置电压来控制,额外增加了一个负偏置电压模块200,增加了电路的复杂性,而且增加了整体的面积,增大了成本。 However, this scheme requires Native NM0S100 negative bias voltage to control an additional negative bias voltage module 200, increases the complexity of the circuit, but also increases the overall area, increases the cost.

发明内容 SUMMARY

[0006] 本发明提供了一种结构简单、成本低廉且性能优良的衬底触发的栅极接地NMOS管。 [0006] The present invention provides a grounded gate NMOS transistor with simple structure, low cost and good performance of the substrate is triggered.

[0007] 一种衬底触发的栅极接地NMOS管,用于核心电路的ESD防护,包括: [0007] A substrate-triggered grounded gate NMOS transistor for ESD protection of the core circuit, comprising:

[0008] 一GGNMOS管,衬底、源极和栅极接地,漏极连接核心电路的输入端; [0008] GGNMOS a tube, a substrate, a source and a gate to ground input terminal, a drain connected to the core circuit;

[0009] 一PMOS管,漏极连接GGNMOS管的衬底,源极和衬底连接核心电路的输入端,栅极连接核心电路的VDD电源线。 [0009] The core circuit connected to an input terminal a PMOS transistor, a drain connected to the substrate GGNMOS tube, source and substrate, a gate connected to VDD power supply line of the core circuit.

[0010] 所述核心电路指的是需对其进行静电放电防护的芯片。 [0010] The core circuit refers to the need to be chip ESD protection.

[0011] 当GGNMOS管为双叉指时,其器件的具体结构如下: [0011] When a double tube GGNMOS interdigitated, the specific structure of the device is as follows:

3[0012] 它包括P型衬底,所述的P型衬底上注有P阱和N阱,P阱上从外向内依次设有第一P+注入区、第一N+注入区、第二N+注入区、第二P+注入区、第三N+注入区、第四N+注入区、第三P+注入区,N阱57上从外向内依次设有第五N+注入区、第五P+注入区和第四P+注入区; 3 [0012] It comprises a P-type substrate, impregnated with the P-type substrate P well and N-well from the outside are sequentially provided on a first P + implanted P-well region, a first N + implanted region, a second N + injection region, a second P + implantation zone, a third N + implanted region, a fourth N + injection region, the third P + implantation zone, successively with a fifth N + implanted region from the outside to the N-well 57, the fifth P + injection region and a fourth P + implant regions;

[0013] 第一N+注入区和第二N+注入区之间的P阱上、第三N+注入区和第四N+注入区之间的P阱上、第五P+注入区和第四P+注入区之间的N阱上覆有层叠的SiA氧化层和多晶硅层,其余注入区之间通过浅沟槽进行隔离; Between the P-well [0013] First the N + implantation zone and the second N + implanted region, a third P-well between the N + implantation zone and the fourth N + implanted region, the fifth and fourth P + P + implanted region implanted region covered with laminated between the N-well oxide layer and a polysilicon layer SiA, implanted between the remaining region by a shallow trench isolation;

[0014] 第一N+注入区和第二N+注入区之间的多晶硅层、第一P+注入区和第一N+注入区共同接地;第三N+注入区和第四N+注入区之间的多晶硅层、第四N+注入区和第三P+注入区共同接地;第二N+注入区、第三N+注入区、第五N+注入区和第五P+注入区连接核心电路的输入端;第五P+注入区和第四P+注入区之间的多晶硅层连接VDD电源线;第二P+ 注入区与第四P+注入区通过导线连接。 A third polysilicon layer between the N + implantation zone and the fourth N + implant regions; [0014] The first N + polysilicon layer common ground between the injection region and the second N + implanted region, a first P + injection region and the first N + implanted region , common ground fourth N + implanted region and a third P + implantation region; link core circuit input terminal of a second N + implanted region, a third N + implanted region, a fifth N + implantation zone and a fifth P + implant regions; fifth P + implanted region and a fourth polysilicon layer between the P + implantation zone connecting the power supply line VDD; the second implanted P + P + implanted region and the fourth region is connected by a wire.

[0015] 上述衬底触发栅极接地NMOS管在GGNMOS管旁边增设了一个PMOS管,替代了原来的Native NMOS管,PMOS管的源极和衬底接到核心电路的输入端,在NMOS管的漏极旁边增加了第二P+注入区,第二P+注入区连接衬底,同时PMOS管的漏极连接到第二P+注入区, 栅极连接VDD电源线,VDD作为控制信号。 [0015] The substrate-triggered grounded gate NMOS transistor GGNMOS tube alongside the addition of a PMOS transistor, to replace the original Native NMOS transistor, and the source of the PMOS transistor is connected to the substrate core circuit input terminal, the NMOS transistor next added a second P + drain implanted region, a second region connected to the P + doping of the substrate, while the drain of the second PMOS transistor is connected to the P + implanted region, a gate connected to VDD power supply line, VDD as the control signal.

[0016] 在ESD条件下,当核心电路输入端对地有ESD脉冲时,VDD端处于浮空状态,PMOS 管的栅极处于浮空状态,由于PMOS管的源极有很高的ESD脉冲电压,PMOS管的栅极和漏极两者之前的电压差高于其阈值电压,PMOS管开启,电流注入到GGNMOS管的衬底中,提高了衬底电位而触发GGNMOS管工作;在正常工作时,VDD为高电位,PMOS管截止,GGNMOS管不工作。 [0016] Under ESD conditions, when the core circuit has an input terminal to ground an ESD pulse, the VDD terminal is in a floating state, the gate of the PMOS transistor in a floating state, since the source of the PMOS transistor is a high voltage ESD pulse , the voltage difference between the two previous gate and drain of the PMOS transistor is higher than its threshold voltage, the PMOS is turned on, current is injected into the substrate tube GGNMOS improved substrate potential trigger GGNMOS work tube; during normal operation , VDD is a high potential, PMOS tube end, GGNMOS tube does not work.

[0017] 本发明通过用PMOS来取代Native NMOS,用VDD作为PMOS的控制信号,既能使得多叉指GGNMOS均勻开启,提高器件的鲁棒性。 [0017] The present invention is replaced by a PMOS Native NMOS, PMOS used as a control signal to VDD, such that both open multiple interdigital GGNMOS uniform, to improve the robustness of the device. 同时利用VDD作为控制信号能大大简化控制电路,而且又不额外增加面积。 While using as a control signal VDD can greatly simplify the control circuit, and without additional areas.

附图说明 BRIEF DESCRIPTION

[0018] 图1为现有GGNMOS管的电路原理图; [0018] FIG. 1 is a schematic circuit diagram of a conventional tube GGNMOS;

[0019] 图2为现有多叉指GGNMOS管的实现版图; [0019] FIG 2 is a conventional multi tube GGNMOS interdigitated layout of realization;

[0020] 图3为现有衬底触发GGNMOS管的电路原理图; [0020] FIG. 3 GGNMOS trigger circuit diagram of a conventional substrate tube;

[0021] 图4为本发明衬底触发GGNMOS管的电路原理图; [0021] FIG. 4 GGNMOS flop circuit diagram of the present invention, the substrate tube;

[0022] 图5为本发明GGNMOS管纵向剖面图; [0022] FIG. 5 GGNMOS longitudinal sectional view of the tube of the present invention;

[0023] 图6为本发明八叉指GGMOS管与现有八叉指GGMOS TLP测试结果。 [0023] FIG. 6 eight tubes GGMOS interdigitated interdigital prior eight GGMOS the TLP test results of the present invention. 具体实施方式 detailed description

[0024] 如图4所示,一种衬底触发的栅极接地NMOS管,用于核心电路的ESD防护,包括: [0024] As shown, a substrate-triggered grounded gate NMOS transistor 4, the ESD protection for the core circuit, comprising:

[0025] 多叉指的GGNMOS管101,源极和栅极接地,漏极连接核心电路的输入端Input ; [0025] The plurality of interdigital GGNMOS tube 101, source and gate grounded, a drain connected to the input terminal Input core circuitry;

[0026] PMOS管102,漏极连接GGNMOS管101的衬底,源极和衬底连接核心电路的输入端, 栅极连接核心电路的VDD电源线。 [0026] PMOS tube 102, the substrate GGNMOS drain pipe 101 is connected to the circuit input terminal connected to the core source and substrate, a gate connected to VDD power supply line of the core circuit.

[0027] 当GGNMOS管为双叉指结构时,其纵向剖面图如图5所示,它包括P型衬底50,P型衬底50上注有P阱51和N阱57,从外向内P阱51上依次设有P+注入区53a、N+注入区54a、N+注入区54b、P+注入区53b、N+注入区54c、N+注入区54d、P+注入区53c,从外向内,N阱57上注有N+注入区54e、P+注入区5!3e和P+注入区53d。 [0027] When a double tube GGNMOS interdigital structure whose longitudinal cross-sectional view shown in Figure 5, which includes a P-type substrate 50, P type substrate 50 marked with P-well 51 and N-well 57, from the inside outward P the well 51 in turn is provided with P + implanted region 53a, N + implanted region 54a, N + implanted region 54b, P + implanted region 53b, N + implanted region 54c, N + implanted region 54d, P + implanted region 53c, from the outside, N-well 57 Note an N + implanted region 54e, P + implanted region 5! 3e and the P + implanted region 53d.

[0028] N+注入区54a和N+注入区54b之间的P阱上、N+注入区54c和N+注入区54d之间的P阱上、P+注入区5¾和P+注入区53d之间的N阱上覆有层叠的SiA氧化层55和多晶硅层56,其余注入区之间通过浅沟槽52进行隔离。 + On a P-well between the implanted region 54b, the P-well between 54d N + implanted region 54c and N + implanted regions, the [0028] N + implanted regions 54a and N N-well between 53d is P + implanted region 5¾ and the P + implanted region SiA stacked oxide coated with layers 55 and polysilicon layer 56, to rest between the isolation implant region by a shallow trench 52.

[0029] 对核心电路进行静电防护时,N+注入区5½和N+注入区54b之间的多晶硅层、P+ 注入区53a和N+注入区5½共同接地;N+注入区5½和N+注入区54d之间的多晶硅层、 N+注入区54d和P+注入区53c共同接地;N+注入区54b、N+注入区54c、N+注入区54e和P+注入区5¾连接核心电路的输入端hput,P+注入区5¾和P+注入区53d之间的多晶硅层连接连接核心电路的VDD电源线;P+注入区53b与P+注入区53d连接。 [0029] When a core circuit electrostatic protection, N + implanted region 5½ and N + implanted polysilicon layer between the region 54b, P + implanted region 53a and N + implanted 5½ common ground region; between 54d N + implanted region 5½ and N + implanted region 53c common ground polysilicon layer, N + implanted region 54d and the P + implantation zone; N + implanted region 54b, N + implanted region 54c, N + implanted region 54e and the P + implantation zone 5¾ connected to the core circuit input terminal hput, P + implant regions 5¾ and the P + implanted region the polysilicon layer 53d are connected between the power supply line VDD is connected to the core circuit; 53b connected to the P + implantation zone and the P + implanted region 53d.

[0030] N+注入区54e、P+注入区53d、P+注入区53e以及二者之间对应区域上方的SW2 氧化层和多晶硅层共同构成电路中的PMOS管102 ;在P阱51中P+注入区5¾两侧的注入区、SiO2氧化层和多晶硅层共同构成双插指的GGNMOS管101。 [0030] N + implanted region 54e, corresponding to SW2 oxide layer over the region and the polysilicon layer jointly constitute a circuit PMOS transistor 102 between the P + implanted region 53d, P + implant regions 53e and both; in P + implanted region P-well 51 5¾ both sides of the implanted region, SiO2 oxide layer and the polysilicon layer jointly constitute a double tube GGNMOS interpolation means 101.

[0031] 上述电路的工作原理如下: Working Principle [0031] The above-described circuit is as follows:

[0032] 当核心电路正常工作时,VDD为高电平,PMOS管102截止,整个防护电路没有电流通路,因而不干扰核心电路的正常工作。 [0032] When the core circuit is working properly, the VDD is high, the PMOS tube 102 is turned off, no current path entire protection circuit, and therefore does not interfere with normal operation of core circuit. 而在危险的静电信号从输入端化? In danger of electrostatic signal from the input terminal? 此进来的时候, 由于VDD端为浮空状态,由于PMOS管102的源极有很高的ESD脉冲电压,PMOS管的栅极和漏极两者之前的电压差高于其阈值电压,PMOS管102导通,因此PMOS管102、P+注入区53b、P阱51、以及P+注入区53a构成一条电流通路,PMOS管102、P+注入区53b、P阱51、 以及P+注入区53d构成一条电流通路。 This came in since the VDD terminal is in a floating state, since the source electrode of the PMOS transistor 102 has a high voltage ESD pulse, the voltage difference between the gate and drain both before PMOS transistor is higher than its threshold voltage, the PMOS 102 is turned on, the PMOS transistor 102, a P + implantation zone 53b, P-well 51 and the P + implanted region 53a constituting a current path, the PMOS transistor 102, a P + implantation zone 53b, P-well 51 and the P + implantation region 53d constituting a current path . 这时会抬高在P阱51寄生电阻Rpw上的电压,提高GGNMOS管101衬底电位,使得由P阱51与N+注入区5½和P阱51与N+注入区54d构成的二极管分别导通,GGNMOS管101寄生的双极型晶体管就打开,这时静电电荷就主要通过GGNMOS管101泄放掉。 In this case 51 will raise the voltage across the parasitic resistance Rpw P-well, to improve the substrate potential GGNMOS tube 101, so that the P-well region 51 and 5½ by the P-well and N + 51 and N + implanted region implanted diodes 54d are turned on, GGNMOS tube parasitic bipolar transistor 101 is opened, then the electrostatic charge on the main pipe 101 exhausting through GGNMOS. 通过灌入电流来整体提高衬底的电位,这样各个叉指能够均勻开启导通泄放电流,从而使静电电荷不至于危害到核心电路,保护了核心电路的安全。 Sink current through the substrate to an overall increase of the potential, so that the respective interdigital uniformly open bleeder current conduction, so that the electrostatic charge to the core will not harm to protect the security of the core circuit.

[0033] 用传输线脉冲发生器(TLP)测试普通八叉指GGNMOS管和本发明八叉指GGNMOS 管,结果如图6所示。 [0033] The pulse generator by a transmission line (TLP) test ordinary eight interdigital octree GGNMOS tubes and pipes of the present invention refers to GGNMOS results shown in Figure 6. 普通八叉指GGNMOS的失效电流112为4. 14A,而本发明八叉指GGNMOS 的失效电流It2提高到4. 7A,相比增加了13. 6%。 Common failure octree means 112 is current GGNMOS 4. 14A, while the present invention refers to an octree GGNMOS failure current It2 is increased to 4. 7A, compared to an increase of 13.6%.

Claims (2)

1. 一种具有衬底触发的栅极接地NMOS管的器件,用于核心电路的ESD防护,其特征在于,包括:一多叉指栅极接地NMOS管(101),其衬底、源极和栅极接地,其漏极连接核心电路的输入端;一PMOS管(102),该PMOS管的漏极连接多叉指栅极接地NMOS管(101)的衬底,该PMOS 管的源极和衬底连接核心电路的输入端,该PMOS管的栅极连接核心电路的VDD电源线。 A device having a grounded gate NMOS transistor substrate triggered ESD protection for core circuitry, characterized by comprising: more than one interdigital grounded gate NMOS transistor (101) substrate, a source and a gate grounded circuit is connected to an input terminal of the drain core; a PMOS transistor connected to the drain (102), the plurality of interdigital PMOS transistor substrate grounded gate NMOS transistor (101), a source electrode of the PMOS transistor and a core circuit connected to the input terminal of the substrate, a gate of the PMOS transistor is connected to VDD power supply line core circuit.
2.根据权利要求1所述的具有衬底触发的栅极接地NMOS管的器件,其特征在于:包括P型衬底(50),所述的P型衬底(50)上设有P阱(51)和N阱(57),P阱(51)上从远离N 阱一侧向N阱方向依次设有第一P+注入区(53a)、第一N+注入区(5½)、第二N+注入区(54b)、第二P+注入区(5¾)、第三N+注入区(5½)、第四N+注入区(54d)、第三P+注入区(53c),N阱(57)上从远离P阱一侧向P阱方向依次设有第五N+注入区(5½)、第五P+注入区(53e)和第四P+注入区(53d);第一N+注入区(Ma)和第二N+注入区(Mb)之间的P阱上、第三N+注入区(Mc)和第四N+注入区(Md)之间的P阱上、第五P+注入区(53e)和第四P+注入区(53d)之间的N阱上覆有层叠的SiO2氧化层和多晶硅层,其余注入区之间通过浅沟槽(52)进行隔离;第一N+注入区(Ma)和第二N+注入区(Mb)之间的多晶硅层、第一P+注入区(53a) 和第一N+注入区(Ma)共 The grounded-gate NMOS transistor device having a substrate of the trigger to claim 1, further comprising: a P-type substrate (50), said P-type substrate is provided on a P-well (50) (51) and the N well (57), P-well (51) sequentially from a side remote from the N-well is provided with a first P + implantation zone (53a) the direction of the N-well, a first N + implantation zone (5½), a second N + implanted region (54b), a second P + implant region (5¾), a third N + implantation zone (5½), a fourth N + implanted region (54d), the third P + implantation zone (53c), N-well on (57) remote from P-well with a side of the fifth order N + implant region (5½) direction of the P-well, P + fifth implant region (53e) and fourth P + implanted region (53d is); a first N + implant region (Ma) and a second N + between the P-well implant region (Mb), the third P-well between N + implantation zone (Mc) and a fourth N + implanted region (Md), a fifth P + implant region (53e) and fourth P + implanted region covered with SiO2 stacked polysilicon layer and the oxide layer between the N well (53d), remaining between the injection region by a shallow trench isolation (52); a first N + implant region (Ma) and a second N + implant region ( between polysilicon layer Mb), a first P + implantation zone (53a) and a first N + implant region (Ma) co 接地;第三N+注入区(Mc)和第四N+注入区(Md)之间的多晶硅层、第四N+注入区(Md) 和第三P+注入区(53c)共同接地;第二N+注入区(54b)、第三N+注入区(5½)、第五N+注入区(Me)和第五P+注入区(53e)连接核心电路的输入端;第五P+注入区(53e)和第四P+注入区(53d)之间的多晶硅层连接VDD电源线; 第二P+注入区(53b)与第四P+注入区(53d)通过导线连接。 Common ground between the third polysilicon layer N + implantation zone (Mc) and a fourth N + implanted region (Md), a fourth N + implanted region (Md) and a third P + implanted region (53c);; Ground second N + implant region (54b), a third N + implantation zone (5½), a fifth N + implantation zone (Me), and a fifth P + implant region (53e) connected to the core circuit input terminal; fifth P + implant region (53e) and fourth P + implantation the region between the polysilicon layer (53d is) connected to the power supply line VDD; the second P + implanted region (53b) and fourth P + implanted region (53d is) is connected by a wire.
CN 201010130838 2010-03-23 2010-03-23 Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube CN101834184B (en)

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