CN100446239C - Electrostatic protection circuit in integrated circuit - Google Patents
Electrostatic protection circuit in integrated circuit Download PDFInfo
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- CN100446239C CN100446239C CNB2005101111765A CN200510111176A CN100446239C CN 100446239 C CN100446239 C CN 100446239C CN B2005101111765 A CNB2005101111765 A CN B2005101111765A CN 200510111176 A CN200510111176 A CN 200510111176A CN 100446239 C CN100446239 C CN 100446239C
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Abstract
The protection circuit includes hyperdactylia paralleled GGNMOS circuit, and diode. Drain pole of GGNMOS is connected to previous stage of internal circuit. Source pole of the middle GGNMOS and substrate are connected to anode of the diode, and grid pole is connected to ground. Source poles and grid poles of the other GGNMOS are connected to ground, and substrates connected to each other are connected to anode of the diode. Cathode of diode is connected to ground. When ESD occurs, the middle GGNMOS is turned to on first so as to generate bias voltage at diode, and provide the bias for substrates of all peripheral GGNMOS. Thus, all GGNMOS in the protection circuit are turned to open uniformly. The invention is suitable for manufacturing IC.
Description
Technical field
The present invention relates to integrated circuit and make the field, relate in particular to the electrostatic discharge protective circuit in a kind of integrated circuit.
Background technology
Integrated circuit is easy to be subjected to the destruction of static, generally all can design electrostatic discharge protective circuit in the input and output terminal of circuit or power protection and be damaged because of receiving static to prevent internal circuit.GGNMOS (Gate Grounded NMOS, the N type MOS transistor of grounded-grid) is a kind of widely used electrostatic preventing structure.Fig. 1 is the GGNMOS electrical block diagram.As shown in Figure 1,3 is GGNOMOS, and wherein the previous stage of the drain electrode 4 of GGNOMOS and internal circuit 2 is connected, and source electrode 6, grid 5 and substrate 7 be ground connection all.Fig. 2 is the domain that refers to GGNMOS circuit in parallel more.As shown in Figure 2, for guaranteeing certain protection intensity, with several GGNMOS parallel connections.Adopt and refer to that GGNMOS circuit in parallel carries out electrostatic protection to integrated circuit and can improve protection intensity more.
Fig. 3 refers to GGNMOS circuit schematic cross-section in parallel more.As shown in Figure 3, be P trap 12 on the P type substrate 13, on the described P trap 12 resistance substrate is arranged, the one end is connected with the base stage of triode 15, the other end is connected with P+ diffusion region 10, the emitter and collector of triode connects N+ diffusion region 11 respectively, and an isolation 8 is arranged between P+ diffusion region 10 and the N+ diffusion region 11.When static takes place because the diverse location transistor can cause the protective circuit unlatching inhomogeneous to the difference of the volume resistance of P type trap control; at middle GGNMOS device; because it is from the control of P type trap farthest, the resistance substrate maximum, the easiest of other GGNMOS devices unlatchings.When this when P type trap control GGNMOS device is farthest opened, other GGNMOS devices are not also opened.
GGNMOS device in the electrostatic discharge protective circuit of prior art can not be opened uniformly, has reduced the Global Macros ability of electrostatic discharge protective circuit.
Summary of the invention
Technical problem to be solved by this invention provides a kind of electrostatic discharge protective circuit of integrated circuit, can make to refer to that each GGNMOS device is opened more uniformly in the GGNMOS circuit in parallel, improves the ability of whole electrostatic protection more.
For solving the problems of the technologies described above; electrostatic discharge protective circuit in the integrated circuit of the present invention; comprise and refer to GGNMOS circuit in parallel more; the drain electrode of GGNMOS connects the previous stage of internal circuit; also comprise diode; wherein middle GGNMOS source end and substrate are connected with the negative electrode of diode; grounded-grid; should refer to other GGNMOS source end ground connection in the GGNMOS circuit in parallel more; grounded-grid; substrate interconnects and is connected with the negative electrode of diode; the plus earth of diode; when static release took place, middle described GGNMOS conducting at first produced bias voltage at described diode; supply with all GGNMOS substrate bias of other all peripheries, GGNMOS all in the protective circuit is opened evenly.
Compared with the prior art; the electrostatic discharge protective circuit of a kind of integrated circuit of the present invention; the source end that refers to the GGNMOS that GGNMOS circuit in parallel is middle connects an anti-phase diode more; can be after electrostatic discharge protective circuit takes place to puncture conducting; produce bias voltage at this diode; supply with all GGNMOS substrate bias of other all peripheries; can make the faster unlatching of parasitic NPN triode; GGNMOS all in the protective circuit is opened evenly, and circuit of the present invention can better provide electrostatic protection.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is a prior art GGNMOS electrical block diagram;
Fig. 2 refers to the domain of GGNMOS circuit in parallel more for prior art;
Fig. 3 refers to GGNMOS circuit schematic cross-section in parallel for prior art more;
Fig. 4 is an electrical block diagram of the present invention.
Embodiment
Fig. 4 is the electrostatic protection circuit structure schematic diagram of a kind of integrated circuit of the present invention.The present invention refers to improve on the GGNMOS circuit base in parallel at the electrostatic discharge protective circuit of prior art more.As shown in Figure 4, comprise a plurality of GGNMOS devices, the source end of middle GGNMOS device 18, substrate are connected with the negative electrode of a diode 16, its grounded-grid, and drain electrode connects the previous stage of internal circuit 2.The plus earth of above-mentioned diode 16.Except middle GGNMOS18, the drain electrode of other GGNMOS17 connects internal circuit 2 and input/output signal 1, and its substrate interconnects and is connected source electrode and grounded-grid with the negative electrode of diode 16.
When device is worked; the electrostatic discharge protective circuit of a kind of integrated circuit of the present invention; from P trap control farthest, volume resistance maximum, the middle GGNMOS device source end opened prior to other GGNOMS devices easily connect a diode; after electrostatic discharge protective circuit takes place to puncture conducting; can produce bias voltage at this diode, the substrate bias of the bias voltage of generation all GGNMOS of all peripheries to other.This active mode provide the bias voltage form to substrate, make the transistor unlatching that comparatively fast is triggered, big current capacity is arranged.Can make simultaneously and open evenly, better electrostatic protection effect is arranged.
Claims (1)
1. the electrostatic discharge protective circuit in the integrated circuit; it is characterized in that; comprise and refer to GGNMOS circuit in parallel more; the drain electrode of GGNMOS connects the previous stage of internal circuit; also comprise diode; wherein middle GGNMOS source end and substrate are connected with the negative electrode of diode; grounded-grid; should refer to other GGNMOS source end ground connection in the GGNMOS circuit in parallel more; grounded-grid; substrate interconnects and is connected with the negative electrode of diode; the plus earth of diode; when static release took place, middle described GGNMOS conducting at first produced bias voltage at described diode; supply with all GGNMOS substrate bias of other all peripheries, GGNMOS all in the protective circuit is opened evenly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101111765A CN100446239C (en) | 2005-12-06 | 2005-12-06 | Electrostatic protection circuit in integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101111765A CN100446239C (en) | 2005-12-06 | 2005-12-06 | Electrostatic protection circuit in integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979844A CN1979844A (en) | 2007-06-13 |
| CN100446239C true CN100446239C (en) | 2008-12-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101111765A Active CN100446239C (en) | 2005-12-06 | 2005-12-06 | Electrostatic protection circuit in integrated circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN100446239C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834184B (en) * | 2010-03-23 | 2011-08-03 | 浙江大学 | Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001097358A1 (en) * | 2000-06-15 | 2001-12-20 | Sarnoff Corporation | Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits |
| CN1489210A (en) * | 2002-10-08 | 2004-04-14 | 台湾积体电路制造股份有限公司 | Static discharge protection circuit and relative metal oxide semiconductor transistor structure |
| CN1510749A (en) * | 2002-12-23 | 2004-07-07 | 矽统科技股份有限公司 | Electrostatic discharge protective circuit with self-trigger function |
| US20040164354A1 (en) * | 2001-06-14 | 2004-08-26 | Sarnoff Corporation | Minimum-dimension, fully- silicided MOS driver and ESD protection design for optimized inter-finger coupling |
| CN1542961A (en) * | 2003-04-29 | 2004-11-03 | 矽统科技股份有限公司 | Electrostatic discharge protective circuit having uniform conducting design |
| CN1577836A (en) * | 2003-07-28 | 2005-02-09 | 恩益禧电子股份有限公司 | Polydactylism type electrostatic discharging protection elements |
| US20050082621A1 (en) * | 2003-10-01 | 2005-04-21 | Jau-Wen Chen | Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process |
-
2005
- 2005-12-06 CN CNB2005101111765A patent/CN100446239C/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001097358A1 (en) * | 2000-06-15 | 2001-12-20 | Sarnoff Corporation | Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits |
| US20040164354A1 (en) * | 2001-06-14 | 2004-08-26 | Sarnoff Corporation | Minimum-dimension, fully- silicided MOS driver and ESD protection design for optimized inter-finger coupling |
| CN1489210A (en) * | 2002-10-08 | 2004-04-14 | 台湾积体电路制造股份有限公司 | Static discharge protection circuit and relative metal oxide semiconductor transistor structure |
| CN1510749A (en) * | 2002-12-23 | 2004-07-07 | 矽统科技股份有限公司 | Electrostatic discharge protective circuit with self-trigger function |
| CN1542961A (en) * | 2003-04-29 | 2004-11-03 | 矽统科技股份有限公司 | Electrostatic discharge protective circuit having uniform conducting design |
| CN1577836A (en) * | 2003-07-28 | 2005-02-09 | 恩益禧电子股份有限公司 | Polydactylism type electrostatic discharging protection elements |
| US20050082621A1 (en) * | 2003-10-01 | 2005-04-21 | Jau-Wen Chen | Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1979844A (en) | 2007-06-13 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |