CN1489210A

CN1489210A - Static discharge protection circuit and relative metal oxide semiconductor transistor structure

Info

Publication number: CN1489210A
Application number: CNA021457255A
Authority: CN
Inventors: 柯明道; 徐国钧
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2002-10-08
Filing date: 2002-10-08
Publication date: 2004-04-14
Anticipated expiration: 2022-10-08
Also published as: CN1241262C

Abstract

Protection circuit of electro-static discharge (ESD) includes a component possessing polydactyly structure, multiple components for measuring transient state current and multiple feedback line. The component of polydactyly structure possesses finger grids, finger source electrode and at least one drain electrode, which is coupled to a joint mat. A bipolarity junction transistor (BJT) is parasitized under each finger grid. Each finger source electrode is emitter of one of BJT. Each transient state current measuring component is coupled between relevant finger source electrode and a power source line in order to detect transient state current passing through relevant finger grid. Each feedback line is coupled between base electrode of first BJT and emitter of second BJT in order to trigger the first BJT to discharge ESD current, if ESD event occurs.

Description

Electrostatic storage deflection (ESD) protection circuit and relevant metal-oxide semiconductor transistor arrangement

Technical field

(electrostatic discharge, ESD) protection circuit and its related elements refer to a kind of ESD protection circuit that high matrix triggers efficient that has especially to the present invention relates to a kind of static discharge.

Background technology

Basically, ESD is the transient energy dispose procedure of the big energy in a kind of external world by integrated circuit (integrated circuit), and whole discharge process approximately was 100 nanoseconds.In the so short time, hundreds of volts, or even thousands of volts ESD stress will be released.If the process of release is inappropriate, with the element infringement that is easy to cause in the IC, especially transistorized grid.Along with the reduction of thickness of grid oxide layer, grid is also just fragile more, and IC also needs special design more, prevent ESD the infringement that may cause.

Big energy discharges and will certainly cause high heat.For the effect of dispelling the heat considers that general ESD protective element all is to use large-size components.As shown in Figure 1, be the input port (port) of the existing ESD of a having safeguard function.MOS (NMOS) Mn of the MOS of eurymeric (PMOS) Mp and minus is as the ESD protective element, generally be the metal oxide semiconductor field effect that refers to structure (multi-finger layout) more answer transistor (metal-oxide-semiconductor field effect transistor, MOS).Fig. 2 A is an existing layout that refers to the MOS of structure more; Fig. 2 B is the profile of Fig. 2 A.The MOS that refers to structure (multi-finger) because of it has big component size, occupies less element area again simultaneously, so usually be used as the ESD protective element more.

Yet large-sized MOS element can meet with to refer to topology layout (uniformly) problem of being triggered uniformly more.Refer to the difference of several finger grids of structure MOS more, and have different triggering speed because of the position.And, often have only the several finger grids of part to be triggered.So, refer to that the ESD tolerance of structure MOS often can't be along with component size increases and increases more.In order to improve the ESD tolerance that refers to structure MOS, known technology includes gate coupled technology and matrix triggering technique at present, respectively as shown in Figure 3 and Figure 4 more.

Summary of the invention

In view of this, main purpose of the present invention provides a kind of can making and refers to the technology that structure MOS evenly triggers more, improves the ESD tolerance that refers to structure MOS more.

Another object of the present invention provides a corresponding component placement figure (device layout), can utilize chip area efficiently, makes a dynamical ESD protective element.

According to above-mentioned purpose, the present invention proposes static discharge (electrostaticdischarge, ESD) protection circuit that a kind of matrix triggers.This ESD protection circuit include have the element (device) that refers to structure more, a plurality of transient current detecting element and a plurality of feedback lines.The element that should refer to structure has a plurality of finger grids more, a plurality of finger source electrode and at least one fingers drains.This refers to that drain electrode is coupled to a bond pad (pad).Under each finger grid equal parasitism have a bipolarity junction transistor (bipolar junctiontransistor, BJT).Each finger source electrode is one of them a emitter-base bandgap grading of this BJT.Each transient current detecting element is coupled between the finger source electrode and a power line of a correspondence, in order to the flow through transient current (transient current) of a corresponding finger grid of detection.Each feedback line is coupled between the emitter-base bandgap grading of the base stage (base) of one the one BJT and one the 2nd BJT, when esd event takes place, in order to trigger a BJT, to discharge the ESD electric current.

The present invention proposes a kind of a kind of metal-oxide semiconductor transistor arrangement with dynamical electro-static discharge protective ability in addition, is located on the matrix (substrate) of one second conductivity type.This metal-oxide semiconductor transistor arrangement includes a protective ring (guard ring) of this second conductivity type, a plurality of finger structures, a plurality of well resistance and connection wire road (internal connection circuits).This protective ring is formed on this matrix, as the electric connection point of this matrix.This refers to that structure surrounded by this protective ring.Each refers to that structure includes a finger grid, a finger source electrode, refers to a drain electrode and a matrix electric current inlet point.This finger source electrode is constituted with one first doped region of one first conductivity type.This refers to that one second doped region that drains with this first conductivity type is constituted, and is coupled to a bond pad.This finger grid is located between this first doped region and this second doped region.This matrix electric current inlet point is to be constituted by one the 3rd doped region of this second conductivity type of this second doped region encirclement.Near this finger grid this first doped region, this matrix and this second doped region is the bipolarity junction transistor that constitutes a parasitism.One end of each well resistance be coupled to this finger source electrode one of them, the other end of each well resistance is coupled to a power line.The connection wire road in order to couple this finger source electrode one of them to this matrix electric current inlet point one of them.So, when esd event took place, the ESD electric current of the well resistance that the one first parasitic BJT that flows through links to each other with one can trigger one second parasitic BJT.

The invention has the advantages that, when finger grid when parasitic BJT is triggered by ESD stress below one of them, a large amount of electric currents corresponding transient current detecting element of flowing through, and then improve the emitter voltage of this BJT.After emitter voltage raises, can provide the base current of another BJT, trigger this another BJT, to add the ranks that discharge ESD stress.So under the chain reaction, all BJT can be triggered, and make this ESD protection circuit or metal-oxide semiconductor transistor arrangement reach best ESD protection effect.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Fig. 1 is the input port of the existing ESD of a having safeguard function;

Fig. 2 A is an existing layout that refers to the MOS of structure more;

Fig. 2 B is the profile of Fig. 2 A;

Fig. 3 shows an existing gate coupled technology;

Fig. 4 shows an existing matrix triggering technique;

Fig. 5 is the ESD protection circuit that matrix of the present invention triggers, the conceptual schematic view when implementing with NMOS;

Fig. 6 is the embodiment of NMOS during merely just as the ESD protective element that refers to structure more;

Fig. 7 is the embodiment of NMOS during as a driver that refers to structure more;

Fig. 8 is the embodiment of PMOS during merely just as the ESD protective element that refers to structure more;

Fig. 9 is the embodiment of PMOS during as a driver that refers to structure more;

Figure 10 is one according to the present invention, has 4 layouts (layout) that refer to many fingers structure NMOS of structures;

Figure 11 A and Figure 11 B are respectively the profile of XX ' line and YY ' line in Figure 10;

Figure 12 to Figure 15 is according to the present invention, can trigger four embodiment of a plurality of BJT simultaneously;

Figure 16 one can be used for the NMOS profile of many fingers structure of Figure 12;

Figure 17 is meant the layout of the many fingers structure NMOS that completely cuts off with empty grid structure between drain electrode and the matrix electric current inlet point;

Figure 18 is the profile of Figure 17, but its feedback line makes the triggering that its parasitic BJT can be in regular turn;

Figure 19 is the profile of Figure 17, but its feedback line makes the triggering that its parasitic BJT can be simultaneously;

Figure 20 to Figure 22 respectively with a plurality of diodes of an inductance, diode and series connection as the transient current detecting element among the present invention; And

Figure 23 is applied to the embodiment of stack NMOS for the present invention.

Embodiment

Fig. 5 is the ESD protection circuit that matrix of the present invention triggers, the conceptual schematic view when implementing with NMOS.ESD protection circuit 30 of the present invention has NMOS (by the finger structure of G1-Gn), a plurality of transient current detecting element 32 and a plurality of feedback lines 34 that refers to structure one more.Each refers to that one of structure refers to that drain electrode (finger drain) is coupled to a bond pad (pad) 36.Each transient current detecting element 32 all is coupled in one and refers between the finger source electrode (finger source) and a Vss power line of structure.Each refers to that finger drain electrode, matrix and finger source electrode under the structure can constitute the collector electrode (collector) of the BJT (T1-Tn) of a parasitism, base stage (base) and emitter-base bandgap grading (emitter) respectively.Each feedback line (feedback circuits) 34 is connected between the base stage of the emitter-base bandgap grading of a parasitic BJT and another parasitic BJT, as shown in Figure 5.

Cardinal principle of the present invention is as follows.If, refer to that the NMOS of structure is not triggered equably when esd event just takes place more, for example have only G1 to be triggered, the electric current of the transient current detecting element 32 that the G1 that then flows through in a large number links to each other with will promote the emitter voltage of T1.Arrive to a certain degree as long as the emitter voltage of T1 is high, by a feedback line 34 and matrix triggering technique, the base voltage of T2 also can raise, and then triggers the unlatching of T2, makes G2 add the ranks of conducting ESD electric current.By the connected mode among Fig. 5 as can be known, the triggering of G1 will cause the triggering of G2, and the triggering of G2 will cause the triggering of G3, by that analogy.At last, the triggering of Gn will cause the triggering of G1.What in other words, any one referred to that the triggering of structure will the chain reaction formula causes other to refer to the triggering of structure.Therefore, refer to that structure adds under the situation of conducting ESD electric current jointly, ESD protective element of the present invention and circuit design will have good ESD tolerance more.

As the NMOS of many fingers structure during merely just as the ESD protective element, its a plurality of finger source electrodes can directly be coupled to Vss, or are coupled to Vss by resistance, as shown in Figure 5 and Figure 6.In Fig. 6, transient current detecting element 32 is resistance R s1-Rsn.Each feedback line 34 is a simple connection wire (internal connection wire), connects the base stage of emitter-base bandgap grading and another BJT of a BJT.

As the NMOS of many fingers structure during just as the ESD protective element, in the time of also will be as the driver (driver) of output port (output port), according to the demand of drive current, can with the part or whole finger grids is coupled to prime driver (pre-driver).In Fig. 7, all finger grids all are coupled to prime driver 38, give full play to its driving force.

Except the NMOS of many fingers structure, present invention may also be embodied on the PMOS element that refers to structure more.Fig. 8 and Fig. 9 are that two PMOS with many fingers structure implement embodiments of the invention.Wherein, the finger grid among Fig. 8 all is coupled to the VDD power line, and in order to closeall finger grid when the normal power operation, this connected mode is applicable to the ESD protection circuit of input port.Finger grid among Fig. 9 is coupled to a prime driver 38, and its PMOS that refers to structure is as level driver (post driver) after more, and the ESD protective element that can be used as output port uses.

Figure 10 is one according to the present invention, has 4 layouts (layout) that refer to many fingers structure NMOS of structures.Figure 11 A and Figure 11 B are respectively the profile of XX ' line and YY ' line in Figure 10.Refer to that structure NMOS is located on the P mold base 40, its outermost is a P+ doped region 42 more, as the guard ring (guard ring) of many fingers structure NMOS, simultaneously also as the electric connection point of P mold base 40, is coupled to VSS.

There are 4 to refer to structure among Figure 10,11A and the 11B.Each refers to that structure has a finger grid 44, a finger source electrode, refers to a drain electrode and a matrix electric current inlet point.Each refers to that structure and another refer to that structure has the zone of common sparing.Finger source electrode is a N+ doped region 46.Refer to that drain electrode is a N+ doped region 48, be coupled to a bond pad 36.Matrix electric current inlet point is a P+ doped region 50, and each P+ doped region 50 is all surrounded by N+ doped region 48.Field oxide 52a is arranged as isolated between P+ doped region 50 and the N+ doped region 48.Among the figure, field oxide 52a be with the shallow isolating trough method (shallow trend isolation STI) is made, but also available selective oxidation method (local oxidation LOCOS) is made.

By among Figure 11 B as can be known, each refers to that the finger grid below parasitism of structure has a NPN BJT.N+ doped region 48, P mold base 40 and N+ doped region 46 constitute the collection utmost point, base stage and the emitter-base bandgap grading of BJT respectively.Base stage is connected to P+ doped region 42 by the exhibition resistance (spread resistor) of matrix 40.Base stage also is coupled to matrix electric current inlet point 50.When matrix electric current inlet point has electric current to enter, can improve the base voltage of BJT, and then trigger the BJT conducting, discharge the ESD electric current.

It is other that well resistance is located at N+ doped region 46, constituted with a N type well 54 respectively.One side of N type well 54 is connected to N+ doped region 46, and another side is connected to N+ doped region 56.And N+ doped region 56 is coupled to Vss.Can form field oxide 52b on the N type well 54, on the one hand isolated N+

doped region

56 and 46 is on the other hand in order to increase the resistance of well resistance.

Shown a kind of connection wire road (internal connection circuits) among Figure 11 B.The most left finger source electrode and the rightest finger source electrode are connected to the matrix electric current inlet point (the P+ doped region 50 on the left side) on the left side jointly, and two finger source electrodes of central authorities are connected to the matrix electric current inlet point (the P+ doped region 50 on the right) on the right jointly.

ESD protection circuit among Figure 11 A and the 11B, the chain reaction that is produced when esd event is so that the principle that all finger structures all trigger describing in detail among Fig. 5 before, no longer repeats at this.

Each feedback line not necessarily has only the base stage that connects a finger source electrode and a BJT, also can connect the base stage of a finger source electrode and a plurality of BJT, or even the base stage of all BJT.The electric current of a transient current detecting element 32 of just flowing through can trigger not only one BJT simultaneously.Figure 12 to Figure 15 is the embodiment of this kind scheme, and wherein, feedback line has connected the base stage of all BJT.In other words, when a BJT was triggered, the base voltage of other BJT also will be enhanced and trigger.Figure 16 one can be used for the NMOS profile of many fingers structure of Figure 12, and wherein Ji Sheng BJT can be triggered simultaneously.

Also can be between P+ doped region 50 and the N+ doped region 48 with an empty grid structure (dummy gate) as isolated.Figure 17 is the layout of many fingers structure NMOS of referring to completely cut off with empty grid structure 70 between drain electrode and the matrix electric current inlet point.Figure 18 is the profile of Figure 17 along YY ' line, but its feedback line makes its parasitic BJT triggering in proper order.Figure 19 for Figure 17 along the profile of YY ' line but its feedback line makes its parasitic BJT triggering simultaneously.

A large amount of electric currents when the function of transient current detecting element 32 is to detect esd event, and then the current potential of raising finger source electrode.Therefore, except resistance, available element has inductance (as shown in figure 20), diode (as shown in figure 21) or diode in series (as shown in figure 22).Especially inductance, that can design makes it when general normal power operation, and the variation of electric current can not produce enough voltage and trigger parasitic BJT.But when esd event, the big electric current in the short time changes the two ends that can make inductance and produces enough pressure reduction to trigger BJT.

For mixed pressure (mixed-voltage) IC, stacking-type (stacked) NMOS is used for bearing the discrepancy signal with the accurate position of high voltage, simultaneously as an output driver or an ESD protective element.Stack NMOS equally also can use notion of the present invention, utilizes a transient current detecting element to detect and flows through and pile up the ESD electric current that refers to structure, feeds back then and parasitizes and pile up the BJT that refers under the structure, as shown in figure 23.

The MOS of existing ESD protection circuit and many finger structures, the uneven problem of triggering is arranged because the position is different easily, and ESD protection circuit of the present invention utilizes detection, matrix triggering technique and the chain reaction of ESD electric current, all BJT are triggered together, so can have preferable ESD tolerance.

Though the present invention discloses as above with preferred embodiment, but be not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention, the equivalent structure transformation of making all is included in the claim of the present invention.

Claims

1. the electrostatic storage deflection (ESD) protection circuit that matrix triggers is characterized in that, includes:

Has an element that refers to structure more, have a plurality of finger grids, a plurality of finger source electrode and the drain electrode of at least one finger, this refers to that drain electrode is coupled to a bond pad, and equal parasitism has a bipolarity junction transistor under each finger grid, and each finger source electrode is one of them emitter-base bandgap gradings of these a plurality of BJT;

A plurality of transient current detecting elements, each transient current detecting element are coupled between the finger source electrode and a power line of a correspondence, in order to the flow through transient current of a corresponding finger grid of detection; And

A plurality of feedback lines, each feedback line are coupled between the emitter-base bandgap grading of the base stage of one the one BJT and one the 2nd BJT, when esd event takes place, in order to trigger a BJT, to discharge the ESD electric current.

2. ESD protection circuit as claimed in claim 1 is characterized in that, described element is a NMOS.

3. ESD protection circuit as claimed in claim 1 is characterized in that, described element is a PMOS.

4. ESD protection circuit as claimed in claim 1 is characterized in that, one of them is coupled to a power line a plurality of finger grids of described element.

5. ESD protection circuit as claimed in claim 4 is characterized in that, one of them is coupled to a power line by a resistance a plurality of finger grids of described element.

6. ESD protection circuit as claimed in claim 1 is characterized in that, one of them is coupled to a preceding stage drive circuit a plurality of finger grids of described element.

7. ESD protection circuit as claimed in claim 1 is characterized in that, described a plurality of transient current detecting elements are a plurality of resistance.

8. ESD protection circuit as claimed in claim 7 is characterized in that, described each this resistance is to be located at one second conductivity type matrix with a well resistance of first conductivity type to be constituted.

9. ESD protection circuit as claimed in claim 1 is characterized in that, described a plurality of transient current detecting elements are a plurality of inductance.

10. ESD protection circuit as claimed in claim 1 is characterized in that, described a plurality of transient current detecting elements comprise a diode.

11. ESD protection circuit as claimed in claim 1 is characterized in that, described a plurality of transient current detecting elements comprise a plurality of forward diode in series.

12. ESD protection circuit as claimed in claim 1 is characterized in that, described feedback line connects the base stage of a BJT and the emitter-base bandgap grading of the 2nd BJT.

13. ESD protection circuit as claimed in claim 1 is characterized in that, described feedback line connects the base stage of a BJT, the emitter-base bandgap grading of one the one BJT and the emitter-base bandgap grading of the 2nd BJT simultaneously.

14. ESD protection circuit as claimed in claim 1 is characterized in that, described element is a stacking-type MOS.

15. a kind of metal-oxide semiconductor transistor arrangement with electro-static discharge protective ability is located on the matrix of one second conductivity type, includes:

One protective ring of this second conductivity type is formed on this matrix, as the electric connection point of this matrix;

A plurality of finger structures, surrounded by this protective ring, each refers to that structure includes a finger grid, one finger source electrode, one refers to a drain electrode and a matrix electric current inlet point, this finger source electrode is that one first doped region with one first conductivity type is constituted, this refers to drain is that one second doped region with this first conductivity type is constituted, be coupled to a bond pad, this finger grid is located between this first doped region and this second doped region, this matrix electric current inlet point is to be constituted near this first doped region this finger grid by one the 3rd doped region of this second conductivity type of this second doped region encirclement, this matrix and this second doped region constitute the bipolarity junction transistor of a parasitism;

A plurality of well resistance, an end of each well resistance be coupled to these a plurality of finger source electrodes one of them, the other end of each well resistance is coupled to a power line; And

The connection wire road, in order to couple this finger source electrode one of them to these a plurality of matrix electric current inlet points one of them, with when esd event takes place, the electric current of the well resistance that the one first parasitic BJT that flows through links to each other with one can trigger one second parasitic BJT.

16. metal-oxide semiconductor transistor arrangement as claimed in claim 15, it is characterized in that, described each these a plurality of well resistance are the wellblocks by this second conductivity type, are located between this first doped region and one the 4th doped region, and the 4th doped region is coupled to this power line.

17. metal-oxide semiconductor transistor arrangement as claimed in claim 15 is characterized in that, is provided with a field oxide district between described first doped region and the 4th doped region in addition, to increase the resistance value of one of these a plurality of well resistance.

18. metal-oxide semiconductor transistor arrangement as claimed in claim 15 is characterized in that, is provided with a field oxide district between described second doped region and the 3rd doped region, in order to separate this second doped region and the 3rd doped region.

19. metal-oxide semiconductor transistor arrangement as claimed in claim 15 is characterized in that, is provided with a void between described second doped region and the 3rd doped region and puts the grid structure, in order to separate this second doped region and the 3rd doped region.