CN101521372B - Integrated circuit with electrostatic discharge protecting circuit - Google Patents
Integrated circuit with electrostatic discharge protecting circuit Download PDFInfo
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- CN101521372B CN101521372B CN2008100816673A CN200810081667A CN101521372B CN 101521372 B CN101521372 B CN 101521372B CN 2008100816673 A CN2008100816673 A CN 2008100816673A CN 200810081667 A CN200810081667 A CN 200810081667A CN 101521372 B CN101521372 B CN 101521372B
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Abstract
The invention discloses an integrated circuit with an electrostatic discharge protecting circuit. The integrated circuit comprises a first power source connecting pad, a second power source connectingpad, at least one circuit module and a power source clamping circuit. The circuit module comprises a signal connecting pad, an internal circuit and a first bipolar junction transistor. A first parasi tic resistance is arranged between the collector of the first bipolar junction transistor and the second power source connecting pad. The power source clamping circuit comprises at least one first metal-oxide-semiconductor transistor and at least one first parasitic bipolar junction transistor.
Description
Technical field
The present invention relates to a kind of integrated circuit, relate in particular to a kind of integrated circuit, and this integrated circuit has been used bipolar junction transistor and substrate triggering (substrate trigger) technology strengthens/improve the electrostatic protection ability with ESD protection circuit.
Background technology
Along with scientific and technological progress, integrated circuit processing technique is constantly development thereupon also.Known to the technical staff of integrated circuit fields, but various electronic circuit aggregations/form on the chip, and in order to make chip can receive extraneous voltage source (for example grid bias power supply), and can with extraneous other circuit/chip swap data, can be provided with the connection pad (pad) of conduction on the chip.For example, in order to transmit bias voltage, can be provided with power supply connection pad (power pad) on the chip, also be vdd terminal and VSS end.In addition, also being provided with signal bonding pad (signal pad) on chip, also is I/o pad (I/O pad), in order to receiving inputted signal and/or send output signal.
The connection pad of these conductions can make chip be able to be connected with extraneous other circuit/chip.Yet, when chip in processes such as encapsulation, test, transportation, processing, these connection pads also are easy to because contact with the static power supply in the external world, and the improper electric power of static is conducted to chip internal, and and then cause the damage of chip internal circuit, this phenomenon is so-called static discharge (ESD, Electro-Static Discharge).Therefore, be used for protecting integrated circuit to avoid the ESD protection circuit of damage of electrostatic discharge (ESD protection circuit) and also therefore become more important along with improving of integrated circuit technology.
Usually between each connection pad of chip, can be provided with ESD protection circuit.The basic function of this ESD protection circuit is, when between two connection pads of chip during false touch static power supply, ESD protection circuit can be between two connection pads low-impedance current path of conducting, make the electric current of static power supply discharge can be preferentially flow through and can not flow into other internal circuit of chip from this current path; So, just can protect other internal circuit in the chip not to be subjected to electrostatic discharge effect.
And comprise PS (positive to VSS) pattern, NS (negative to VSS) pattern, PD (positiveto VDD) pattern and ND (negative to VDD) pattern in its test mode of integrated circuit for the static discharge ability to bear, and the test between the power supply, as DS (VDD to VSS) pattern.Lifting the PS pattern is example, and so-called PS pattern promptly refers to, with VSS connection pad ground connection, the connection pad to be measured that positive ESD voltage comes across integrated circuit (IC) chip is with to the discharge of VSS connection pad, this moment VDD connection pad and all the other connection pads suspension joint (floating) all.And the ND pattern is, and with VDD connection pad ground connection, the connection pad to be measured that negative ESD voltage appears at integrated circuit (IC) chip is with to the discharge of VDD connection pad, and this moment VSS connection pad and all the other connection pads suspension joint all.
See also Fig. 1, Figure 1 shows that the schematic diagram of the integrated circuit 100 that has ESD protection circuit in the prior art.As shown in Figure 1, integrated circuit 100 comprises the first power supply connection pad (power pad) 101, second source connection pad 102, signal bonding pad (signal pad) 103, impedance component 105, internal circuit (internal circuit) 110, two diodes (diode) 121,122 and power supply strangulation (power clamp) circuit 130.Wherein power supply clamped circuit 130 comprises N type metal oxide semiconductor (metal oxide semiconductor, MOS) the P-type mos transistor 134 of a transistor 132 and grid power supply (gate-powered) of a grounded-grid (gate-grounded).In Fig. 1, the first power supply connection pad 101 is a vdd terminal, and second source connection pad 102 is the VSS end.In known technology, power supply clamped circuit 130 also can only use the N type metal oxide semiconductor transistor 132 of grounded-grid or grid to connect the P-type mos transistor 134 both one of them of electricity, or uses the two to be implemented simultaneously.
In Fig. 1, diode 121 is in order to forming esd protection circuit between the signal bonding pad 103 and the first power supply connection pad 101, and diode 122 is used for being formed on the esd protection circuit between signal bonding pad 103 and the second source connection pad 102.In addition, 130 of aforesaid power supply clamped circuits are as the esd protection circuit between the first power supply connection pad 101 (VDD) and the second source connection pad 102 (VSS).
Yet; because the characteristic of the conducting inconsistent (turn-onuniformity) of N type metal oxide semiconductor transistor 132 and P-type mos transistor 134 these elements itself; cause when if the size of N type metal oxide semiconductor transistor 132 in the power supply clamped circuit 130 or P-type mos transistor 134 increases; therefore its electrostatic protection ability can't consistently thereupon strengthen, and needs a brand-new electrostatic discharge (ESD) protection mechanism badly and reaches when circuit size increases and can strengthen its electrostatic discharge (ESD) protection ability in the lump.
Summary of the invention
The present invention discloses a kind of have static discharge (Electrostatic Discharge, ESD) integrated circuit of protective circuit.This integrated circuit comprises the first power supply connection pad, second source connection pad, at least one circuit module, power supply clamped circuit.Wherein comprise signal bonding pad, internal circuit and first bipolar junction transistor in this circuit module, wherein this internal circuit is coupled between this first power supply connection pad and this second source connection pad.And this its base stage of first bipolar junction transistor is coupled to this first power supply connection pad, and its emitter-base bandgap grading is coupled to this signal bonding pad, in addition, has one first dead resistance between its collection utmost point of this first bipolar junction transistor and this second source connection pad.This power supply clamped circuit is coupled between this first power supply connection pad and this second source connection pad, and this power supply clamped circuit comprises at least one first metal oxide semiconductor transistor, and at least one first parasitic bipolar junction transistor.Wherein the control end of this first metal oxide semiconductor transistor is coupled to this second source connection pad, and first link is coupled to this first power supply connection pad, and second link is coupled to this second source connection pad.This first parasitic bipolar junction transistor, its collection utmost point is coupled to this first link of this first metal oxide semiconductor transistor, and emitter-base bandgap grading is coupled to this second link of this first metal oxide semiconductor transistor and this collection utmost point and this first dead resistance that base stage is coupled to this first bipolar junction transistor.
According to integrated circuit of the present invention, wherein this power supply clamped circuit also comprises second metal oxide semiconductor transistor and second parasitic bipolar junction transistor; The control end of this second metal oxide semiconductor transistor is coupled to this first power supply connection pad, and first link is coupled to this second source connection pad, and second link is coupled to this first power supply connection pad; This circuit module also comprises: second bipolar junction transistor, its base stage are coupled to this second source connection pad, and emitter-base bandgap grading is coupled to this signal bonding pad, wherein, have one second dead resistance between the collection utmost point of this second bipolar junction transistor and this first power supply connection pad; And the collection utmost point of this second parasitic bipolar junction transistor is coupled to this first link of this second metal oxide semiconductor transistor, emitter-base bandgap grading is coupled to this second link of this second metal oxide semiconductor transistor, and base stage is coupled to this collection utmost point and this second dead resistance of this second bipolar junction transistor.
According to integrated circuit of the present invention, it comprises a plurality of circuit modules, the collection of first bipolar junction transistor in each circuit module extremely all is coupled to this base stage of this first dead resistance and this first parasitic bipolar junction transistor, and the collection of second bipolar junction transistor in each circuit module extremely all is coupled to this base stage of this second dead resistance and this second parasitic bipolar junction transistor.
According to integrated circuit of the present invention, it also comprises impedance component, is coupled between this signal bonding pad and this internal circuit.
According to integrated circuit of the present invention, wherein this first metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor.
According to integrated circuit of the present invention, wherein this first metal oxide semiconductor transistor is the P-type mos transistor.
According to integrated circuit of the present invention, it comprises a plurality of circuit modules, and the collection of first bipolar junction transistor in each circuit module extremely all is coupled to this base stage of this first dead resistance and this first parasitic bipolar junction transistor.
The present invention is applied in base stage trigger mechanism (substrate-trigger scheme) among the ESD protection circuit technology, makes the disclosed integrated circuit with ESD protection circuit can reduce because large-sized metal oxide semiconductor transistor (M than prior art
nOr M
p) the inconsistent characteristic of conducting of element, and then promoted the electrostatic discharge (ESD) protection ability on the integrated circuit (IC) chip.In addition, the present invention has also disclosed an ESD protection circuit.This ESD protection circuit can correspond to a plurality of circuit modules (comprising a plurality of internal circuits and signal bonding pad in it) respectively; and do not need additionally to increase the area of ESD protection circuit, thereby reduced chip expend the layout area of ESD protection circuit with and production cost.
Description of drawings
Figure 1 shows that the schematic diagram of the integrated circuit that comprises ESD protection circuit in the prior art.
Fig. 2 is for having the schematic diagram of the integrated circuit of ESD protection circuit in the first embodiment of the invention.
Fig. 3 is for having the schematic diagram of the integrated circuit of ESD protection circuit in the second embodiment of the invention.
Fig. 4 is for having the schematic diagram of the integrated circuit of ESD protection circuit in the third embodiment of the invention.
Fig. 5 is for having the schematic diagram of the integrated circuit of ESD protection circuit in the fourth embodiment of the invention.
Embodiment
See also Fig. 2, Fig. 2 is the schematic diagram according to the integrated circuit 200 that has ESD protection circuit in the first embodiment of the invention.Integrated circuit 200 includes, but is not limited to the first power supply connection pad 201, second source connection pad 202, at least one circuit module 210 and power supply clamped circuit 220, in addition, in the integrated circuit 200, power supply clamped circuit 220 also has one first parasitic bipolar junction transistor 285.Note that in addition in the present embodiment, the first power supply connection pad 201 is a vdd terminal, and second source connection pad 202 is the VSS end.
As shown in Figure 2, in circuit module 210, comprise signal bonding pad 230, internal circuit 240 and first bipolar junction transistor 250.In addition, if design needs, also can comprise an impedance component 270 (as shown in Figure 2) in the circuit module 210.For narrate convenient for the purpose of, among ensuing narration, signal bonding pad 230 be an input signal connection pad (input pad, IP).Internal circuit 240 in circuit module 210 is coupled between the first power supply connection pad 201 and the second source connection pad 202.Place first bipolar junction transistor 250 in the circuit module 210, its base stage (collector) is coupled to the first power supply connection pad 201 (vdd terminal), emitter-base bandgap grading (emitter) is coupled to signal bonding pad 230, and has one first dead resistance (parasitical resistance) 260 between the collection utmost point of first bipolar junction transistor 250 and the second source connection pad 202 (VSS end).In the present embodiment, first bipolar junction transistor 250 is a P type bipolar junction transistor, yet in other embodiments, first bipolar junction transistor in the circuit module 210 also can be N type bipolar junction transistor, or be provided with N type bipolar junction transistor and P type bipolar junction transistor simultaneously, and will in follow-up embodiment, disclose in detail about the design variation of the bipolar junction transistor in the circuit module 210.
As shown in the figure, power supply clamped circuit 220 is coupled between the first power supply connection pad 201 (vdd terminal) and the second source connection pad 202 (VSS end), in the present embodiment, power supply clamped circuit 220 is implemented by first metal oxide semiconductor transistor 280, yet, the number of metal oxide semiconductor transistor is not a restrictive condition of the present invention in the power supply clamped circuit 220, that is to say, in power supply clamped circuit 220, also can use the metal oxide semiconductor transistor of two dissimilar (also being N type and P type) to be implemented.
In first embodiment, the control end NC of first metal oxide semiconductor transistor 280 in the power supply clamped circuit 220 is coupled to second source connection pad 202 (VSS end), the first link NA is coupled to the first power supply connection pad 201 (vdd terminal), and the second link NB then is coupled to second source connection pad 202 (VSS end).Because first metal oxide semiconductor transistor 280 is a N type metal oxide semiconductor transistor, so aforesaid control end NC is a grid, the first end NA is drain electrode (drain), and the second end NB then is source electrode (source).In addition, as shown in Figure 2, the collection utmost point (collector) of first parasitic bipolar junction transistor 285 is coupled to the first link NA of first metal oxide semiconductor transistor 280, the emitter-base bandgap grading of first parasitic bipolar junction transistor 285 (emitter) then is coupled to the second link NB of first metal oxide semiconductor transistor 280, then is the collection utmost point and first dead resistance 260 that is coupled to first bipolar junction transistor 250 as for the base stage (base) of this first parasitic bipolar junction transistor 285.Known to those skilled in the art, also comprise first parasitic bipolar junction transistor 285 and first dead resistance 260 in the power supply clamped circuit 220, and first parasitic bipolar junction transistor 285 and first dead resistance 260 are owing to first metal oxide semiconductor transistor, 280 semiconductor structure characteristics own produce.
Yet to note that, only to show that in Fig. 2 a circuit module 210 is in order narrating conveniently, is not one of restrictive condition of the present invention.In other embodiments of the invention; this integrated circuit 200 with ESD protection circuit also can comprise a plurality of circuit modules; in addition; in the present embodiment; the first power supply connection pad 201 is a vdd terminal; and second source connection pad 202 is the VSS end; yet; the number of circuit module 210 and the pairing power end of the first power supply connection pad and the pairing power end of second source connection pad are not one of restrictive condition of the present invention; that is to say; in other embodiment of the present invention, also can have a plurality of circuit modules and correspond to first power supply connection pad of VSS end and the second source connection pad that corresponds to vdd terminal; aforesaid design variation spirit all according to the invention, and drop among the category of the present invention.
Below to be implemented on integrated circuit shown in Figure 2 200 with the PS pattern of electrostatic protection test be example, the running of electrostatic discharge protective circuit of the present invention is described.In the PS pattern, positive ESD voltage appears at signal bonding pad 230 with to second source connection pad 202 (VSS end) discharge, as mentioned above, this moment second source connection pad 202 (VSS end) ground connection (grounded).
As shown in Figure 2, positive ESD voltage will cause electric current I
EsdVia the first power supply connection pad 201 (vdd terminal) and turn-on power clamped circuit 220 (also being first metal oxide semiconductor transistor 280), work as electric current I by signal bonding pad 230 in addition
BiasingWhen flowing through the collection utmost point of first bipolar junction transistor 250 and first dead resistance 260, can trigger first parasitic bipolar junction transistor 285 and make its conducting, so the current path of second esd discharge is provided.
As previously mentioned, than prior art, the conducting path of ESD electric current is by single-pathway (I originally
Esd), additionally increased by first bipolar junction transistors 250 in the circuit module 210 and another paths (I of being produced by the substrate trigger mechanism
Biasing).By having used bipolar junction transistor element 250 to replace traditional diode element; and trigger mechanism at the bottom of the as fired basis; the present invention has successfully promoted under the identical chips area in the electrostatic discharge (ESD) protection ability of PS pattern, and has improved originally because the inconsistent problem that is produced in large-sized integrated circuit of conducting in it of the metal-oxide semiconductor transistor component in the power supply clamped circuit.
Therefore; when needing to strengthen its static discharge holding capacity under the PS pattern in the design of integrated circuit; adopt the circuit framework disclosed in above-mentioned first embodiment of the present invention under identical layout area, (layout area) to allow more static discharge current, so can promote the electrostatic discharge (ESD) protection ability of integrated circuit under equal area effectively.
See also Fig. 3, Figure 3 shows that the schematic diagram of the integrated circuit 300 that has ESD protection circuit in the second embodiment of the invention.Integrated circuit 300 includes, but is not limited to the first power supply connection pad 301, second source connection pad 302, circuit module 310 and power supply clamped circuit 320, in addition, in integrated circuit 300 power supply clamped circuits 320, also has one first parasitic bipolar junction transistor 385.Note that in the present embodiment, the first power supply connection pad 301 is the VSS end, and second source connection pad 302 is a vdd terminal.
As shown in Figure 3, in circuit module 310, comprise signal bonding pad (for example signal input connection pad) 330, internal circuit 340, first bipolar junction transistor 350 and impedance component 370.The internal circuit 340 that is positioned at circuit module 310 is coupled between first power supply connection pad 301 (VSS end) and the second source connection pad 302 (vdd terminal), in addition, the collection utmost point (collector) of first bipolar junction transistor 350 is coupled to the first power supply connection pad 301 (VSS end), the emitter-base bandgap grading of first bipolar junction transistor 350 (emitter) then is coupled to signal bonding pad 330, and has one first dead resistance (parasitical resistance) 360 between the collection utmost point of first bipolar junction transistor 350 and the second source connection pad 302 (vdd terminal).
In the present embodiment, this moment, circuit module 310 interior employed first bipolar junction transistors 350 were N type bipolar junction transistor, yet in other embodiments, circuit module 310 also can comprise N type bipolar junction transistor and P type bipolar junction transistor simultaneously, and these design variation about bipolar junction transistor will disclose in follow-up embodiment in detail.
As shown in Figure 3, power supply clamped circuit 320 is coupled between first power supply connection pad 301 (VSS end) and the second source connection pad 302 (vdd terminal).In the present embodiment, comprise one first metal oxide semiconductor transistor 380 in the power supply clamped circuit 320.Yet, if design needs, in power supply clamped circuit 320, also can use the metal oxide semiconductor transistor of two dissimilar (also being N type and P type) to be implemented, that is to say, in Fig. 3, show only for convenience of description usefulness of a metal oxide semiconductor transistor 380.These relevant narrations will disclose in follow-up specification in detail.
Please continue with reference to Fig. 3, in the present embodiment, the control end NC of first metal oxide semiconductor transistor 380 is coupled to second source connection pad 302 (vdd terminal), the first link NA is coupled to the first power supply connection pad 301 (VSS end), the second link NB then is coupled to second source connection pad 302 (vdd terminal), in the present embodiment, first metal oxide semiconductor transistor 380 is implemented by the P-type mos transistor, therefore, above-mentioned control end NC is a grid, the first end NA is drain electrode (drain), and the second end NB then is source electrode (source).In addition, the base stage of first parasitic bipolar junction transistor 385 is coupled to the first link NA of first metal oxide semiconductor transistor 380, and the emitter-base bandgap grading of first parasitic bipolar junction transistor 385 is coupled to the second link NB of first metal oxide semiconductor transistor 380, then is the collection utmost point and first dead resistance 360 that is coupled to first bipolar junction transistor 350 in the circuit module 310 as for the collection utmost point of this first parasitic bipolar junction transistor 385.
Note that here first parasitic bipolar junction transistor 385 and first dead resistance 360 are owing to first metal oxide semiconductor transistor, 380 semiconductor structure characteristics own cause.
Next, being implemented on integrated circuit shown in Figure 3 300 with the ND pattern of electrostatic protection test is example, and the running of electrostatic discharge protective circuit of the present invention is described.In the ND pattern, negative ESD voltage appears in the signal bonding pad 330, so that second source connection pad 302 (vdd terminal) is discharged, please note, in the ND pattern, this moment second source connection pad 302 (vdd terminal) ground connection (grounded), and the first power supply connection pad 301 (VSS end) and all the other connection pads suspension joint (floating) all.
When integrated circuit 300 suffers the static discharge current of ND pattern, negative ESD voltage will cause electric current I
EsdBy signal bonding pad 330 flow through first power supply connection pad 301 (VSS end) and turn-on power clamped circuit 320, and work as electric current I
BiasingFlow through the collection utmost point and first dead resistance 360 of first bipolar junction transistor 350, can trigger first parasitic bipolar junction transistor 385 and make its conducting, the current path that an esd discharge is only arranged in the prior art, the second embodiment of the present invention can also provide the current path of second esd discharge under the ND pattern.
As previously mentioned, than prior art, the conducting path of ESD electric current is by script single-pathway (I
Esd), additionally increased by first bipolar junction transistor 350 and another paths (I of being produced by the base stage trigger mechanism
Biasing).By having used bipolar junction transistor element 350 to replace trigger mechanism at the bottom of traditional diode element and the as fired basis; the present invention has successfully promoted when the ND pattern takes place; electrostatic discharge (ESD) protection ability under the identical chips area, and improved originally because the metal-oxide semiconductor transistor component in the power supply clamped circuit is inconsistent so that the problem that produces when the integrated circuit size increases owing to the conducting in it.
Therefore; when needing to strengthen its static discharge holding capacity under the ND pattern in the design of integrated circuit; adopt the circuit framework disclosed in the second embodiment of the present invention under identical layout area, (layout area) to allow more static discharge current, so can promote the electrostatic discharge (ESD) protection ability of integrated circuit under equal area effectively.
Yet to note that, only to show that in Fig. 3 a circuit module 310 is in order narrating conveniently, is not one of restrictive condition of the present invention.In other embodiments, this integrated circuit with ESD protection circuit also can comprise a plurality of circuit modules 310.Above-mentioned design variation spirit all according to the invention, and drop among the category of the present invention.These relevant narrations will describe in detail in the narration of back.
See also Fig. 4, Figure 4 shows that schematic diagram according to the integrated circuit 400 that has ESD protection circuit in the third embodiment of the invention.Strengthened the protective capability of integrated circuit 400 static discharge under PS pattern and ND pattern in the present embodiment simultaneously.Integrated circuit 400 comprises the first power supply connection pad 401 (vdd terminal), second source connection pad 402 (VSS end), circuit module 410 and power supply clamped circuit 420.
As shown in Figure 4, in circuit module 410, comprise signal bonding pad 430, internal circuit 440, first bipolar junction transistor 450 and second bipolar junction transistor 455.In addition, if design needs, in circuit module 410, also can comprise impedance component 470.Wherein be positioned at the internal circuit 440 of circuit module 410, be coupled between the first power supply connection pad 401 and the second source connection pad 402.
And because the relation of coupling of the emitter-base bandgap grading of first bipolar junction transistor 450, base stage and the collection utmost point is identical with the relation of coupling of first bipolar junction transistor 250 of first embodiment of the invention, so please refer to aforesaid disclosure, this just just not given unnecessary details for the sake of simplicity.Similarly, the relation of coupling of second bipolar junction transistor, 455 its emitter-base bandgap gradings, base stage and the collection utmost point is identical with the relation of coupling of first bipolar junction transistor 350 of second embodiment of the invention, please refer to the disclosure of Fig. 3, does not here give unnecessary details one by one with regard to omission.
In addition, in power supply clamped circuit 420, comprise first metal oxide semiconductor transistor 480 and second metal oxide semiconductor transistor 490.The control end of first metal oxide semiconductor transistor 480, first link and second link are respectively NC_1, NA_1, NB_1, and are coupled to second source connection pad 402, the first power supply connection pad 401, second source connection pad 402 separately.Control end, first link and second link as for second metal oxide semiconductor transistor 490 in the power supply clamped circuit 420 are respectively NC_2, NA_2, NB_2, and are coupled to the first power supply connection pad 401, second source connection pad 402, the first power supply connection pad 401 separately.Wherein first metal oxide semiconductor transistor 480 is a N type metal oxide semiconductor transistor, and second metal oxide semiconductor transistor 490 then is the P-type mos transistor.
Wherein since the coupling mode of first metal oxide semiconductor transistor 480 of power supply clamped circuit 420 and first parasitic bipolar junction transistor 485 that first metal oxide semiconductor transistor 480 is constituted and first dead resistance 460 with described in previous first embodiment.Because before having described the coupling mode of first metal oxide semiconductor transistor 480, first parasitic bipolar junction transistor 485 and first dead resistance 460 in detail (please refer to, each element 280,285 and 260 coupling mode in the power supply clamped circuit 220 among Fig. 2), so further instruction just repeats no more in this omission.
In addition, the coupling mode of second parasitic bipolar junction transistor 495 that constituted of second metal oxide semiconductor transistor 490 of power supply clamped circuit 420 and second metal oxide semiconductor transistor 490 and second dead resistance 465 is with described in previous second embodiment.Because before having described the coupling mode of second metal oxide semiconductor transistor 490, second parasitic bipolar junction transistor 495 and second dead resistance 465 in detail (please refer to, each element 380,385 and 360 coupling mode in the power supply clamped circuit 320 among Fig. 3), so further instruction just repeats no more in this omission.
In the present embodiment, first embodiment is described as the front, has one first dead resistance 460 between the collection utmost point of first bipolar junction transistor 450 and the second source connection pad 402 (VSS end), this first dead resistance 460 constitutes owing to first metal oxide semiconductor transistor, 480 semiconductor structure characteristics own, similarly, because the characteristic of first metal oxide semiconductor transistor 480 itself also comprises first parasitic bipolar junction transistor 485 in the power supply clamped circuit 420 of integrated circuit 400.
In addition, described in second embodiment of front, have second dead resistance 465 between the collection utmost point of second bipolar junction transistor 455 and the first power supply connection pad 401 (vdd terminal), this second dead resistance 465 constitutes owing to second metal oxide semiconductor transistor, 490 semiconductor structure characteristics own; Similarly, because the characteristic of second metal oxide semiconductor transistor 490 itself also comprises second parasitic bipolar junction transistor 495 in integrated circuit 400.As shown in the figure, the collection utmost point of second parasitic bipolar junction transistor 495 is coupled to the first link NA_2 of second metal oxide semiconductor transistor 490, emitter-base bandgap grading is coupled to the second link NB_2 of second metal oxide semiconductor transistor 490, and base stage is coupled to the collection utmost point and second dead resistance 465 of second bipolar junction transistor 455 of circuit module 410.
In present embodiment (as shown in Figure 4), when the PS of static discharge pattern takes place, in the integrated circuit in the static discharge pattern reactiveness of circuit and wherein the coupling mode of each element can regard as identical with first embodiment disclosed in Fig. 2; And when the ND of static discharge pattern takes place, the reactiveness of circuit the and wherein coupling mode of each element is identical with second embodiment disclosed in Fig. 3 in the static discharge pattern in the integrated circuit.Please refer to aforesaid disclosure.
When the PS of static discharge pattern occurs in the integrated circuit 400, positive ESD voltage appears at signal bonding pad 430, with to second source connection pad 402 (VSS end) discharge, with aforesaid disclosure, VSS connection pad ground connection (grounded) the first power supply connection pad 401 (vdd terminal) this moment suspension joint then.At this moment, positive ESD voltage will cause electric current from signal bonding pad 430 first power supply connection pad 401 (vdd terminal) and the turn-on power clamped circuit 420 of flowing through, and when electric current flow through the collection utmost point and first dead resistance 460 of first bipolar junction transistor 450, this bypass electric current can trigger first parasitic bipolar junction transistor 485 and make its conducting, and therefore the second discharge path of ESD electric current is provided under the PS pattern.
In addition, when the ND of static discharge pattern occurs in the integrated circuit 400, negative ESD voltage appears at signal bonding pad 430, so that the first power supply connection pad 401 (vdd terminal) is discharged, in the ND pattern, this moment VDD connection pad 401 ground connection (grounded), and second source connection pad (VSS end) and all the other connection pads suspension joint (floating) all.As shown in Figure 4, when integrated circuit 400 suffers the static discharge current of ND pattern, negative ESD voltage will cause electric current from signal bonding pad 430 via second source connection pad 402 (VSS end) and turn-on power clamped circuit 420, and when electric current flow through the collection utmost point and second dead resistance 465 of second bipolar junction transistor 455, second parasitic bipolar junction transistor 495 that can trigger in the power supply clamped circuit 420 makes its conducting, the current path that an esd discharge is only arranged in the prior art, the third embodiment of the present invention provides the ESD electric current two discharge paths under the ND pattern.
See also Fig. 5, Fig. 5 is for having the schematic diagram of the integrated circuit 500 of ESD protection circuit in the fourth embodiment of the invention.As shown in Figure 5, integrated circuit 500 comprises the first power supply connection pad 501 (vdd terminal), second source connection pad (VSS end), a plurality of circuit module 510 and a power supply clamped circuit 520.Wherein, in each circuit module 510, has identical circuit framework (as shown in Figure 5), comprise in the circuit module 510 that (for example, each circuit module 510 has separately signal input connection pad IP1～IPn), internal circuit 540, first bipolar junction transistor 550 and second bipolar junction transistor 555 to signal bonding pad 530.In addition, also comprise impedance component 470 in circuit module 510, but if can reach same effect, this can omit the setting of impedance component 470 in other embodiments of the invention, this relevant design variation also drops in the category of the present invention.In the present embodiment, comprise first metal oxide semiconductor transistor 580 and second metal oxide semiconductor transistor 590 in the power supply clamped circuit 520, wherein first metal oxide semiconductor transistor 580 is a N type metal oxide semiconductor transistor, and second metal oxide semiconductor transistor 590 is the P-type mos transistor.
Because the characteristic of first metal oxide semiconductor transistor, 580 semiconductor structures own is so the power supply clamped circuit 520 in the integrated circuit 500 also has one first parasitic bipolar junction transistor 585 and one first dead resistance 560; Similarly, for second metal oxide semiconductor transistor 590, the power supply clamped circuit 520 of integrated circuit 500 also has one second parasitic bipolar junction transistor 595 and one second dead resistance 565.Because circuit framework shown in Figure 5 is derived from circuit framework shown in Figure 4, and those skilled in the art should understand the function and the running of each element in the circuit framework shown in Figure 5 easily according to aforesaid technology disclosure, do not give unnecessary details at this in addition so describe in detail just.
Than embodiment shown in Figure 4, in the present embodiment, a plurality of circuit modules 510 can be shared a power supply clamped circuit 520 and the first power supply connection pad 501 (vdd terminal) and second source connection pad 502 (VSS end) simultaneously, therefore save the layout area of chip widely, more saved production cost.Because four patterns at static discharge; it also is the PS pattern; the NS pattern; in PD pattern and the ND pattern; PS pattern and ND pattern are the fragile ring of integrated circuit esd protection ability in the chip; and by among the previous embodiment that discloses of the present invention as can be known; the present invention has used bipolar junction transistor 550 and 555 and has replaced traditional diode element; and used the base stage triggering technique; therefore can be by metal oxide semiconductor transistor 580; 590 dead resistances 560 own; 565 and parasitic bipolar junction transistor 585; 595 characteristic allows the esd protection ability of chip under PS pattern and ND pattern be improved.In addition, electrostatic discharge (ESD) protection notion provided by the present invention is only used a power supply clamped circuit, but can correspond to a plurality of circuit modules 510 with different internal circuits 540.When the not bigger electrostatic discharge (ESD) protection abilities of 510 of each circuit modules are provided, have also saved chip and expended layout area, and then saved cost and promote the chip service efficiency at ESD protection circuit.
In addition; when integrated circuit only need strengthen the electrostatic discharge (ESD) protection ability of single PS pattern or ND pattern based on itself requirement, also can use the disclosed technology of the present invention and use the power supply clamped circuit that only has one first metal oxide semiconductor transistor to be realized.In other words, when needing to strengthen the PS pattern, in the power supply clamped circuit, adopt N type metal oxide semiconductor transistor to be used as first metal-oxide semiconductor transistor component.In addition, only need strengthen chip to the ND pattern under during ESD electrostatic discharge (ESD) protection ability, then in the power supply clamped circuit, adopt the P-type mos transistor unit to be used as first metal oxide semiconductor transistor.
In addition, whether the setting of circuit module middle impedance element (for example the impedance component shown in Fig. 1～5 105,270,370,470,570) is not one of restrictive condition of the present invention, and Fig. 1～Fig. 5 shown in aforementioned is circuit diagram and does not represent semi-conductive practical structures, and any semiconductor structure that reaches effect same all belongs to category of the present invention.In other words; any electric framework if the technology that adopts the front to narrate utilize the parasitic antenna of metal-oxide semiconductor transistor component to provide the esd discharge path to strengthen/improve ESD electrostatic protection ability and improve that metal-oxide semiconductor transistor component all belongs to category of the present invention because of the inconsistent problem that takes place of conducting own in the power supply clamped circuit.
The above only is the preferred embodiments of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
The primary clustering symbol description
100,200,300,400,500 integrated circuits
101,201,301,401,501 first power supply connection pads
102,202,302,402,502 second source connection pads
103,230,330,430,530 signal bonding pad
105,270,370,470,570 impedors
110,240,340,440,540 internal circuits
210,310,410,510 circuit modules
121,122 diodes
130,220,320,420,520 power supply clamped circuits
132,134,280,380,480,490,580,590 metal oxide semiconductor transistors
250,350,450,455,550,555 bipolar junction transistors
260,360,460,465,560,565 dead resistances
285,385,485,495,585,595 parasitic bipolar junction transistors
Claims (7)
1. integrated circuit with ESD protection circuit, it comprises:
The first power supply connection pad;
The second source connection pad;
At least one circuit module comprises:
Signal bonding pad;
Internal circuit is coupled between described first power supply connection pad and the described second source connection pad; And
First bipolar junction transistor, its base stage are coupled to the described first power supply connection pad, and emitter-base bandgap grading is coupled to described signal bonding pad, wherein, have one first dead resistance between the collection utmost point of described first bipolar junction transistor and the described second source connection pad;
The power supply clamped circuit is coupled between described first power supply connection pad and the described second source connection pad, and described power supply clamped circuit comprises:
At least one first metal oxide semiconductor transistor, the control end of described first metal oxide semiconductor transistor is coupled to described second source connection pad, first link is coupled to the described first power supply connection pad, and second link is coupled to described second source connection pad; And
At least one first parasitic bipolar junction transistor, its collection utmost point is coupled to described first link of described first metal oxide semiconductor transistor, emitter-base bandgap grading is coupled to described second link of described first metal oxide semiconductor transistor, and base stage is coupled to the described collection utmost point and described first dead resistance of described first bipolar junction transistor.
2. integrated circuit according to claim 1, wherein, described power supply clamped circuit also comprises second metal oxide semiconductor transistor and second parasitic bipolar junction transistor; The control end of described second metal oxide semiconductor transistor is coupled to the described first power supply connection pad, first link is coupled to described second source connection pad, and second link be coupled to the described first power supply connection pad, wherein, the control end of described second metal oxide semiconductor transistor is a grid, first link is drain electrode, and second link is a source electrode; Described circuit module also comprises: second bipolar junction transistor, its base stage is coupled to described second source connection pad, emitter-base bandgap grading is coupled to described signal bonding pad, wherein, has one second dead resistance between the collection utmost point of described second bipolar junction transistor and the described first power supply connection pad; And the collection utmost point of described second parasitic bipolar junction transistor is coupled to described first link of described second metal oxide semiconductor transistor, emitter-base bandgap grading is coupled to described second link of described second metal oxide semiconductor transistor, and base stage is coupled to the described collection utmost point and described second dead resistance of described second bipolar junction transistor.
3. integrated circuit according to claim 2, it comprises a plurality of circuit modules, the collection of first bipolar junction transistor in each circuit module extremely all is coupled to the described base stage of described first dead resistance and described first parasitic bipolar junction transistor, and the collection of second bipolar junction transistor in each circuit module extremely all is coupled to the described base stage of described second dead resistance and described second parasitic bipolar junction transistor.
4. integrated circuit according to claim 1, it also comprises impedance component, is coupled between described signal bonding pad and the described internal circuit.
5. integrated circuit according to claim 1, wherein, described first metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor.
6. integrated circuit according to claim 1, wherein, described first metal oxide semiconductor transistor is the P-type mos transistor.
7. integrated circuit according to claim 1, it comprises a plurality of circuit modules, and the collection of first bipolar junction transistor in each circuit module extremely all is coupled to the described base stage of described first dead resistance and described first parasitic bipolar junction transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100816673A CN101521372B (en) | 2008-02-27 | 2008-03-05 | Integrated circuit with electrostatic discharge protecting circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810082716 | 2008-02-27 | ||
| CN200810082716.5 | 2008-02-27 | ||
| CN2008100816673A CN101521372B (en) | 2008-02-27 | 2008-03-05 | Integrated circuit with electrostatic discharge protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101521372A CN101521372A (en) | 2009-09-02 |
| CN101521372B true CN101521372B (en) | 2011-02-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100816673A Active CN101521372B (en) | 2008-02-27 | 2008-03-05 | Integrated circuit with electrostatic discharge protecting circuit |
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| CN (1) | CN101521372B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201306416A (en) * | 2011-07-28 | 2013-02-01 | Raydium Semiconductor Corp | Electric apparatus with ESD protection effect |
| CN113559350A (en) * | 2021-08-02 | 2021-10-29 | 北京哈特凯尔医疗科技有限公司 | Control circuit of hydration treatment liquid inlet and outlet balance system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903419A (en) * | 1997-09-29 | 1999-05-11 | Motorola, Inc. | Circuit for electrostatic discharge (ESD) protection |
| CN1489210A (en) * | 2002-10-08 | 2004-04-14 | 台湾积体电路制造股份有限公司 | Static discharge protection circuit and relative metal oxide semiconductor transistor structure |
| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
-
2008
- 2008-03-05 CN CN2008100816673A patent/CN101521372B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903419A (en) * | 1997-09-29 | 1999-05-11 | Motorola, Inc. | Circuit for electrostatic discharge (ESD) protection |
| CN1489210A (en) * | 2002-10-08 | 2004-04-14 | 台湾积体电路制造股份有限公司 | Static discharge protection circuit and relative metal oxide semiconductor transistor structure |
| CN1658388A (en) * | 2004-02-18 | 2005-08-24 | 富士通株式会社 | Electrostatic discharge protection circuit |
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| Publication number | Publication date |
|---|---|
| CN101521372A (en) | 2009-09-02 |
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