CN114388493A - ESD protection circuit - Google Patents
ESD protection circuit Download PDFInfo
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- CN114388493A CN114388493A CN202011141158.2A CN202011141158A CN114388493A CN 114388493 A CN114388493 A CN 114388493A CN 202011141158 A CN202011141158 A CN 202011141158A CN 114388493 A CN114388493 A CN 114388493A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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Abstract
The invention discloses an ESD (electro-static discharge) protection circuit, and relates to the technical field of integrated circuits. The circuit comprises an analog circuit module, a digital circuit module and an isolation unit, wherein the analog circuit module is isolated from the digital circuit module through the isolation unit; the analog circuit module comprises a plurality of analog signal output units, a plurality of analog power supply units and a plurality of analog ground units, and is arranged in a mode that N analog signal output units, one analog power supply unit, N analog signal output units and one analog ground unit are in a group; the digital circuit module comprises a plurality of GPIO units, a plurality of digital power supply units and a plurality of digital ground units, and is arranged in a mode that M GPIO units, one digital power supply unit, M GPIO units and one digital ground unit are in a group. According to the technical scheme, the analog circuit module and the digital circuit module are isolated through the isolation unit, so that the ESD capability of the circuit is enhanced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an ESD protection circuit.
Background
In CMOS integrated circuits, with the evolution of mass production processes, the size of devices has reached deep submicron or even nanometer level, which raises some reliability issues while improving the performance of integrated circuits, increasing the operation speed and reducing the chip area. In the CMOS devices, due to advanced processes and shrinking of the device size, the ability of the CMOS integrated circuit to Discharge ESD (Electro-static Discharge) is greatly reduced, and the externally generated static electricity is not reduced, so that the damage of the CMOS integrated circuit due to ESD is more serious. ESD is a major factor causing most electronic devices or systems to be damaged by Electrical Overstress (EOS). Such damage causes permanent damage to the semiconductor components and systems, thereby affecting the circuit function of the integrated circuit and rendering the electronic product useless.
Disclosure of Invention
The invention mainly aims to provide an ESD protection circuit, aiming at enhancing the ESD capability of the circuit.
In order to achieve the above object, the present invention provides an ESD protection circuit, which includes an analog circuit module, a digital circuit module, and an isolation unit, wherein the analog circuit module is isolated from the digital circuit module by the isolation unit;
the analog circuit module comprises a plurality of analog signal output units, a plurality of analog power supply units and a plurality of analog ground units, and is arranged in a mode that N analog signal output units, one analog power supply unit, N analog signal output units and one analog ground unit are in a group;
the digital circuit module comprises a plurality of GPIO units, a plurality of digital power supply units and a plurality of digital ground units, and is arranged in a mode that M GPIO units, one digital power supply unit, M GPIO units and one digital ground unit are in a group.
Preferably, the analog power supply units are communicated with one another, and the analog ground units are communicated with one another; the digital power supply units are communicated with one another, and the digital ground units are communicated with one another.
Preferably, the isolation unit comprises a first diode and a second diode connected in parallel, wherein the anode of the first diode is connected to an analog ground, the cathode of the first diode is connected to a digital ground, and the anode of the second diode is connected to the digital ground, and the cathode of the second diode is connected to the analog ground.
Preferably, N in the group of N analog signal output units, one analog power supply unit, N analog signal output units, and one analog ground unit is 2 to 6.
Preferably, the N analog signal output units are 4 analog signal output units.
Preferably, M in the group of M GPIO units, one digital power supply unit, M GPIO units, and one digital ground unit is 2-6.
Preferably, the M GPIO units are 4 GPIO units.
Preferably, the digital power supply unit, the analog power supply unit, the digital ground unit and the analog ground unit are all in an RC Clamp structure.
Preferably, the analog signal output unit and the GPIO unit include driving transistors of GGPMOS and/or GGNMOS structures.
According to the technical scheme, the analog circuit module and the digital circuit module are isolated through the isolation unit, and are respectively arranged in the form of N analog signal output units, an analog power supply unit, N analog signal output units, an analog ground unit, M GPIO units, a digital power supply unit, M GPIO units and a digital ground unit, so that the circuit is provided with extremely strong ESD capacity.
Drawings
FIG. 1 is a schematic diagram of an ESD protection circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of an isolation unit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a digital power supply unit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of an analog signal output unit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a GPIO unit in an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
An embodiment of the invention provides an ESD protection circuit, as shown in fig. 1, for enhancing ESD capability of a core of a chip. The ESD protection circuit comprises an analog circuit module, a digital circuit module and an isolation unit, wherein the analog circuit module is isolated from the digital circuit module through the isolation unit; the Analog circuit module comprises a plurality of Analog signal output units (Analog PADs), a plurality of Analog Power supply units (Power PADs 1) and a plurality of Analog Ground PADs 1, and is arranged in a mode that N Analog signal output units (Analog PADs), one Analog Power supply unit (Power PAD 1), N Analog signal output units (Analog PADs) and one Analog Ground PAD1 are in a group; the digital circuit module comprises a plurality of GPIO units GPIO, a plurality of digital Power supply units Power PAD2 and a plurality of digital Ground units group PAD2, and M GPIO units GPIO, one digital Power supply unit Power PAD2, M GPIO units GPIO and one digital Ground unit group PAD2 are arranged in a group.
In some embodiments, N in a group of N of the Analog PADs, one of the Power PADs 1, N of the Analog PADs, one of the Ground PADs 1 is 2-6. M in a group of M GPIO units GPIO, one digital Power supply unit Power PAD2, M GPIO units GPIO, one digital Ground unit group PAD2 is 2-6.
In a preferred embodiment, the N Analog signal output units Analog PAD are 4 Analog signal output units Analog PAD. Specifically, one Analog Power supply unit Power PAD1 or one Analog Ground unit group PAD1 is placed in every 4 Analog signal output units Analog PAD, so that the impedance between two adjacent Analog Power supply units Power PAD1 and Analog Ground PAD1 can be guaranteed not to exceed 1 ohm, and the impedance of the circuit can be guaranteed not to be too large.
In a preferred embodiment, the M GPIO units GPIO are 4 GPIO units GPIO. Specifically, one digital Power supply unit Power PAD2 or digital Ground PAD2 is placed every 4 GPIO units GPIO, so that the impedance between two adjacent digital Power supply units Power PAD2 and digital Ground PAD2 is not more than 1 ohm, and the impedance of the circuit is not too large.
In some embodiments, each of the analog Power supply units Power PAD1 and each of the analog Ground units group PAD1 are connected to each other; the digital Power supply units Power PAD2 are communicated with each other, and the digital Ground PAD2 are communicated with each other. Specifically, each power supply and each ground are respectively connected, and a power supply ground network is reasonably planned to ensure that the impedance between any two power supply PADs and any two ground PADs does not exceed 1.5 ohms so as to ensure that the impedance of the circuit is not too large.
Preferably, as shown in fig. 2, the isolation unit includes a first diode D1 and a second diode D2 connected in parallel, the anode of the first diode D1 is connected to the analog ground VSSA, the cathode of the first diode D1 is connected to the digital ground VSSD, and the anode of the second diode D2 is connected to the digital ground VSSD, and the cathode of the second diode D2 is connected to the analog ground VSSA. The isolation unit adopts a diode structure, and can isolate the Analog ground VSSA and the digital ground VSSD so as to avoid the interference of the digital ground VSSD from influencing the Analog signal output by the Analog PAD unit. Specifically, the analog ground VSSA is the ground of the analog circuit block, and the digital ground VSSD is the ground of the digital circuit block.
Preferably, the digital Power supply unit Power PAD2, the analog Power supply unit Power PAD1, the digital Ground PAD2 and the analog Ground PAD1 are all RC Clamp structures.
Specifically, as shown in fig. 3, taking the digital Power supply unit Power PAD2 as an example: the digital Power supply unit Power PAD2 comprises a first resistor R1, a second resistor R2 and a first NMOS transistor MN1 which are connected to an IO Power supply, and a first capacitor C1 and a third resistor R3 which are connected to an IO ground; the first resistor R1 is further connected with one end of a first capacitor C1 and the input end of an inverter P, and the other end of the first capacitor C1 is connected with IO ground; the power supply end of the inverter P is connected to the IO power supply through the second resistor R2, and the ground end of the inverter P is connected to the IO ground through the third resistor R3; the output end of the phase inverter P is connected to the grid electrode of the first NMOS transistor MN1, the drain electrode of the first NMOS transistor MN1 is connected to an IO power supply, and the source electrode of the first NMOS transistor MN1 is connected to an IO ground. Specifically, the first resistor R1 and the first capacitor C1 form an RC charging and discharging circuit, and the charging time is to ensure the conduction of the first NMOS transistor MN1, so that the ESD current on the IO power supply is fully discharged to the digital ground. The inverter P is connected to an IO power supply and an IO ground through the second resistor R2 and the third resistor R3, when ESD current comes from the IO power supply and the IO ground, a tube of the inverter P can be protected from being damaged, and values of the second resistor R2 and the third resistor R3 are about 50-100 omega. The first NMOS transistor MN1 is used as a main ESD discharge path, and is turned on/off by the RC charging/discharging circuit, so as to ensure complete discharge of ESD current, and at the same time, it cannot be turned on under high voltage for a long time, and thus the turn-on time is 200-400 ns.
In the embodiment, the structures of the digital Power supply unit Power PAD2, the analog Power supply unit Power PAD1, the digital Ground PAD2 and the analog Ground PAD1 are the same, so that the design difficulty and the follow-up work can be reduced. In other embodiments, the structures of the digital Power supply unit Power PAD2, the analog Power supply unit Power PAD1, the digital Ground PAD2, and the analog Ground PAD1 may also be different, and may be modified accordingly according to specific circuit designs to meet different circuit design requirements.
Preferably, the Analog signal output unit Analog PAD and the GPIO unit GPIO include driving tubes of GGPMOS and/or GGNMOS structures, which are ESD-configured through the GGPMOS and/or GGNMOS structures.
Specifically, as shown in fig. 4, the Analog PAD includes a first PMOS transistor MP1 connected to the IO power supply and a second NMOS transistor MN2 connected to the first PMOS transistor MP 1. The source and the gate of the first PMOS transistor MP1 are connected to the IO power supply, and the drain is connected to the drain of the second NMOS transistor MN2 and the analog power supply; the gate and source of the second NMOS transistor MN2 are connected to IO ground.
Specifically, as shown in fig. 5, the GPIO unit GPIO includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5 connected to the input terminal and the output terminal, and a PAD terminal connected to the internal circuit. Drains of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to each other and to an input terminal, an output terminal and a PAD terminal; the gates of the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to each other and to the output terminal, and the gates of the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to each other and to the output terminal. The sources of the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the digital power supply, and the sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to the digital ground. When ESD is needed, the PMOS driving tube is of a GGPMOS structure, and ESD large current on a PAD end can be discharged to a digital Power supply unit Power PAD 2; similarly, the NMOS driver is also a GGNMOS structure, and can discharge the ESD large current on the PAD terminal to the digital Ground PAD 2.
In particular, in the embodiment of the ESD protection circuit of the present invention, the type of the device used by the protection circuit needs to be consistent with the type of the device to be protected.
In some embodiments, an ESD implant may be added to the layout design according to the process rules to further enhance the ESD capability of the circuit.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. An ESD protection circuit is characterized by comprising an analog circuit module, a digital circuit module and an isolation unit, wherein the analog circuit module and the digital circuit module are isolated by the isolation unit;
the analog circuit module comprises a plurality of analog signal output units, a plurality of analog power supply units and a plurality of analog ground units, and is arranged in a mode that N analog signal output units, one analog power supply unit, N analog signal output units and one analog ground unit are in a group;
the digital circuit module comprises a plurality of GPIO units, a plurality of digital power supply units and a plurality of digital ground units, and is arranged in a mode that M GPIO units, one digital power supply unit, M GPIO units and one digital ground unit are in a group.
2. The ESD protection circuit of claim 1, wherein each of said analog power cells is in communication with each other, and each of said analog ground cells is in communication with each other; the digital power supply units are communicated with one another, and the digital ground units are communicated with one another.
3. The ESD protection circuit of claim 1, wherein the isolation unit comprises a first diode and a second diode connected in parallel, the first diode having an anode connected to an analog ground and a cathode connected to a digital ground, the second diode having an anode connected to the digital ground and a cathode connected to the analog ground.
4. The ESD protection circuit of claim 1, wherein N in the set of N analog signal output units, one analog power supply unit, N analog signal output units, and one analog ground unit is 2-6.
5. The ESD protection circuit according to claim 4, wherein the N analog signal output units are 4 analog signal output units.
6. The ESD protection circuit of claim 1, wherein M of the set of M of the GPIO cells, one of the digital power supply cells, M of the GPIO cells, one of the digital ground cells is 2-6.
7. The ESD protection circuit of claim 6 wherein the M GPIO cells are 4 GPIO cells.
8. The ESD protection circuit of claim 1, wherein the digital power supply unit, the analog power supply unit, the digital ground unit, and the analog ground unit are all RC Clamp structures.
9. The ESD protection circuit of claim 1, wherein the analog signal output unit and the GPIO unit comprise driver transistors of GGPMOS and/or GGNMOS structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011141158.2A CN114388493A (en) | 2020-10-22 | 2020-10-22 | ESD protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011141158.2A CN114388493A (en) | 2020-10-22 | 2020-10-22 | ESD protection circuit |
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| CN114388493A true CN114388493A (en) | 2022-04-22 |
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| CN202011141158.2A Pending CN114388493A (en) | 2020-10-22 | 2020-10-22 | ESD protection circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117291139A (en) * | 2023-11-27 | 2023-12-26 | 成都锐成芯微科技股份有限公司 | DCDC voltage stabilizer with optimized layout |
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2020
- 2020-10-22 CN CN202011141158.2A patent/CN114388493A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117291139A (en) * | 2023-11-27 | 2023-12-26 | 成都锐成芯微科技股份有限公司 | DCDC voltage stabilizer with optimized layout |
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