CN117291139A - DCDC voltage stabilizer with optimized layout - Google Patents
DCDC voltage stabilizer with optimized layout Download PDFInfo
- Publication number
- CN117291139A CN117291139A CN202311592613.4A CN202311592613A CN117291139A CN 117291139 A CN117291139 A CN 117291139A CN 202311592613 A CN202311592613 A CN 202311592613A CN 117291139 A CN117291139 A CN 117291139A
- Authority
- CN
- China
- Prior art keywords
- ground
- lines
- power
- layer
- driving unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 title claims abstract description 24
- 239000003381 stabilizer Substances 0.000 title claims abstract description 10
- 230000003068 static effect Effects 0.000 claims abstract description 22
- 230000005611 electricity Effects 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 6
- 238000005457 optimization Methods 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
- H05F1/00—Preventing the formation of electrostatic charges
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a DCDC voltage stabilizer with optimized layout, which comprises a driving unit and an electrostatic protection unit, wherein the driving unit comprises a PMOS driving unit and an NMOS driving unit; the static protection unit is located between the PMOS driving unit and the NMOS driving unit so as to separate the PMOS driving unit from the NMOS driving unit, a plurality of layers of wiring networks which are mutually communicated are arranged above the driving unit and the static protection unit, and the wiring networks comprise power lines, ground lines and VX network which are alternately distributed. The DCDC voltage stabilizer with optimized layout reduces latch-up risk and enhances ESD capability.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a DCDC voltage stabilizer with optimized layout.
Background
In the field of semiconductor chip design, DC-DC (Direct Current-Direct Current) is a common power converter, and is widely applied to various chips due to its high conversion efficiency and other characteristics. However, since the current of the DC-DC voltage regulator is very large, usually hundreds of milliamperes, a designer needs to pay special attention when laying out wires in the design process, and ESD (Electro-Static discharge) and latch up risks are extremely easily caused once the operation is improper. Taking BUCK DC-DC (Buck Direct Current-Direct Current) as an example, the BUCK type circuit is mainly composed of a field effect transistor, a resistor, a capacitor and the like, the BUCK is realized by controlling the on and off of the field effect transistor, the layout of the BUCK is also critical, the area of a driving tube is large because of the large Current, the probability of latch-up is large, and the ESD capability of the circuit is considered. There is therefore a need to provide a new solution to the above-mentioned problems.
Disclosure of Invention
The invention mainly aims to provide a DCDC voltage stabilizer with optimized layout, which aims to prevent latch up risk and improve ESD capability.
In order to achieve the above purpose, the invention provides a DCDC voltage stabilizer with optimized layout, which comprises a driving unit and an electrostatic protection unit, wherein the driving unit comprises a PMOS driving unit and an NMOS driving unit; the static electricity protection unit is positioned between the PMOS driving unit and the NMOS driving unit to separate the PMOS driving unit from the NMOS driving unit on a wafer; and a plurality of layers of wiring networks which are mutually communicated are arranged above the driving unit and the static electricity protection unit, and each wiring network comprises power lines, ground lines and VX (virtual X) network which are alternately distributed.
Preferably, the PMOS driving unit includes a plurality of PMOS driving pipes, and at least one layer of the plurality of power lines and the plurality of VX lines are alternately distributed in a transverse direction, and at least one layer of the plurality of power lines and the plurality of VX lines are alternately distributed in a longitudinal direction above the PMOS driving pipes;
the NMOS driving unit comprises a plurality of NMOS driving pipes, wherein at least one layer of ground wires and VX wires which are alternately distributed transversely are arranged above the NMOS driving pipes, and at least one layer of ground wires and VX wires which are alternately distributed longitudinally are arranged;
the power line above the PMOS driving tube extends to the upper part of the static electricity protection unit, is close to the ground line above the NMOS driving tube and extends to the upper part of the static electricity protection unit, and the distance between the power line and the ground line is 1/3 of the line width of the power line/the ground line; the VX line above the PMOS driving tube extends to the upper part of the static electricity protection unit and is connected with the VX line above the NMOS driving tube;
and the upper part of the static electricity protection unit also comprises at least one layer of a plurality of power lines, ground lines and VX lines which are longitudinally and alternately distributed.
Preferably, in the wiring network layer which is laterally and alternately distributed, the width of the part of the power line above the PMOS driving tube extending to the upper part of the electrostatic protection unit is reduced to be half of the original width; the part of the ground wire above the NMOS driving tube extending to the upper part of the static electricity protection unit is reduced to half of the original width, the part of the ground wire and the power wire extending to the upper part of the static electricity protection unit are arranged in parallel to form a power wire and a ground wire which are equivalent to the original width, and a wiring network in which the ground wire, the power wire and the VX wire are alternately distributed is formed with the VX wire above the static electricity protection unit.
Preferably, the PMOS driving unit further includes a first logic circuit, and the NMOS driving unit further includes a second logic circuit; the upper part of the first logic circuit comprises at least one layer of a plurality of power lines, a plurality of ground lines and at least one layer of power lines which are distributed transversely; the second logic circuit comprises at least one layer of a plurality of power lines and a plurality of ground lines which are distributed transversely and at least one layer of ground lines which are distributed longitudinally.
Preferably, in the wiring network layer distributed laterally, the power lines above the electrostatic protection units adjacent to the first logic circuit and the second logic circuit are distributed across the ground line so as to be connected to the power lines above the first logic circuit and the second logic circuit and the ground line, respectively.
Preferably, the electrostatic protection unit has a GGNMOS structure.
Preferably, the power line, the ground line and the VX line which are distributed transversely are positioned on the same layer, and the power line, the ground line and the VX line which are distributed longitudinally are positioned on the same layer.
Preferably, the wiring network further comprises a packaging pad above the wiring network, wherein the packaging pad comprises a power supply packaging pad above the PMOS driving tube, a ground packaging pad above the NMOS driving tube, and a VX packaging pad above the electrostatic protection unit and in the surrounding areas of the power supply packaging pad and the ground packaging pad.
Preferably, the package pad is formed of a metal layer on top of the die.
Preferably, the power line, the ground line and the VX line are formed of a metal layer on the upper portion of the wafer.
According to the technical scheme, the layout is optimized, and the isolation technology of separating the PMOS driving unit from the NMOS driving unit through the electrostatic protection unit is adopted, so that the latch up risk is reduced, and the ESD capability is enhanced.
Drawings
FIG. 1 is a schematic diagram of a layout in a DCDC voltage regulator with layout optimization according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a laterally routed network in a layout optimized DCDC voltage regulator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a network with vertical routing in a layout optimized DCDC voltage regulator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a packaged pad in a DCDC voltage regulator with optimized layout according to an embodiment of the present invention.
Reference numerals:
a PMOS driving unit 1, a first logic circuit 11, a PMOS driving tube 12;
an NMOS drive unit 2, a second logic circuit 21, an NMOS drive pipe 22;
an electrostatic protection unit 3;
a power line 31, a ground line 32, and a vx line 33;
the power package pad P100, the ground package pad G200, and the VX package pad VX300.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention is further described below with reference to the accompanying drawings.
An embodiment of the present invention provides a DCDC voltage regulator with optimized layout, as shown in fig. 1, including: a driving unit and an electrostatic protection unit 3, wherein the driving unit comprises a PMOS driving unit 1 and an NMOS driving unit 2; the static protection unit is located between the PMOS driving unit 1 and the NMOS driving unit 2 to separate the PMOS driving unit and the NMOS driving unit from each other, and a multi-layer wiring network connected with each other is arranged above the driving unit and the static protection unit 3, and the wiring network includes a power line 31, a ground line 32, and a VX line 33 network which are alternately distributed.
According to the embodiment of the invention, the layout is optimized, and the isolation technology of separating the PMOS driving unit 1 from the NMOS driving unit 2 by the electrostatic protection unit 3 is adopted, so that the latch up risk is reduced, and the ESD capability is enhanced.
Specifically, the number of layers of the wiring network is related to factors such as the process and materials selected in actual operation.
In a preferred embodiment, the electrostatic protection unit 3 is constituted by a GGNMOS tube, serving as electrostatic protection.
In a preferred embodiment, as shown in fig. 1-3, the PMOS driving unit 1 includes a plurality of PMOS driving tubes 12, and at least one layer of a plurality of power lines 31 and a plurality of VX lines 33 alternately distributed in a lateral direction and at least one layer of a plurality of power lines 31 and a plurality of VX lines 33 alternately distributed in a longitudinal direction are disposed above the PMOS driving tubes 12; the NMOS driving unit 2 includes a plurality of NMOS driving tubes 22, and at least one layer of ground lines 32 and VX lines 33 alternately distributed in the lateral direction and at least one layer of ground lines 32 and VX lines 33 alternately distributed in the longitudinal direction are included above the NMOS driving tubes 22.
The power line 31 above the PMOS driving tube 12 extends above the electrostatic protection unit 3 and is close to the ground line 32 above the NMOS driving tube 22 and extends above the electrostatic protection unit 3, and the distance between the power line 31 and the ground line 32 is 1/3 of the line width of the power line 31/ground line 32; the VX line 33 above the PMOS driving tube 12 extends to above the electrostatic protection unit 3, and is connected to the VX line 33 above the NMOS driving tube 22; in other embodiments, the spacing between the power line 31 and the ground line 32 may be designed according to different processes, and only the DRC (design rule check ) rule needs to be satisfied.
The electrostatic protection unit 3 further comprises at least one layer of a plurality of power lines 31, ground lines 32 and VX lines 33 which are longitudinally and alternately distributed. Specifically, in the wiring network layer distributed longitudinally, the number of the power supply lines 31, the ground lines 32 and the VX lines 33 above the electrostatic protection unit 3 is related to the actual area of the electrostatic protection unit 3, and the designer can arrange the power supply lines 31, the ground lines 32 and the VX lines 33 as much as possible on the premise of meeting DRC rules. In a specific embodiment, the pitches among the power line 31, the ground line 32 and the VX line 33 may be designed according to different processes, only to satisfy DRC rules.
Specifically, as shown in fig. 2, in the wiring network layer distributed laterally, the width of the portion of the power line 31 above the PMOS driving tube 12 extending above the electrostatic protection unit 3 is reduced to half of the original width; the ground line 32 above the NMOS drive tube 22 is reduced in width to half of the original width to a portion above the electrostatic protection unit 3, the power line 31 and the ground line 32 corresponding to the original width are formed in parallel with the power line 31 extending above the electrostatic protection unit 3, and the ground line 32, the power line 31, and the VX line 33 above the electrostatic protection unit 3 form a wiring network alternately distributed. Specifically, the spacing between the parallel power line 31 and ground line 32 is 1/3 of the line width of the power line 31/ground line 32. In the embodiment of the invention, 1/3 of the line width of the power line 31/ground line 32 is used as the distance between the power line 31 and the ground line 32, so that the uniformity of current can be enhanced, and the improvement of ESD capability is facilitated.
In a preferred embodiment, the PMOS driving unit further comprises a first logic circuit 11, and at least one layer of a plurality of power lines 31 and a plurality of ground lines 32 distributed laterally and at least one layer of power lines 31 distributed longitudinally are included above the first logic circuit 11.
Specifically, in actual design work, the first logic circuit 11 is relatively small in position in the driving unit, and the power lines 31 and the ground lines 32 may be distributed according to the actual area size, but in general, the number of the power lines 31 should be equivalent to the number of the ground lines 32. Meanwhile, above the first logic circuit 11, the power lines 31 distributed longitudinally and the power lines 31 distributed laterally are mutually connected.
The NMOS drive unit further includes a second logic circuit 21, and at least one layer of a plurality of power supply lines 31 and a plurality of ground lines 32 distributed in a lateral direction and at least one layer of ground lines 32 distributed in a longitudinal direction are included above the second logic circuit 21.
Specifically, in actual design work, the position of the second logic circuit 21 in the driving unit is relatively small, and the power lines 31 and the ground lines 32 may be distributed according to the actual area size, but in general, the number of the power lines 31 should be equivalent to the number of the ground lines 32. Meanwhile, above the second logic circuit 21, the ground lines 32 distributed longitudinally and the ground lines 32 distributed laterally are mutually connected.
Specifically, as shown in fig. 2, in the wiring network layer distributed laterally, the power supply lines 31 and the ground lines 32 above the electrostatic protection units 3 adjacent to the first logic circuits 11 and the second logic circuits 21 are distributed across to be connected to the power supply lines 31 and the ground lines 32 above the first logic circuits 11 and the second logic circuits 21, respectively. In the wiring network layer distributed longitudinally, the power supply lines 31 above the first logic circuits 11 are connected to the power supply lines 31 distributed laterally. The ground line 32 above the second logic circuit 21 is connected to the ground line 32 distributed laterally.
In a specific embodiment, the wiring network above the driving unit has multiple layers, and the multiple layers of wiring network are connected with each other through punching or the like, so that the power lines 31, the ground lines 32 and the VX lines 33 are connected with each other. The multi-layer wiring network connects MOS tubes, logic circuits and the like in the whole DCDC voltage stabilizer to complete the network of power supply-power supply, ground-ground and VX-VX in the DCDC voltage stabilizer.
Specifically, in the multi-layer wiring network, the wiring network layers distributed transversely and the wiring network layers distributed longitudinally are alternately distributed above the driving unit and the electrostatic protection unit 3, that is, the wiring network layers distributed longitudinally are above the wiring network layers distributed transversely, and the wiring network layers distributed transversely are above the wiring network layers distributed longitudinally.
In the embodiment, the power line 31, the ground line 32 and the VX line 33 which are distributed in the transverse direction are located in the same layer, and the power line 31, the ground line 32 and the VX line 33 which are distributed in the longitudinal direction are located in the same layer.
In a preferred embodiment, the power line 31, ground line 32 and VX line 33 are formed from a metal layer on top of the wafer.
In a preferred embodiment, as shown in fig. 4, the wiring network further includes a package pad above the wiring network, the package pad including a power package pad P100 above the PMOS driving tube 12, a ground package pad G200 above the NMOS driving tube 22, and a VX package pad VX300 above the electrostatic protection unit 3 and in a region surrounding the power package pad P100 and the ground package pad G200. In particular, the package pad completely covers the wiring network located thereunder. The packaging pad is formed by a metal layer at the upper part of the wafer, so that the uniformity of current is further enhanced, and the improvement of ESD (electro-static discharge) capability is facilitated; meanwhile, the VX packaging pad VX300 is arranged above the electrostatic protection unit 3, so that a projection area on a wafer is separated from a projection area of a power supply and a ground, noise brought by a switch circuit is shielded, and the latch up risk is effectively reduced.
It should be understood that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (10)
1. The DCDC voltage stabilizer with optimized layout is characterized by comprising a driving unit and an electrostatic protection unit, wherein the driving unit comprises a PMOS driving unit and an NMOS driving unit; the static electricity protection unit is positioned between the PMOS driving unit and the NMOS driving unit to separate the PMOS driving unit from the NMOS driving unit on a wafer;
and a plurality of layers of wiring networks which are mutually communicated are arranged above the driving unit and the static electricity protection unit, and each wiring network comprises power lines, ground lines and VX (virtual X) network which are alternately distributed.
2. The layout optimized DCDC voltage regulator according to claim 1, wherein the PMOS driving unit includes a plurality of PMOS driving pipes, and the PMOS driving pipes include at least one layer of the plurality of power lines and the plurality of VX lines that are alternately distributed in a lateral direction, and at least one layer of the plurality of power lines and the plurality of VX lines that are alternately distributed in a longitudinal direction;
the NMOS driving unit comprises a plurality of NMOS driving pipes, wherein at least one layer of ground wires and VX wires which are alternately distributed transversely are arranged above the NMOS driving pipes, and at least one layer of ground wires and VX wires which are alternately distributed longitudinally are arranged;
the power line above the PMOS driving tube extends to the upper part of the static electricity protection unit, is close to the ground line above the NMOS driving tube and extends to the upper part of the static electricity protection unit, and the distance between the power line and the ground line is 1/3 of the line width of the power line/the ground line; the VX line above the PMOS driving tube extends to the upper part of the static electricity protection unit and is connected with the VX line above the NMOS driving tube;
and the upper part of the static electricity protection unit also comprises at least one layer of a plurality of power lines, ground lines and VX lines which are longitudinally and alternately distributed.
3. The DCDC voltage regulator optimized for layout optimization according to claim 2, wherein in the wiring network layer alternately distributed in the lateral direction, the width of the portion of the power line above the PMOS driving tube extending above the electrostatic protection unit is reduced to half of the original width; the part of the ground wire above the NMOS driving tube extending to the upper part of the static electricity protection unit is reduced to half of the original width, the part of the ground wire and the power wire extending to the upper part of the static electricity protection unit are arranged in parallel to form a power wire and a ground wire which are equivalent to the original width, and a wiring network in which the ground wire, the power wire and the VX wire are alternately distributed is formed with the VX wire above the static electricity protection unit.
4. The layout optimized DCDC voltage regulator of claim 2, wherein the PMOS driver unit further comprises a first logic circuit and the NMOS driver unit further comprises a second logic circuit; the upper part of the first logic circuit comprises at least one layer of a plurality of power lines, a plurality of ground lines and at least one layer of power lines which are distributed transversely; the second logic circuit comprises at least one layer of a plurality of power lines and a plurality of ground lines which are distributed transversely and at least one layer of ground lines which are distributed longitudinally.
5. The DCDC voltage regulator of claim 4, wherein the power lines above the electrostatic protection cells adjacent to the first logic circuit and the second logic circuit are distributed across the ground line in a laterally distributed routing network layer to connect the power lines above the first logic circuit and the second logic circuit with the ground line, respectively.
6. A DCDC voltage regulator with optimized layout according to claim 3, wherein the electrostatic protection unit is composed of GGNMOS transistors.
7. The layout optimized DCDC voltage regulator of claim 2, wherein the transversely distributed power lines, ground lines, VX are on the same layer, and the longitudinally distributed power lines, ground lines, VX are on the same layer.
8. The layout optimized DCDC voltage regulator of claim 2, further comprising a package pad above the routing network, the package pad comprising a power supply package pad above the PMOS drive tube, a ground package pad above the NMOS drive tube, and VX package pads above the electrostatic protection unit and in areas surrounding the power supply package pad and ground package pad.
9. The layout optimized DCDC voltage regulator of claim 8, wherein the package pad is formed from a metal layer on top of the die.
10. The layout optimized DCDC voltage regulator of claim 1, wherein the power, ground and VX lines are formed from a metal layer on top of the die.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311592613.4A CN117291139A (en) | 2023-11-27 | 2023-11-27 | DCDC voltage stabilizer with optimized layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311592613.4A CN117291139A (en) | 2023-11-27 | 2023-11-27 | DCDC voltage stabilizer with optimized layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117291139A true CN117291139A (en) | 2023-12-26 |
Family
ID=89258977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311592613.4A Pending CN117291139A (en) | 2023-11-27 | 2023-11-27 | DCDC voltage stabilizer with optimized layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117291139A (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040228066A1 (en) * | 2003-05-16 | 2004-11-18 | Nec Electronics Corporation | Capacitor cell, semiconductor device and process for manufacturing the same |
| US20080042686A1 (en) * | 2006-06-28 | 2008-02-21 | Kanji Otsuka | Electrostatic discharge protection circuit and terminating resistor circuit |
| CN101442869A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Dynamic detection electrostatic protection circuit |
| US20110234184A1 (en) * | 2010-03-26 | 2011-09-29 | Panasonic Corporation | Start-up in-rush current protection circuit for dcdc converter |
| CN106206570A (en) * | 2016-08-23 | 2016-12-07 | 灿芯半导体(上海)有限公司 | The integrated circuit of layout optimization |
| CN206532778U (en) * | 2017-03-07 | 2017-09-29 | 灿芯半导体(上海)有限公司 | The integrated circuit of layout optimization |
| CN107228991A (en) * | 2017-06-05 | 2017-10-03 | 安徽福讯信息技术有限公司 | A kind of component storehouse electrostatic protection real-time monitoring system |
| CN108649805A (en) * | 2018-06-14 | 2018-10-12 | 成都信息工程大学 | High power D C-DC power-switching circuits based on isolation and delay technology |
| CN109148439A (en) * | 2018-08-14 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Full chip electrostatic releasing network |
| CN112670283A (en) * | 2019-10-15 | 2021-04-16 | 南亚科技股份有限公司 | Off-chip driver structure |
| CN112771615A (en) * | 2018-09-29 | 2021-05-07 | 英特尔公司 | Dual power I/O transmitter |
| CN113393816A (en) * | 2021-06-07 | 2021-09-14 | 无锡十顶电子科技有限公司 | Scheme for reducing cost of liquid crystal display driving chip |
| WO2022051701A1 (en) * | 2020-09-04 | 2022-03-10 | Texas Instruments Incorporated | Isolated dc-dc power converter with low radiated emissions |
| CN114388493A (en) * | 2020-10-22 | 2022-04-22 | 成都锐成芯微科技股份有限公司 | ESD protection circuit |
-
2023
- 2023-11-27 CN CN202311592613.4A patent/CN117291139A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040228066A1 (en) * | 2003-05-16 | 2004-11-18 | Nec Electronics Corporation | Capacitor cell, semiconductor device and process for manufacturing the same |
| US20080042686A1 (en) * | 2006-06-28 | 2008-02-21 | Kanji Otsuka | Electrostatic discharge protection circuit and terminating resistor circuit |
| CN101442869A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Dynamic detection electrostatic protection circuit |
| US20110234184A1 (en) * | 2010-03-26 | 2011-09-29 | Panasonic Corporation | Start-up in-rush current protection circuit for dcdc converter |
| CN106206570A (en) * | 2016-08-23 | 2016-12-07 | 灿芯半导体(上海)有限公司 | The integrated circuit of layout optimization |
| CN206532778U (en) * | 2017-03-07 | 2017-09-29 | 灿芯半导体(上海)有限公司 | The integrated circuit of layout optimization |
| CN107228991A (en) * | 2017-06-05 | 2017-10-03 | 安徽福讯信息技术有限公司 | A kind of component storehouse electrostatic protection real-time monitoring system |
| CN108649805A (en) * | 2018-06-14 | 2018-10-12 | 成都信息工程大学 | High power D C-DC power-switching circuits based on isolation and delay technology |
| CN109148439A (en) * | 2018-08-14 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Full chip electrostatic releasing network |
| CN112771615A (en) * | 2018-09-29 | 2021-05-07 | 英特尔公司 | Dual power I/O transmitter |
| CN112670283A (en) * | 2019-10-15 | 2021-04-16 | 南亚科技股份有限公司 | Off-chip driver structure |
| WO2022051701A1 (en) * | 2020-09-04 | 2022-03-10 | Texas Instruments Incorporated | Isolated dc-dc power converter with low radiated emissions |
| CN116114158A (en) * | 2020-09-04 | 2023-05-12 | 德克萨斯仪器股份有限公司 | Isolated DC-DC power converter with low radiation emissions |
| CN114388493A (en) * | 2020-10-22 | 2022-04-22 | 成都锐成芯微科技股份有限公司 | ESD protection circuit |
| CN113393816A (en) * | 2021-06-07 | 2021-09-14 | 无锡十顶电子科技有限公司 | Scheme for reducing cost of liquid crystal display driving chip |
Non-Patent Citations (1)
| Title |
|---|
| 柴常春;张冰;杨银堂;吴晓鹏;王婧;: "一种抑制ESD保护电路闩锁效应的版图研究", 电路与系统学报, no. 01, 15 February 2013 (2013-02-15) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7280329B2 (en) | Integrated circuit device having input/output electrostatic discharge protection cell equipped with electrostatic discharge protection element and power clamp | |
| JP6898570B2 (en) | Semiconductor integrated circuit equipment | |
| CN101211911B (en) | Semiconductor integrated circuit | |
| US7964968B2 (en) | Semiconductor integrated circuit | |
| KR100433199B1 (en) | I/o cell placement method and semiconductor device | |
| US11824055B2 (en) | Semiconductor integrated circuit device | |
| CN100428462C (en) | Semiconductor integrated circuit device | |
| US6399991B1 (en) | Semiconductor integrated circuit | |
| WO2021090471A1 (en) | Semiconductor integrated circuit device | |
| US7660085B2 (en) | Semiconductor device | |
| US20080137245A1 (en) | Semiconductor device | |
| US7449750B2 (en) | Semiconductor protection device | |
| US20040206985A1 (en) | Semiconductor integrated circuit | |
| CN117291139A (en) | DCDC voltage stabilizer with optimized layout | |
| US7394143B2 (en) | Semiconductor integrated circuit device | |
| JP5168872B2 (en) | Semiconductor integrated circuit | |
| CN102339824A (en) | Defectivity-immune technique of implementing MIM-based decoupling capacitors | |
| WO2024047820A1 (en) | Semiconductor integrated-circuit device | |
| US20240213770A1 (en) | Semiconductor integrated circuit device | |
| WO2022215485A1 (en) | Semiconductor integrated circuit device | |
| JP2010225782A (en) | Semiconductor integrated circuit device | |
| CN117397029A (en) | Semiconductor integrated circuit device with a plurality of semiconductor chips | |
| TW202341002A (en) | Integrated circuit layout and semiconductor die | |
| JP2022135584A (en) | Semiconductor device | |
| CN116913914A (en) | Integrated circuit layout and semiconductor die |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |