CN103872039B - The manufacture method of ESD protection circuit - Google Patents
The manufacture method of ESD protection circuit Download PDFInfo
- Publication number
- CN103872039B CN103872039B CN201210530228.2A CN201210530228A CN103872039B CN 103872039 B CN103872039 B CN 103872039B CN 201210530228 A CN201210530228 A CN 201210530228A CN 103872039 B CN103872039 B CN 103872039B
- Authority
- CN
- China
- Prior art keywords
- doped portion
- cooling element
- metal
- amber ear
- ear note
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention discloses a kind of ESD protection circuit, comprise the grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor be positioned in Semiconductor substrate, the drain electrode of described ggnmos transistor connects the input/output terminal of chip circuit, source electrode and grid and the equal ground connection of Semiconductor substrate; This circuit also comprises and is positioned near described ggnmos transistor, for absorbing the amber ear note cooling element of the heat that described ggnmos transistor produces.The invention also discloses a kind of manufacture method of ESD protection circuit.Adopt the present invention can extend the working life of ESD protective device.
Description
Technical field
The present invention relates to IC manufacturing field, particularly a kind of manufacture method of ESD protection circuit.
Background technology
In integrated circuit (IC) chip manufacturing and final application system, along with improving constantly of very lagre scale integrated circuit (VLSIC) technology, current CMOS (Complementary Metal Oxide Semiconductor) pipe (CMOS) integrated circuit has entered the sub-micro stage, the size of MOS device constantly reduces, the harm of static discharge (ElectrostaticDischarge, ESD) to integrated circuit becomes more and more significant.According to statistics, 35% is had caused by ESD problem in the product of ic failure.Therefore, esd protection design is carried out to integrated circuit and also become particularly important.
When using device to carry out esd protection to integrated circuit, conventional device is grounded-grid NMOS tube (GGNMOS), controllable silicon (SiliconControlledRectifier, SCR), diode etc.Wherein due to GGNMOS and integrated circuit CMOS technology well compatible, and to be widely adopted.Fig. 1 is the existing GGNMOS device semiconductor structure figure for esd protection circuit.Fig. 2 is the GGNMOS device equivalent circuit diagram for esd protection circuit corresponding with Fig. 1.As depicted in figs. 1 and 2, this GGNMOS device comprises P type substrate 100; Be positioned at the grid 101 on P type substrate 100 surface; Lay respectively at grid 101 both sides substrate is interior, doping type is N-type source electrode 102 and drain electrode 103.One is comprised by source electrode 102 and drain electrode 103 in above-mentioned GGNMOS device, and the parasitic NPN triode that substrate 100 is between the two formed.Wherein, drain 103 as collector electrode, source electrode 102 as emitter, substrate 100 as base stage.P type substrate 100, source electrode 102 and grid 101 are all connected to ground wire GND, and drain electrode 103 are connected to the input/output terminal (I/O) of power line VDD and chip circuit.Due to grid 101 and P type substrate 100 ground connection, GGNMOS device cannot open formation conducting channel all the time.When the current potential on power line VDD is positioned at normal operating state, GGNMOS device is closed, and parasitic NPN triode wherein also can not conducting; When causing transient potential too high when power line VDD is subject to ESD electrostatic pulse; GGNMOS device endoparasitism NPN triode generation current will be triggered; make conducting between power line VDD and ground wire GND; the instantaneous large-current that ESD electrostatic pulse produces will be flowed away by above-mentioned parasitic NPN triode rapidly, thus reaches the object that protection internal circuit is subject to ESD electrostatic impact.After ESD electrostatic pulse disappears, above-mentioned parasitic NPN triode is closed, and can not impact the normal work of protected internal circuit.
It should be noted that when GGNMOS is when instantaneously by large electric current, a large amount of heats can be produced and GGNMOS is burnt out, making it lose esd protection ability, therefore, how to extend the working life of GGNMOS, better protective circuit, become the problem needing to solve.
Summary of the invention
In view of this, the invention provides a kind of ESD protection circuit and preparation method thereof, the working life of ESD protective device can be extended.
Technical scheme of the present invention is achieved in that
The invention provides a kind of ESD protection circuit, comprise the grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor be positioned in Semiconductor substrate, the drain electrode of described ggnmos transistor connects the input/output terminal of chip circuit, source electrode and grid and the equal ground connection of Semiconductor substrate; This circuit also comprises and is positioned near described ggnmos transistor, for absorbing the amber ear note cooling element of the heat that described ggnmos transistor produces.
Described amber ear note cooling element is thermocouple, this thermocouple comprises N doped portion and P doped portion, and connect the metal of N doped portion and P doped portion, in one end be not connected with metal of N doped portion, there is the first contact electrode, in one end be not connected with metal of P doped portion, there is the second contact electrode.
Described amber ear note cooling element is in parallel with described ggnmos transistor, and described first contact electrode is connected with the drain electrode of ggnmos transistor, and described second contact electrode is connected to ground.
Described first contact electrode is connected with the drain electrode of ggnmos transistor, and described second contact electrode is connected with chip circuit.
Described ggnmos transistor is refer to ggnmos transistor in parallel more.
The metal of described connection N doped portion and P doped portion is copper or aluminium.
Present invention also offers a kind of manufacture method of ESD protection circuit, the method comprises:
There is provided a grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor, described ggnmos transistor at least comprises the grid being positioned at semiconductor substrate surface, grid both sides substrate is interior, doping type is N-type source electrode and drain electrode; While the described source electrode of formation and drain electrode, the redundant area in Semiconductor substrate forms N doped portion and the P doped portion of amber ear note cooling element;
Form intermetallic interconnection layer on ggnmos transistor surface, in described intermetallic interconnection layer, there is the connecting hole being filled with metal;
Form interlayer dielectric layer on the surface of described intermetallic interconnection layer, in described interlayer dielectric layer, there is the groove being filled with metal or connecting hole; While forming the groove or connecting hole being filled with metal, the connection N doped portion of amber ear note cooling element and the metal of P doped portion is formed with layer, the metal of described connection N doped portion and P doped portion and described be filled with metal groove or connecting hole between insulated by interlayer dielectric layer, and to be electrically connected by the N doped portion of connecting hole and amber ear note cooling element and P doped portion;
The drain electrode of described ggnmos transistor is connected the input/output terminal of chip circuit, source electrode and grid and the equal ground connection of Semiconductor substrate; By described amber ear note cooling element place in circuit.
The method of described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end be not connected with metal of N doped portion, described amber ear note cooling element is connected to ground by the second contact electrode in one end be not connected with metal of P doped portion.
The method of described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end be not connected with metal of N doped portion, described amber ear note cooling element is connected with chip circuit by the second contact electrode in one end be not connected with metal of P doped portion.
As can be seen from such scheme; ESD protection circuit of the present invention adds amber ear note cooling element on the basis of GGNMOS structure; this amber ear note cooling element is thermocouple, and this thermocouple comprises N doped portion and P doped portion, and connects the metal of N doped portion and P doped portion.Amber ear note cooling element is positioned near GGNMOS structure; when transient current is very large; also electric current is had by this amber ear note cooling element; the heat that GGNMOS structure produces can be led away by time; GGNMOS structure is unlikely to burn out; thus extend the working life of ESD protective device, reach object of the present invention.
Accompanying drawing explanation
Fig. 1 is the existing GGNMOS device semiconductor structure figure for esd protection circuit.
Fig. 2 is the GGNMOS device equivalent circuit diagram for esd protection circuit corresponding with Fig. 1.
Fig. 3 is the amber ear note cooling element schematic diagram formed according to peltier effect.
Fig. 4 is the equivalent circuit diagram of first embodiment of the invention ESD protection circuit.
Fig. 5 is ESD protection circuit semiconductor structure generalized section of the present invention.
Fig. 6 is first embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view.
Fig. 7 is the equivalent circuit diagram of second embodiment of the invention ESD protection circuit.
Fig. 8 is second embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
Core concept of the present invention is exactly in the esd protection circuit with ggnmos transistor, add amber ear note cooling element; amber ear note cooling element is positioned near ggnmos transistor, and amber ear note cooling element can reach the effect of cooling ggnmos transistor after passing into electric current.Simply introduce the application background of amber ear note cooling element below.
When electric current flow through connection and two kinds of different conductors under remaining on uniform temperature time, except Joule heat, also produce radiation or absorb heat.This effect is the phenomenon first found by J.C.A.Peltier in 1834, and is called peltier effect.According to peltier effect formed amber ear note cooling element schematic diagram as shown in Figure 3.This amber ear note cooling element comprises N doped portion 5 and P doped portion 6, and connect the metal 10 of N doped portion and P doped portion, in one end be not connected with metal of N doped portion, there is the first contact electrode 11, in one end be not connected with metal of P doped portion, there is the second contact electrode 12.When electric current flows to P from N; the temperature connecting the metal 10 of N doped portion and P doped portion declines; the temperature at the first contact electrode 11 and the second contact electrode 12 place rises; the metal 10 that the present invention utilizes temperature to decline just; cooling ggnmos transistor, makes ggnmos transistor when transient current is excessive, namely plays protective circuit effect; be unlikely to again heat too high and be burned, thus reach object of the present invention.
The equivalent circuit diagram of first embodiment of the invention ESD protection circuit as shown in Figure 4.Amber ear note cooling element 401 is in parallel with ggnmos transistor 402.Wherein, the drain electrode 1 of ggnmos transistor 402 connects the input/output terminal of chip circuit, source electrode 2 and grid 3 and Semiconductor substrate 4 all ground connection; The N doped portion of amber ear note cooling element 401 is connected to the drain electrode 1 of ggnmos transistor 402 by the first contact electrode (not shown), the P doped portion of amber ear note cooling element 401 is connected to ground by the second contact electrode (not shown).
The manufacture method of embodiment of the present invention ESD protection circuit; comprise the following steps; below in conjunction with the ESD protection circuit semiconductor structure generalized section of Fig. 5, and the ESD protection circuit semiconductor structure schematic top plan view of Fig. 6 is described in detail.
Step 41, provide a grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor, described ggnmos transistor at least comprises the grid 3 being positioned at Semiconductor substrate 4 surface, and in the substrate of grid 3 both sides, doping type is source electrode 2 and the drain electrode 1 of N-type; While the described source electrode 2 of formation and drain electrode 1, the redundant area in Semiconductor substrate forms N doped portion 5 and the P doped portion 6 of amber ear note cooling element;
Formation for ggnmos transistor does not repeat them here, and ggnmos transistor is arranged in active area, keeps apart each active area by shallow channel isolation area (STI).Semiconductor substrate 4 is P type substrate, can be monocrystalline silicon, polysilicon, carborundum or silicon Germanium compound etc.Because NMOS tube electronics is as majority carrier, so the source electrode of NMOS tube and drain electrode are N-type, inject N-type element boron fluoride (BF
2) or boron (B) etc.While Semiconductor substrate being carried out to ion implantation formation source-drain electrode, the position of function element is there is not at semiconductor substrate surface, i.e. redundant area, also the N doped portion 5 that N-type ion implantation forms amber ear note cooling element is carried out, carry out in another redundant area the P doped portion 6 that P type ion implantation forms amber ear note cooling element, the P type element of injection is phosphorus (P) or arsenic (As) etc.
Step 42, form intermetallic interconnection layer 7 on ggnmos transistor surface, there is in described intermetallic interconnection layer 7 connecting hole 8 being filled with metal;
In order to clearly demonstrate amber ear note cooling element of the present invention, merely illustrate the connecting hole 8 be electrically connected with the N doped portion 5 of amber ear note cooling element and P doped portion 6 in Fig. 5, the connecting hole of other and grid, source electrode and drain electrode UNICOM does not all illustrate.This step is the fundamental technology making metal interconnecting layer, has just made the connecting hole be electrically connected with the N doped portion 5 of amber ear note cooling element and P doped portion 6 simultaneously.
Step 43, the surface of described intermetallic interconnection layer 7 formed interlayer dielectric layer 9, there is in described interlayer dielectric layer 9 groove or connecting hole that are filled with metal; While forming the groove or connecting hole being filled with metal, the connection N doped portion 5 of amber ear note cooling element and the metal 10 of P doped portion 6 is formed with layer, the metal 10 of described connection N doped portion and P doped portion and described be filled with metal groove or connecting hole between insulated by interlayer dielectric layer 9, and to be electrically connected by the N doped portion 5 of connecting hole 8 and amber ear note cooling element and P doped portion 6.
This step is the fundamental technology making metal interconnecting layer, has just made the connection N doped portion 5 of amber ear note cooling element and the metal 10 of P doped portion 6 simultaneously.It should be noted that, metal 10 is formed with layer with the groove or connecting hole being filled with metal, metal 10 requires and is filled with between the groove of metal or connecting hole keeps apart, and metal 10 will be electrically connected with the connecting hole 8 of lower floor, can find out from the vertical view of Fig. 6.Above-mentioned connecting hole or the interior metal of filling of groove are copper or aluminium etc.
Step 44, the drain electrode 1 of described ggnmos transistor is connected the input/output terminal of chip circuit, source electrode 2 and grid 3 and Semiconductor substrate 4 all ground connection; By described amber ear note cooling element place in circuit; Wherein, the method of described amber ear note cooling element place in circuit is comprised: described amber ear note cooling element is connected with the drain electrode 1 of described ggnmos transistor by the first contact electrode 11 in one end be not connected with metal of N doped portion, described amber ear note cooling element is connected to ground by the second contact electrode 12 in one end be not connected with metal of P doped portion.
This embodiment specific works principle is as follows:
When ESD occurs, electric current flows through ggnmos transistor 402 and Po Er note cooling element 401 simultaneously, the connection N doped portion 5 of amber ear note cooling element 401 and metal 10 temperature of P doped portion 6 decline, because ggnmos transistor 402 and Po Er note cooling element 401 are apart from very near, the temperature declined passes to ggnmos transistor 402 by dielectric layer, the heat that the big current that ggnmos transistor 402 flows through when ESD occurs is produced is rapidly absorbed, and is unlikely to ggnmos transistor 402 to burn out.
In addition, in order to improve the resistance ESD ability of GGNMOS device, usually can adopt and refer to GGNMOS structure in parallel more, namely multiple GGNMOS is connected in parallel, but this how finger parallel-connection structure can cause non-uniform Trigger Problems: the dead resistance in the leakage path of middle NMOS is larger than the dead resistance in the NMOS leakage path of surrounding, when power line VDD producing electrostatic breakdown and causing current potential to raise, middle NMOS is always prior to other NMOS conductings, not only make above-mentionedly to refer to that the conducting homogeneity of GGNMOS structure in parallel is very poor more, and the heat that can produce due to the NMOS of centre is burned too greatly, make wholely to refer to that GGNMOS structure in parallel loses esd protection ability more.Therefore, amber ear note cooling element 401 of the present invention, its metal 10 connecting N doped portion 5 and P doped portion 6 also can around this GGNMOS structure referring to parallel connection more, and the heat that the NMOS in the middle of effectively absorbing produces, raising refers to the conducting homogeneity of GGNMOS structure in parallel more.
The equivalent circuit diagram of second embodiment of the invention ESD protection circuit as shown in Figure 7.Wherein, the drain electrode 1 of ggnmos transistor 402 connects the input/output terminal of chip circuit, source electrode 2 and grid 3 and Semiconductor substrate 4 all ground connection; The N doped portion of amber ear note cooling element 401 is connected to the drain electrode 1 of ggnmos transistor 402 by the first contact electrode (not shown), the P doped portion of amber ear note cooling element 401 is connected with chip circuit by the second contact electrode (not shown).
The manufacture method of ESD protection circuit in this embodiment, substantially identical with the first embodiment, when difference is amber ear note cooling element 401 place in circuit, P doped portion is connected with chip circuit by the second contact electrode 12.Second embodiment of the invention ESD protection circuit semiconductor structure schematic top plan view as shown in Figure 8.
This embodiment specific works principle is as follows:
When ESD occurs, electric current flows through ggnmos transistor 402, but unavoidably also having small area analysis flows through amber ear note cooling element 401, at this moment amber ear note cooling element 401 is started working, the connection N doped portion 5 of amber ear note cooling element 401 and metal 10 temperature of P doped portion 6 decline, because ggnmos transistor 402 and Po Er note cooling element 401 are apart from very near, the temperature declined passes to ggnmos transistor 402 by dielectric layer, the heat that the big current that ggnmos transistor 402 flows through when ESD occurs is produced is rapidly absorbed, ggnmos transistor 402 is unlikely to burn out.In like manner; also can apply in the protective circuit of this embodiment and refer to GGNMOS structure in parallel more; amber ear note cooling element 401; its metal 10 connecting N doped portion 5 and P doped portion 6 around this GGNMOS structure referring to parallel connection more; effective heat absorbing middle NMOS and produce, improves the conducting homogeneity referring to GGNMOS structure in parallel more.
Above-mentioned two embodiments list amber ear note cooling element and are connected to two modes in protective circuit; protection of the present invention is not limited to this; as long as amber ear note cooling element 401 can pass into electric current; and be positioned near ggnmos transistor; its metal 10 connecting N doped portion 5 and P doped portion 6, around this ggnmos transistor, effectively absorbs the heat of ggnmos transistor by producing during electric current.
By ESD protection circuit of the present invention; the principle that after utilizing amber ear note cooling element to pass into electric current, temperature declines; this amber ear note cooling element being arranged near ggnmos transistor, for absorbing the heat that ggnmos transistor produces, thus reaching object of the present invention.On the other hand, the embodiment of the present invention, when making ESD protection circuit, make use of the production process of existing technique, such as, while making source-drain electrode, make N doped portion and the P doped portion of amber ear note cooling element; While making metal interconnecting layer, make the connection N doped portion of amber ear note cooling element and the metal of P doped portion, make manufacture method be simple and easy to realize.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (3)
1. a manufacture method for ESD protection circuit, the method comprises:
There is provided a grounded-grid N-type metal-oxide semiconductor (MOS) ggnmos transistor, described ggnmos transistor at least comprises the grid being positioned at semiconductor substrate surface, grid both sides substrate is interior, doping type is N-type source electrode and drain electrode; While the described source electrode of formation and drain electrode, the redundant area in Semiconductor substrate forms N doped portion and the P doped portion of amber ear note cooling element;
Form intermetallic interconnection layer on ggnmos transistor surface, in described intermetallic interconnection layer, there is the connecting hole being filled with metal;
Form interlayer dielectric layer on the surface of described intermetallic interconnection layer, in described interlayer dielectric layer, there is the groove being filled with metal or connecting hole; While forming the groove or connecting hole being filled with metal, the connection N doped portion of amber ear note cooling element and the metal of P doped portion is formed with layer, the metal of described connection N doped portion and P doped portion and described be filled with metal groove or connecting hole between insulated by interlayer dielectric layer, and to be electrically connected by the N doped portion of connecting hole and amber ear note cooling element and P doped portion;
The drain electrode of described ggnmos transistor is connected the input/output terminal of chip circuit, source electrode and grid and the equal ground connection of Semiconductor substrate; By described amber ear note cooling element place in circuit.
2. the method for claim 1, is characterized in that, the method for described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end be not connected with metal of N doped portion, described amber ear note cooling element is connected to ground by the second contact electrode in one end be not connected with metal of P doped portion.
3. the method for claim 1, is characterized in that, the method for described amber ear note cooling element place in circuit is comprised:
Described amber ear note cooling element is connected with the drain electrode of described ggnmos transistor by the first contact electrode in one end be not connected with metal of N doped portion, described amber ear note cooling element is connected with chip circuit by the second contact electrode in one end be not connected with metal of P doped portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210530228.2A CN103872039B (en) | 2012-12-11 | 2012-12-11 | The manufacture method of ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210530228.2A CN103872039B (en) | 2012-12-11 | 2012-12-11 | The manufacture method of ESD protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103872039A CN103872039A (en) | 2014-06-18 |
| CN103872039B true CN103872039B (en) | 2016-04-06 |
Family
ID=50910416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210530228.2A Active CN103872039B (en) | 2012-12-11 | 2012-12-11 | The manufacture method of ESD protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103872039B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990331B (en) * | 2015-02-02 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD-protection structure and electronic device |
| CN110289246B (en) * | 2019-06-25 | 2021-08-06 | 清华大学 | Self-refrigeration method and device for interior of IGBT module |
| CN114265038B (en) * | 2021-11-22 | 2024-02-09 | 电子科技大学 | High-precision switch type phase shifting unit with temperature compensation effect |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378280A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Static discharge protective semiconductor device |
| CN1873978A (en) * | 2005-03-23 | 2006-12-06 | 英飞凌科技股份公司 | Electrostatic discharge protection process and device for the improvement of a semiconductor circuit |
| CN101834184A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube |
| CN101847644A (en) * | 2009-03-24 | 2010-09-29 | 索尼公司 | Semiconductor device |
| CN101866922A (en) * | 2010-05-12 | 2010-10-20 | 上海宏力半导体制造有限公司 | GGNMOS device used in ESD protective circuit |
| CN101971380A (en) * | 2008-09-03 | 2011-02-09 | 奥斯兰姆奥普托半导体有限责任公司 | Optoelectronic component |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288426B1 (en) * | 2000-02-28 | 2001-09-11 | International Business Machines Corp. | Thermal conductivity enhanced semiconductor structures and fabrication processes |
-
2012
- 2012-12-11 CN CN201210530228.2A patent/CN103872039B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378280A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Static discharge protective semiconductor device |
| CN1873978A (en) * | 2005-03-23 | 2006-12-06 | 英飞凌科技股份公司 | Electrostatic discharge protection process and device for the improvement of a semiconductor circuit |
| CN101971380A (en) * | 2008-09-03 | 2011-02-09 | 奥斯兰姆奥普托半导体有限责任公司 | Optoelectronic component |
| CN101847644A (en) * | 2009-03-24 | 2010-09-29 | 索尼公司 | Semiconductor device |
| CN101834184A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | Substrate-triggered GGNMOS (Grounded-Grid N-Metal-Oxide-Semiconductor) tube |
| CN101866922A (en) * | 2010-05-12 | 2010-10-20 | 上海宏力半导体制造有限公司 | GGNMOS device used in ESD protective circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103872039A (en) | 2014-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103035638B (en) | Improve adjustable ESD protective device | |
| CN102263104B (en) | Electrostatic discharge (ESD) protection device with metal oxide semiconductor (MOS) structure | |
| CN102544115B (en) | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) | |
| CN104716132B (en) | The thyristor and its circuit of a kind of low trigger voltage and high maintenance voltage | |
| CN101859763B (en) | Integrated circuit including ESD device | |
| CN103872039B (en) | The manufacture method of ESD protection circuit | |
| CN102832233B (en) | SCR (silicon controlled rectifier) type LDMOS ESD (lateral double diffusion metal-oxide-semiconductor device electrostatic discharge) device | |
| US8963202B2 (en) | Electrostatic discharge protection apparatus | |
| CN101866922B (en) | GGNMOS device used in ESD protective circuit | |
| CN204348725U (en) | The low capacitor transient stage voltage suppressor device of a kind of single channel | |
| CN105489503A (en) | Semiconductor structure, forming method thereof, and electrostatic protection circuit | |
| CN102544068B (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| CN202394973U (en) | ESD protective structure between SOI/CMOS integrated circuit power and ground | |
| US8937334B2 (en) | Triggerable bidirectional semiconductor device | |
| CN104051505A (en) | LDMOS ESD device | |
| Zhang et al. | Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp | |
| CN106158744A (en) | Electrostatic preventing structure and preparation method thereof, chip and preparation method thereof | |
| CN102364687A (en) | Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground | |
| CN104183593A (en) | Electrostatic discharge protection structure | |
| CN101866920B (en) | A kind of esd protection structure | |
| CN202888176U (en) | ESD device structure based on BCD technology | |
| CN102544066B (en) | Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes | |
| CN103887303B (en) | Signal IO protection device with reference to single supply and forming method thereof | |
| CN102544067B (en) | Bidirectional controllable silicon device based on assistant triggering of N-channel metal oxide semiconductor (NMOS) tubes | |
| US8941959B2 (en) | ESD protection apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |