CN101866922B - GGNMOS device used in ESD protective circuit - Google Patents
GGNMOS device used in ESD protective circuit Download PDFInfo
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- CN101866922B CN101866922B CN201010172659.7A CN201010172659A CN101866922B CN 101866922 B CN101866922 B CN 101866922B CN 201010172659 A CN201010172659 A CN 201010172659A CN 101866922 B CN101866922 B CN 101866922B
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- well region
- source area
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Abstract
The invention provides a GGNMOS device used in an ESD protective circuit. The device comprises a substrate and a P trap region positioned on the substrate, wherein a plurality of drain electrode regions are arranged in the P trap region; the surface of the P trap region and two sides of the drain electrode regions are provided with grid electrode regions; the P trap region and the other sides of the grid electrode regions are provided with source electrode regions; P type doped regions are arranged among the source electrode regions; and a position below the source electrode regions and close to the source electrode regions is provided with an N trap region. The GGNMOS device used in the ESD protective circuit not only can solve non-uniform triggering problems, but also can solve the problems of resistance reduction, trigger voltage raising and difficult leakage of electrostatic current in a leakage path.
Description
Technical field
The present invention relates to esd protection circuit, particularly relate to a kind of GGNMOS device for esd protection circuit.
Background technology
In IC chip manufacture and final application system, along with improving constantly of very lagre scale integrated circuit (VLSIC) technology, current CMOS integrated circuit has entered the sub-micro stage, the size of MOS device constantly reduces, gate oxide thickness is more and more thinner, its grid voltage endurance capability significantly declines, and static discharge (Electrostatic Discharge, ESD) becomes more and more significant to the harm of integrated circuit.According to statistics, 35% is had caused by ESD problem in the product of ic failure.Therefore, esd protection design is carried out to integrated circuit and also become particularly important.
Esd protection circuit is for chip circuit provides the discharge path of electrostatic induced current, is punctured by internal circuit to avoid electrostatic.Because electrostatic is generally from the external world, such as human body, machine etc., therefore esd protection circuit is usually around the bond pad (PAD) of chip.Export bond pad to be generally connected with drive circuit, be namely connected with the drain region of NMOS tube with large-sized PMOS, therefore this kind of device itself may be used for esd protection electric discharge, and generally in order to insure, output also adds esd protection circuit; And input bond pad and be generally connected on the gate regions of metal-oxide-semiconductor, therefore at the input of chip, must esd protection circuit be added.In addition, the power supply (Udd) and ground (Uss) port of chip also to add esd protection circuit, to ensure that ESD electric current can be discharged into Uss safely from Udd.
When using device to carry out esd protection to integrated circuit, conventional device is gate regions grounding NMOS pipe (GGNMOS), GDPMOS (gate regions connects the P type metal-oxide-semiconductor of VDD power supply) and SCR (controllable silicon) etc.Due to GGNMOS and integrated circuit CMOS technology well compatible, GGNMOS is widely used.
Fig. 1 is a kind of GGNMOS device for esd protection circuit in prior art; as shown in Figure 1; comprise: substrate 1a; be positioned at the P well region 2a on described substrate; the some drain region 7a be provided with in described P well region 2a; at the gate regions 6a that the surface of the both sides of described drain region 7a and described P well region 2a is provided with; the source area 4a be provided with in the opposite side and described P well region 2a of described gate regions 6a, is positioned at STI (shallow trench isolation from) 3a be provided with outside the described source area 4a at edge and the P type doped region 5a be positioned at outside STI.Described drain region 7a and ESD input 8a is electrical connected, described source area 4a and described gate regions 6a ground connection, described P type doped region 5a ground connection.Described drain region 7a and ESD input 8a is electrical connected, described source area 4a, described gate regions 6a and described P type doped region 5a ground connection.
When ESD comes interim, electric current flows into described drain region 7a by ESD input 8a, described electric current flows through described P type doped region 5a by described P well region 2a, then now produce voltage difference at described P well region 2a, when voltage difference exceedes threshold voltage, with regard to forming the state of NPN triode ON, (described source area 4a is equivalent to emitter region, described gate regions 6a is in base, described drain region 7a is in collector area), now electric current just flows into described gate regions 6a from described drain region 7a, finally flow through described source area 4a to flow out, release ESD, this avoid electrostatic damage circuit.
As can see from Figure 1, this GGNMOS structure adopts many fingers transistor, and the NMOS that its structure is equivalent to multiple single finger is connected in parallel, and adds the area of esd protection.But, this GGNMOS structure can cause non-uniform Trigger Problems: the drain region being positioned at middle single finger NMOS is larger than the distance to described P type doped region of single finger NMOS of surrounding apart from described P type doped region, dead resistance in the leakage path of middle single finger NMOS is larger than the dead resistance in the leakage path of single finger NMOS of surrounding, or due to technique out-of-flatness or resistance substrate not of uniform size, cause when the first conducting of the several finger NMOS of ESD stress certain or certain, cause electrostatic induced current can only release from this finger, other fingers perform practically no function; Even to flow through the current unevenness of each finger even for ESD, thus reduces the esd protection circuit performance of many fingers transistor.Even cause the damage of esd protection.
Fig. 2 is the another kind of GGNMOS device for esd protection in prior art; as shown in Figure 2; comprise: substrate 1b; be positioned at the P well region 2b on described substrate; the some drain region 7b be provided with in described P well region 2b; at the gate regions 6b that the surface of the both sides of described drain region 7b and described P well region 2b is provided with; the source area 4b be provided with in the opposite side and described P well region 2b of described gate regions 6b; P type doped region 5b between described source area, and be positioned at STI (shallow trench isolation from) 3b be provided with outside the described source area 4b at edge.Described drain region and ESD input are electrical connected, described source area and described gate regions ground connection, described P type doped region 5b ground connection.As we can see from the figure, same employing many fingers transistor arrangement, but this GGNMOS structure P doped region is inserted between the end of all source areas, make the bleeder resistance of the leakage path of each single finger NMOS identical, this structure can solve non-uniform Trigger Problems, but greatly reduce the length of the leakage path at P well region, reduce the dead resistance in leakage path, and then the voltage difference reduced in P well region, then only have that larger electrostatic current is fashionable just can reach threshold voltage, ability and then conducting, leak away electrostatic, therefore, this causes again the raising greatly of trigger voltage, the antileakaging problem of electrostatic induced current.
In sum, need to provide a kind of GGNMOS device for esd protection can solve non-uniform Trigger Problems, the problem that in leakage path, resistance reduces, trigger voltage raises can be solved again.
Summary of the invention
The present invention will solve the non-uniform Trigger Problems for the GGNMOS device of esd protection in prior art, and solves resistance reduction in leakage path, trigger voltage rising, the antileakaging problem of electrostatic induced current.
For solving the problem; the invention provides a kind of GGNMOS device for esd protection; comprise: substrate; be positioned at the P well region on described substrate, the some drain regions be provided with in described P well region, in the gate regions that the both sides of described drain region and the surface of described P well region are provided with; the source area be provided with in opposite side in described gate regions and described P well region; the P type doped region be provided with between described source area, in the below of described source area, the N well region that adjacent described source area place is provided with.
Further, described drain region and ESD input are electrical connected, described source area, described gate regions ground connection and described P type doped region ground connection.
Further, in described GGNMOS device edge, described N trap, also sti structure is provided with.
Further, the doping content of described P well region is 10
12/ cm
2~ 10
13/ cm
2.
Further, the doping content of described N well region is 10
12/ cm
2~ 10
13/ cm
2.
Further, the concentration of described P type doped region is 10
12/ cm
2~ 10
13/ cm
2.
Preferably, the degree of depth of described N well region equals the degree of depth of described source area.
Preferably, the width of described N well region equals the width of described source area.
Further, the degree of depth of described P well region equals described N well region and source area degree of depth sum.
Preferably, the width of described P type doped region is the minimum widith meeting technological requirement.
Accompanying drawing explanation
Fig. 1 is a kind of GGNMOS device for esd protection circuit in prior art.
Fig. 2 is the another kind of GGNMOS device for esd protection in prior art.
Fig. 3 is a kind of GGNMOS device for esd protection in the present invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, the content novel to the present invention is described further.Certain the present invention is not limited to this specific embodiment, common in this area and say that the general replacement known by personnel is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Central idea of the present invention is, between described source area, arrange P type doped region can solve consistency problem, simultaneously immediately below described source area, the position of adjacent source area arranges N well region, improve the resistance in leakage path, thus solve the problem of trigger voltage rising.
The present invention proposes a kind of GGNMOS device for esd protection; comprise: substrate 1; be positioned at the P well region 2 on described substrate 1; the some drain regions 7 be provided with in described P well region 2; in the gate regions 6 that the both sides of described drain region 7 and the surface of described P well region 2 are provided with, the source area 4 be provided with in the opposite side in described gate regions 6 and described P well region 2, the P type doped region 5 be provided with between described source area 4; in the below of described source area 4, the N well region 9 that adjacent described source area 4 place is provided with.
Further, described drain region 7 is electrical connected with ESD input 8, described source area 4, described gate regions 6 ground connection and described P type doped region 5 ground connection.
In the present embodiment, described P well region 1 is boron doping, and doping content is 10
12/ cm
2~ 10
13/ cm
2; Described N well region 9 is phosphorus doping, and doping content is 10
12/ cm
2~ 10
13/ cm
2, described P type doped region 5 is boron doping, and doping content is 10
12/ cm
2~ 10
13/ cm
2.Adopt above-mentioned doping content, meet technological requirement, effectively can improve the dead resistance of leakage path.
Preferably, the degree of depth of described N well region 9 equals the degree of depth of described source area 4.
Preferably, the width of described N well region 9 equals the width of described source area 4.
Further, the degree of depth of described P well region 1 equals described N well region 9 and described source area 4 degree of depth sum.
Preferably, the width of described P type doped region 5 is the minimum widith meeting technological requirement.The width of above-mentioned doped region and the degree of depth are when meeting GGNMOS performance, are convenient to manufacture technics.
Further.The doping content having source area of described GGNMOS device, doping area and doping thickness change with technique, requirement on devices, and other doped regions all change with requirement on devices, are not construed as limiting in an embodiment.
In sum, when ESD comes interim, electric current flows into described drain region 7 by ESD input 8, described electric current flows through described P type doped region 5 by described P well region 2, owing to having dead resistance in described P well region 2, then flow through electric current and produce voltage difference in described P well region 2, when voltage difference exceedes threshold voltage, with regard to forming the state of NPN triode ON, (described source area 4 is equivalent to emitter region, described gate regions 6 is in base, described drain region 7 is in collector area), now electric current just flows into described gate regions from described drain region, finally flow through described source area 4 to flow out, release electrostatic, this avoid electrostatic damage circuit.In the utility model, the described GGNMOS device for esd protection has many fingers NMOS structure, its structure is connected in parallel with regard to the NMOS being equivalent to multiple single finger, P type doped region 5 is set between described source area 4, make the leakage path length of each single finger NMOS identical, and then can consistency problem be solved; Simultaneously immediately below described source area 4, the position of adjacent source area 4 arranges N well region 9, make the leakage of electric current walk around described N well region 9 from needs drain region 7 and flow into P type doped region 5, which increase the length of leakage path, improve the parasitic resistance values of leakage path, and then improve voltage difference, thus relatively little electrostatic can make described GGNMOS conducting, discharge electrostatic, thus solve trigger voltage rising, the antileakaging problem of electrostatic.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (8)
1. the GGNMOS device for esd protection, it is characterized in that, comprise: substrate, be positioned at the P well region on described substrate, the some drain regions be provided with in described P well region, in the gate regions that the both sides of described P well region surface, described drain region are provided with, in described P well region, the source area that is provided with of the opposite side of described gate regions, the P type doped region be provided with between described source area, at the N well region that the below of described source area, adjacent described source area are provided with; Wherein, described drain region and ESD input are electrical connected, described source area, described gate regions and described P type doped region ground connection.
2., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, in described GGNMOS device edge, described N trap, be also provided with sti structure.
3., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the doping content of described P well region is 10
12/ cm
2~ 10
13/ cm
2.
4., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the doping content of described N well region is 10
12/ cm
2~ 10
13/ cm
2.
5., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the concentration of described P type doped region is 10
12/ cm
2~ 10
13/ cm
2.
6., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the degree of depth of described N well region equals the degree of depth of described source area.
7., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the width of described N well region equals the width of described source area.
8., as claimed in claim 1 for the GGNMOS device of esd protection, it is characterized in that, the degree of depth of described P well region equals described N well region and described source area degree of depth sum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172659.7A CN101866922B (en) | 2010-05-12 | 2010-05-12 | GGNMOS device used in ESD protective circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172659.7A CN101866922B (en) | 2010-05-12 | 2010-05-12 | GGNMOS device used in ESD protective circuit |
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| Publication Number | Publication Date |
|---|---|
| CN101866922A CN101866922A (en) | 2010-10-20 |
| CN101866922B true CN101866922B (en) | 2015-01-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094271B (en) * | 2011-11-01 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protection circuit |
| CN102646601B (en) * | 2012-04-19 | 2016-09-28 | 北京燕东微电子有限公司 | A kind of semiconductor structure and manufacture method thereof |
| CN103872039B (en) * | 2012-12-11 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of ESD protection circuit |
| CN104916631B (en) * | 2014-03-11 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105489503B (en) * | 2016-01-27 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof, electrostatic discharge protective circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983588A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Anti-electrostatic protecting structure by NMOS |
| CN101283452A (en) * | 2005-10-06 | 2008-10-08 | Nxp股份有限公司 | Electrostatic discharge protection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7420793B2 (en) * | 2006-01-12 | 2008-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit system for protecting thin dielectric devices from ESD induced damages |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101283452A (en) * | 2005-10-06 | 2008-10-08 | Nxp股份有限公司 | Electrostatic discharge protection device |
| CN1983588A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Anti-electrostatic protecting structure by NMOS |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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