CN105489503B - Semiconductor structure and forming method thereof, electrostatic discharge protective circuit - Google Patents

Semiconductor structure and forming method thereof, electrostatic discharge protective circuit Download PDF

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Publication number
CN105489503B
CN105489503B CN201610056876.7A CN201610056876A CN105489503B CN 105489503 B CN105489503 B CN 105489503B CN 201610056876 A CN201610056876 A CN 201610056876A CN 105489503 B CN105489503 B CN 105489503B
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China
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well region
region
grid
substrate
gate
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CN201610056876.7A
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Chinese (zh)
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CN105489503A (en
Inventor
胡剑
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上海华虹宏力半导体制造有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

A kind of semiconductor structure and forming method thereof, electrostatic discharge protective circuit, the forming method include:Offer includes the substrate of device region;Several well regions being isolated by substrate are formed in device region substrate;Gate structure is formed on well region surface;Source area is formed in the well region of gate structure side, forms drain region in the substrate of the other side, drain region is across adjacent well region and neighboring gate structures common source polar region and drain region.The present invention is isolated by substrate between the well region by forming several well regions in device region substrate, part drain region is made to be located in well region, part drain region is located in substrate.Since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, the smaller parasitic capacitance of Doped ions concentration is smaller, and the Doped ions concentration of substrate is less than the Doped ions concentration of well region, therefore the parasitic capacitance of GGNMOS can be made to reduce, the problem of so as to reduce input and output delay, and then promote the operating rate of chip.

Description

Semiconductor structure and forming method thereof, electrostatic discharge protective circuit

Technical field

The present invention relates to semiconductor applications more particularly to a kind of semiconductor structure and forming method thereof, electrostatic discharge protective circuits.

Background technology

The utilization of semiconductor chip is more and more extensive, cause semiconductor chip by electrostatic damage factor also increasingly It is more.In the design of existing chip, frequently with electrostatic discharge protective circuit (ESD, Electrostatic Discharge) to reduce core Piece damages.The design of existing ESD protection circuit and application include:N type field effect transistor (the Gate of grid ground connection Grounded NMOS, abbreviation GGNMOS) protect circuit, silicon-controlled (Silicon Controlled Rectifier, abbreviation SCR) protect circuit, horizontal proliferation field-effect transistor (Laterally Diffused MOS, abbreviation LDMOS) protection circuit, Bipolar junction transistor (Bipolar Junction Transistor, abbreviation BJT) protects circuit etc..Wherein, due to GGNMOS There is preferable compatibility with integrated circuit technology and be widely used.

But with the development trend of super large-scale integration, integrated circuit feature size persistently reduces, the prior art The performance of GGNMOS is to be improved.

Invention content

Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, electrostatic discharge protective circuit, optimization The performance of GGNMOS.

To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, include the following steps:Lining is provided Bottom, the substrate include device region;Form several well regions in the device region substrate, the well region include the first well region, Second well region, and one or several third well regions between first well region and the second well region, it is described several It is isolated by the substrate between well region;Gate structure is formed on the well region surface, the gate structure includes being located at The first grid structure on first well region surface is located at the second grid structure on second well region surface, is located at described the Two third gate structures on three well region surfaces;Form source area in the well region, the source area includes being located at described the First source area of one gate structure far from third gate structure side is located at the second grid structure far from described the Second source area of three gate structure sides, and in the same third well region and positioned at described two third gate structures it Between third source area;Substrate between the first grid structure or second grid structure and adjacent third gate structure In, alternatively, forming drain region in substrate between the adjacent third gate structure of several third well regions, the drain region includes The first drain region in substrate between the first grid structure and adjacent third gate structure, first drain region Across first well region and adjacent third well region, between the second grid structure and adjacent third gate structure The second drain region in substrate, second drain region is across second well region and adjacent third well region.

Optionally, the quantity of the third well region is several, and in the step of forming the drain region, the drain region is also Include the third drain region between adjacent third well region in substrate, the third drain region is across the adjacent third trap Area.

Optionally, before forming the well region, further include:Formed in the substrate the first isolation structure and second every From structure;In the step of forming first well region and the second well region, the first well region for surrounding first isolation structure is formed, Form the second well region for surrounding second isolation structure;In the step of forming the source area, in first isolation structure First source area is formed in the first well region between first grid structure, in second isolation structure and second grid Second source area is formed in the second well region between structure.

Optionally, after at the well region, the first isolation structure and the second isolation structure, the forming method further includes: The first body contact zone is formed far from first grid structure side in first isolation structure, and part first body connects It touches area to be located in first well region, forming the second body far from second grid structure side in second isolation structure connects Area is touched, and part second body contact zone is located in second well region.

Optionally, the semiconductor structure is that grid are grounded n type field effect transistor, is used for electrostatic protection;The well region, The type of body contact region and the second body contact zone injection ion is p-type, the type of the drain region and source area injection ion For N-type.

Correspondingly, the present invention also provides a kind of semiconductor structures, including:Substrate, the substrate include device region;It is formed in Several well regions in substrate, several described well regions include the first well region, the second well region positioned at the device region, Yi Jiwei One or several third well regions between first well region and the second well region, by described between several described well regions Substrate is isolated;It is formed in the gate structure on the well region surface, the gate structure includes being located at the first well region table The first grid structure in face is located at the second grid structure on second well region surface, is located at the two of third well region surface A third gate structure;Source area in the well region, the source area include separate positioned at the first grid structure First source area of third gate structure side is located at the second grid structure far from third gate structure side The second source area, and the third source area in same third well region and between the third gate structure;Position Between the first grid structure or second grid structure and adjacent third gate structure, alternatively, being located at several third well regions Adjacent third gate structure between drain region in substrate, the drain region includes positioned at the first grid structure and adjacent The first drain region in substrate between third gate structure, first drain region is across first well region and adjacent Three well regions, the second drain region in substrate between the second grid structure and adjacent third gate structure, described Two drain regions are across second well region and adjacent third well region.

Optionally, the semiconductor structure further includes the first isolation structure being located in first well region, and is located at The second isolation structure in second well region;First isolation structure is located at first source area far from the first grid In first well region of pole structure side, second isolation structure is located at second source area far from the second grid structure In second well region of side.

Optionally, the semiconductor structure further includes:Positioned at first isolation structure far from the first grid structure A part for first body contact zone of side, first body contact zone is located in first well region;Positioned at described second every From second body contact zone of the structure far from second grid structure side, a part for second body contact zone is positioned at described In second well region.

Optionally, the semiconductor structure is that grid are grounded n type field effect transistor, is used for electrostatic protection;The well region, The type of the Doped ions of body contact region and the second body contact zone is p-type, the class of the drain region and source area Doped ions Type is N-type.

Correspondingly, the present invention also provides a kind of electrostatic discharge protective circuits, including:Electrostatic input terminal;Ground terminal;It is of the present invention Semiconductor structure, the substrate, source area and gate structure are connected to ground terminal, the drain region and the electrical phase of electrostatic input terminal Even.

Compared with prior art, technical scheme of the present invention has the following advantages:

The present invention is carried out between several described well regions by substrate by forming several well regions in device region substrate Isolation makes drain region across adjacent well region and in the well region, and part drain region is located in the well region, and part drains Area is located in the substrate.Since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, Doped ions concentration is smaller Parasitic capacitance is smaller, and the Doped ions concentration of the substrate is less than the Doped ions concentration of the well region, therefore can make The parasitic capacitance of GGNMOS reduces, and so as to reduce the problem of input and output are delayed, and then promotes the operating rate of chip.

Description of the drawings

Fig. 1 is the structural schematic diagram of one embodiment of prior art semiconductor structure;

Fig. 2 to Fig. 5 is the corresponding structural schematic diagram of one embodiment of forming method of semiconductor structure of the present invention;

Fig. 6 is the structural schematic diagram of one embodiment of electrostatic discharge protective circuit of the present invention.

Specific implementation mode

By background technology it is found that the performance of prior art GGNMOS is to be improved.Its reason is analyzed to be:

As shown in Figure 1, the structure of mono- embodiments of GGNMOS includes:Substrate 100;P type trap zone in the substrate 100 110, the isolation structure 150 being located in the P type trap zone 110 is multiple on the substrate 100 between isolation structure 150 Gate structure, the N-doped zone between gate structure or between gate structure and isolation structure 150, the N-doped zone In the P type trap zone 110.

Specifically, the multiple gate structure include first grid structure 121 between being sequentially located at isolation structure 150, Second grid structure 122, third gate structure 123 and the 4th gate structure 124.First grid structure 121 and second grid knot N-doped zone between structure 122, between third gate structure 123 and the 4th gate structure 124 is common drain area 130, the first grid Between pole structure 121 and isolation structure 150, between second grid structure 122 and third gate structure 123, the 4th gate structure N-doped zone between 124 and isolation structure 150 is source area 140.

The common drain area 130 is electrical connected with the ESD input terminals 170, the source area 140 and the gate structure Ground connection.

GGNMOS includes by the P between source area 140, common drain area 130 and the source area 140 and drain region 130 The parasitic NPN triode that type well region 110 is constituted.When ESD input terminals 170 are by ESD electrostatic pulses, the wink in common drain area 130 When current potential it is excessively high and trigger GGNMOS endoparasitism NPN triodes conducting, electric current is flowed into described total by the ESD input terminals 170 Drain region 130, and the source area 140 is flowed by the common drain area 130, ESD is discharged, to realize the effect of ESD protections.

Between first grid structure 121 and second grid structure 122, third gate structure 123 and the 4th gate structure 124 A common drain area 130 is shared, multiple NMOS is equivalent to and is connected in parallel, to improve the ability of ESD protections.However, as altogether Area with the common drain area 130 in area is larger, therefore, the parasitism electricity between the common drain area 130 and the well region 110 Appearance is corresponding also larger, to increase the delay of input and output, thereby reduces the operating rate of chip.

In order to solve the technical problem, the present invention provides a kind of manufacturing method of flash memory structure, including:Substrate is provided, The substrate includes device region;Several well regions are formed in the device region substrate, the well region includes being located at the device First well region, second well region in area, and one or several third traps between first well region and the second well region Area is isolated by the substrate between several described well regions;Gate structure, the grid are formed on the well region surface Structure includes the first grid structure positioned at first well region surface, is located at the second grid knot on second well region surface Structure is located at two third gate structures on third well region surface;Source area, the source area packet are formed in the well region It includes and is located at first source area of the first grid structure far from third gate structure side, be located at the second grid knot Second source area of the structure far from third gate structure side, and in same third well region and it is located at the third grid Third source area between the structure of pole;Between the first grid structure or second grid structure and adjacent third gate structure Substrate in, alternatively, forming drain region, the drain electrode in substrate between the adjacent third gate structure of several third well regions Area includes the first drain region in the substrate between the first grid structure and adjacent third gate structure, and described first Drain region is located at the second grid structure and adjacent third gate structure across first well region and adjacent third well region Between substrate in the second drain region, second drain region is across second well region and adjacent third well region.

The present invention is carried out between several described well regions by substrate by forming several well regions in device region substrate Isolation makes drain region across adjacent well region and in the well region, and part drain region is located in the well region, and part drains Area is located in the substrate.Since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, Doped ions concentration is smaller Parasitic capacitance is smaller, and the Doped ions concentration of the substrate is less than the Doped ions concentration of the well region, therefore can make The parasitic capacitance of GGNMOS reduces, and so as to reduce the problem of input and output are delayed, and then promotes the operating rate of chip.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 2 to Fig. 5 is the corresponding structural schematic diagram of one embodiment of forming method of semiconductor structure of the present invention.

With reference to figure 2, substrate 200 is provided, the substrate 200 includes device region I.

In the present embodiment, I substrate 200 of the device region be used to form grid ground connection n type field effect transistor (GGNMOS, Gate Grounded NMOS), the substrate 200 is P type substrate.Wherein, the GGNMOS for static discharge (ESD, Electrostatic Discharge) protection.

The substrate 200 can be silicon substrate, germanium substrate, silicon carbide substrates or germanium silicon substrate.In the present embodiment, described Substrate 200 is monocrystalline substrate.

It should be noted that the substrate 200 is the intrinsic semiconductor undoped with ion;Alternatively, the substrate 200 is mixed Heteroion concentration is relatively low.

It should also be noted that, the substrate further includes positioned at the bonding pad II of I both sides of the device region.The bonding pad II by the substrate 200 when subsequent metal is interconnected for being connected to ground wire GND.

With reference to figure 3, form several well regions in I substrate 200 of the device region, the well region include the first well region 221, Second well region 222, and one or several third well regions between first well region, 221 and second well region 222 223, it is isolated by the substrate 200 between several described well regions.

I substrate 200 of the device region is used to form GGNMOS, for ESD protections, the well region and subsequently in the well region The adjacent source regions and drain region that both sides are formed constitute parasitic NPN, and for realizing the function of Electro-static Driven Comb, the well region is suitable In the base area of NPN triode.

Correspondingly, the well region is P type trap zone, and first well region 221, the second well region 222 and third well region 223 are mixed The type of heteroion is identical with concentration.Specifically, the Doped ions can be B ions or BF ions, the dosage of Doped ions For 1E12 to 1E13 atom per square centimeters.

In the present embodiment, the quantity of the third well region 223 is one.

In other embodiments, the quantity of the third well region is random natural number n, and n >=2.

It should be noted that before forming the well region, further include:The first isolation junction is formed in the substrate 200 Structure 211 and the second isolation structure 212.The step of forming several well regions include:It is formed and surrounds the of first isolation structure 211 One well region 221 forms the second well region 222 for surrounding second isolation structure 212.

Specifically, first isolation structure 211 is located in first well region 221, second isolation structure 212 In in second well region 222.

With reference to figure 4, gate structure is formed on the well region surface, the gate structure includes being located at first well region The first grid structure 231 on 221 surfaces is located at the second grid structure 232 on 222 surface of the second well region, is located at described the Two third gate structures 233 on three well regions, 223 surface.

In the present embodiment, gate structure of the gate structure as GGNMOS.

It should be noted that it is smaller due to only relying on the electrostatic protection ability that single GGNMOS is played, it is formed multiple Gate structure and using adjacent transistor share with source region or drain region by the way of, to realize the parallel connection of transistor, in turn Increase the area of ESD protections.

In the present embodiment, the quantity of the third well region 223 is one, correspondingly, the number of the third gate structure 233 Amount is two.In other embodiments, the quantity of the third well region is random natural number n, and n >=2, correspondingly, described the The quantity of three gate structures is 2n.

In the present embodiment, the material of the gate structure is polysilicon.

It should be noted that the first grid structure 231 is located at first isolation structure 211 close to adjacent third grid 221 surface of the first well region of 233 side of pole structure, it is close that the second grid structure 232 is located at second isolation structure 212 222 surface of the second well region of adjacent 233 side of third gate structure, in order to subsequently in the well region of the gate structure side Source area is formed, drain region is formed between the neighboring gate structures of different well regions.

With reference to figure 5, source area is formed in the well region, the source area includes being located at the first grid structure 231 The first source area 241 far from 233 side of third gate structure is located at the second grid structure 232 far from described the Second source area 242 of three gate structures, 233 side, and in same third well region 223 and it is located at described two thirds Third source area 243 between gate structure 233.

The NPN tri- of the well region, source area and the drain region composition parasitism adjacent with the source area being subsequently formed Pole pipe, for realizing the function of Electro-static Driven Comb.The source area is equivalent to the emitter region of NPN triode.

It should be noted that the first isolation structure 211 is formed in first well region 221, in second well region 222 The second isolation structure 212 is formed with, in the present embodiment, between first isolation structure 211 and first grid structure 231 First source area 241 is formed in first well region 221, between second isolation structure 212 and second grid structure 232 The second well region 222 in form second source area 242.

In the present embodiment, the semiconductor structure is GGNMOS, correspondingly, first source area 241, the second source area 242 and the Doped ions type of third source area 243 be N-type ion, and first source area 241,242 and of the second source area The type of 243 Doped ions of third source area is identical with concentration.Specifically, the Doped ions can be P ion, As ions or The dosage of Sb ions, Doped ions is 1E12 to 1E13 atom per square centimeters.

With continued reference to Fig. 5, in the first grid structure 231 or second grid structure 232 and adjacent third gate structure In substrate 200 between 233, alternatively, in substrate 200 between the adjacent third gate structure 233 of several third well regions 223 Drain region is formed, the drain region includes the lining between the first grid structure 231 and adjacent third gate structure 233 The first drain region 251 in bottom 200, first drain region 251 is across first well region 221 and adjacent third well region 223, the second drain region in substrate 200 between the second grid structure 232 and adjacent third gate structure 233 252, second drain region 252 is across second well region 222 and adjacent third well region 233.

In the present embodiment, the quantity of the third well region 223 is one, and the drain region includes 251 He of the first drain region Second drain region 252.In other embodiments, the quantity of the third well region is random natural number n, and n >=2, correspondingly, shape In the step of the drain region, the drain region further includes the third drain region in substrate between adjacent third well region, The third drain region is across the adjacent third well region.

Well region between the adjacent source area and drain region and the source area and drain region constitutes parasitic NPN tri- Pole pipe, for realizing the function of Electro-static Driven Comb.The drain region is equivalent to the collector area of NPN triode.For example, described first Source area 241, the first well region 221 and the first drain region 251 constitute the first NPN triode.

It should be noted that the drain region is the common drain area of adjacent NPN triode.

In the present embodiment, the semiconductor structure is GGNMOS, correspondingly, first drain region 251 and second drains The Doped ions type in area 252 is N-type ion, and the type of 251 and second drain region of the first drain region, 252 Doped ions It is identical with concentration.Specifically, the Doped ions can be P ion, As ions or Sb ions, and the dosage of Doped ions is 1E12 To 1E13 atom per square centimeters.

It should be noted that the drain region is formed with the source area in the ion doping technique with along with.At other In embodiment, the drain region and source area can also be respectively formed in different ions doping process.

In the present embodiment, is formed after the well region, the first isolation structure 211 and the second isolation structure 212, further include: In first isolation structure 211 the first body contact zone 261, and part institute are formed far from 231 side of first grid structure It states the first body contact zone 261 to be located in first well region 221, in second isolation structure 212 far from the second grid 232 side of structure forms the second body contact zone 262, and part second body contact zone 262 is located at second well region 222 It is interior.Wherein, first body contact zone 261 is formed with second body contact zone 262 in the ion doping technique with along with.

First body contact zone, 261 and second body contact zone 262 is used for the substrate 200 when subsequent metal is interconnected It is connected to ground wire GND, first body contact zone, 261 and second doping type of body contact zone 262 and mixing for the substrate 200 Miscellany type is identical, and doping concentration is higher than the substrate 200, to reduce contact resistance.Specifically, first body contact zone 261 and 262 Doped ions of the second body contact zone type be p-type ion, the p-type ion can be B ions or BF ions, mix The dosage of heteroion is 1E12 to 1E13 atom per square centimeters.

It should be noted that in the present embodiment, it is initially formed the drain region and source area, re-forms the first body contact Area 261 and the second body contact zone 262.In other embodiments, it can also be initially formed the first body contact zone and the second body contact zone, Re-form drain region and source area.

The present invention is passed through described by forming several well regions in device region substrate 200 between several described well regions Substrate 200 is isolated, and makes common drain area across adjacent well region, and part drain region is located in the well region, part drain region In the substrate 200.Since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, Doped ions concentration is smaller Parasitic capacitance is smaller, and the Doped ions concentration of substrate 200 described in the present embodiment is less than the Doped ions concentration of the well region, because This compared with prior art, the parasitic capacitance of GGNMOS of the present invention reduces, the problem of so as to reduce input and output delay, into And promote the operating rate of chip.

Correspondingly, the embodiment of the present invention also provides a kind of semiconductor structure, with continued reference to Fig. 5, shows implementation of the present invention The schematic diagram of example semiconductor structure.The semiconductor structure includes:

Substrate 200, the substrate include device region I;

Several well regions being formed in substrate 200, several described well regions include the first trap positioned at the device region I Area 221, the second well region 222, and one or several thirds between first well region, 221 and second well region 222 Well region 223 is isolated by the substrate 200 between several described well regions;

It is formed in the gate structure on the well region surface, the gate structure includes being located at 221 surface of the first well region First grid structure 231, be located at 222 surface of the second well region second grid structure 232, and be located at the third trap Two third gate structures 233 on 223 surface of area;

Source area in the well region, the source area include being located at the first grid structure 231 far from described First source area 241 of 233 side of third gate structure is located at the second grid structure 232 far from the third grid knot Second source area 242 of 233 side of structure, and positioned at same third well region 223 and it is located at described two third gate structures 233 Between third source area 243;

Between the first grid structure 231 or second grid structure 232 and adjacent third gate structure 233, or Person, the drain region between the adjacent third gate structure 233 of several third well regions 223 in substrate 200, the drain region packet The first drain region 251 in the substrate 200 between the first grid structure 231 and adjacent third gate structure 233 is included, First drain region 251 is located at the second grid structure across first well region 221 and adjacent third well region 223 The second drain region 252 in substrate between 232 and adjacent third gate structure 233, second drain region 252 is across described Second well region 222 and adjacent third well region 223.

In the present embodiment, the part surface of the drain region is in contact with the well region, part surface and the substrate 200 It is in contact, since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, the smaller parasitic capacitance of Doped ions concentration is got over Small, the Doped ions concentration of substrate 200 described in the present embodiment is less than the Doped ions concentration of the well region, therefore, and existing Technology is compared, and the parasitic capacitance of GGNMOS of the present invention reduces, and so as to reduce the problem of input and output are delayed, and then promotes core The operating rate of piece.

In the present embodiment, the quantity of the third well region 223 is one, and the quantity of the third gate structure 233 is two It is a.

In other embodiments, the quantity of the third well region is random natural number n, and n >=2.Correspondingly, the third The quantity of gate structure 233 is 2n, and the drain region further includes the third drain electrode in substrate between adjacent third well region Area's (not shown), the third drain region is across the adjacent third well region.

In the present embodiment, the semiconductor structure further includes the first isolation structure being located in first well region 221 211, and the second isolation structure 212 in second well region 222;First isolation structure 211 is located at described the In the first well region 221 of the source region 241 far from 231 side of first grid structure, second isolation structure 212 is located at In the second well region 222 of second source area 242 far from 232 side of second grid structure.

It should be noted that the semiconductor structure further includes:Positioned at first isolation structure 211 far from described first A part for first body contact zone 261 of 231 side of gate structure, first body contact zone 261 is located at first well region In 221;Positioned at second body contact zone 262 of second isolation structure 212 far from 232 side of second grid structure, institute The part for stating the second body contact zone 262 is located in second well region 222.

In the present embodiment, the substrate 200 further includes positioned at the bonding pad II of I both sides of the device region.First body A part for contact zone 261 is also located in the bonding pad II, and a part for second body contact zone 262 is also located at the company It connects in area II.

First body contact zone, 261 and second body contact zone 262 is used to the substrate 200 being connected to ground wire GND, institute The doping type for stating the first body contact zone 261 and the second body contact zone 262 is identical as the doping type of the substrate 200, and mixes Miscellaneous concentration is higher than the substrate 200, to reduce contact resistance.

In the present embodiment, the semiconductor structure is that grid are grounded n type field effect transistor (GGNMOS, Gate Grounded NMOS), ESD is used to protect.Well region between the adjacent source area and drain region and the source area and drain region is constituted NPN triode, for realizing the function of Electro-static Driven Comb, the drain region is equivalent to the collector area of NPN triode, the source electrode Area is equivalent to the emitter region of NPN triode, and the well region is equivalent to the base area of NPN triode.For example, first source area 241, the first well region 221 and the first drain region 251 constitute the first NPN triode.

Correspondingly, the well region, the first body contact zone 261 and the second body contact zone 262 Doped ions type be P The type of type, the drain region and source area Doped ions is N-type.

Specifically, the Doped ions of first well region 221, the second well region 222 and third well region 223 can be B ions Or BF ions, the dosage of Doped ions is 1E12 to 1E13 atom per square centimeters;First source area 241, the second source electrode The Doped ions of area 242 and third source area 243 can be P ion, As ions or Sb ions, and the dosage of Doped ions is 1E12 To 1E13 atom per square centimeters;The Doped ions of first drain region, 251 and second drain region 252 can be P ion, As The dosage of ion or Sb ions, Doped ions is 1E12 to 1E13 atom per square centimeters.

With reference to figure 6, the embodiment of the present invention also provides a kind of electrostatic discharge protective circuit, including:

Electrostatic input terminal 380;

Ground terminal (not shown);

Semiconductor structure provided by the invention, the substrate 200, source area and gate structure are connected to ground terminal, the leakage Polar region is electrical connected with electrostatic input terminal 380.

In the present embodiment, the semiconductor structure is that grid are grounded n type field effect transistor (GGNMOS, Gate Grounded NMOS), the explanation of an embodiment is specifically referred to, details are not described herein.

In the present embodiment, the electrostatic input terminal 380 realizes electrical phase by contact hole plug 370 and the drain region Even.Specifically, the material of the contact hole plug 370 is tungsten.

In the present embodiment, the part surface of the drain regions GGNMOS is in contact with the well region, part surface with it is described Substrate 200 (as shown in Figure 5) is in contact, since the parasitic capacitance of GGNMOS is influenced by Doped ions concentration, Doped ions The smaller parasitic capacitance of concentration is smaller, and the Doped ions concentration of substrate 200 described in the present embodiment is mixed less than the ion of the well region Miscellaneous concentration, therefore, compared with prior art, the parasitic capacitance of GGNMOS of the present invention reduces, and prolongs so as to reduce input and output When the problem of, and then promoted chip operating rate.

It should be noted that optional, the semiconductor structure has the first body contact zone 261 and the second body contact zone 262.First body contact zone, 261 and second body contact zone 262 is also connected to ground terminal.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (10)

1. a kind of forming method of semiconductor structure, which is characterized in that including:
Substrate is provided, the substrate includes device region;
Several well regions are formed in the device region substrate, the well region includes the first well region, the second well region, and is located at institute One or several third well regions between the first well region and the second well region are stated, pass through the substrate between several described well regions It is isolated;
Gate structure is formed on the well region surface, the gate structure includes the first grid positioned at first well region surface Structure is located at the second grid structure on second well region surface, is located at two third grid knots on third well region surface Structure;
Source area is formed in the well region, the source area includes being located at the first grid structure far from the third grid First source area of structure side is located at second source electrode of the second grid structure far from third gate structure side Area, and the third source area in same third well region and between described two third gate structures;
In substrate between the first grid structure or second grid structure and adjacent third gate structure, if alternatively, Drain region is formed in substrate between the adjacent third gate structure of dry third well region, the drain region includes being located at described first The first drain region in substrate between gate structure and adjacent third gate structure, first drain region is across described first Well region and adjacent third well region, second in substrate between the second grid structure and adjacent third gate structure Drain region, second drain region is across second well region and adjacent third well region;
The semiconductor structure is that grid are grounded n type field effect transistor, the adjacent source area and drain region and the source electrode Well region between area and drain region constitutes NPN triode, and the gate structure is grounded the grid of n type field effect transistor as grid Structure.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that if the quantity of the third well region is Dry, in the step of forming the drain region, the drain region further includes the third in substrate between adjacent third well region Drain region, the third drain region is across the adjacent third well region.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that before forming the well region, also Including:The first isolation structure and the second isolation structure are formed in the substrate;
In the step of forming first well region and the second well region, the first well region for surrounding first isolation structure, shape are formed At the second well region for surrounding second isolation structure;
In the step of forming the source area, shape in the first well region between first isolation structure and first grid structure At first source area, described second is formed in the second well region between second isolation structure and second grid structure Source area.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that form the well region, the first isolation After structure and the second isolation structure, the forming method further includes:In first isolation structure far from the first grid Structure side forms the first body contact zone, and part first body contact zone is located in first well region, described second Isolation structure forms the second body contact zone far from second grid structure side, and part second body contact zone is located at institute It states in the second well region.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the grid ground connection N-type field-effect is brilliant Body pipe is used for electrostatic protection;
The type of the well region, the first body contact zone and the second body contact zone injection ion is p-type, the drain region and source area The type for injecting ion is N-type.
6. a kind of semiconductor structure, which is characterized in that including:
Substrate, the substrate include device region;
Several well regions being formed in substrate, several described well regions include the first well region for being located at the device region, second Well region, and one or several third well regions between first well region and the second well region, several described well regions Between be isolated by the substrate;
It is formed in the gate structure on the well region surface, the gate structure includes the first grid positioned at first well region surface Pole structure is located at the second grid structure on second well region surface, is located at two third grids on third well region surface Structure;
Source area in the well region, the source area include being located at the first grid structure far from the third grid First source area of structure side is located at second source electrode of the second grid structure far from third gate structure side Area, and the third source area in same third well region and between the third gate structure;
Between the first grid structure or second grid structure and adjacent third gate structure, alternatively, positioned at several the Drain region between the adjacent third gate structure of three well regions in substrate, the drain region include being located at the first grid structure The first drain region in substrate between adjacent third gate structure, first drain region is across first well region and phase Adjacent third well region, the second drain region in substrate between the second grid structure and adjacent third gate structure, Second drain region is across second well region and adjacent third well region;
The semiconductor structure is that grid are grounded n type field effect transistor, the adjacent source area and drain region and the source electrode Well region between area and drain region constitutes NPN triode, and the gate structure is grounded the grid of n type field effect transistor as grid Structure.
7. semiconductor structure as claimed in claim 6, which is characterized in that the semiconductor structure further includes being located at described first The first isolation structure in well region, and the second isolation structure in second well region;
First isolation structure is located in the first well region of first source area far from first grid structure side, institute The second isolation structure is stated to be located in the second well region of second source area far from second grid structure side.
8. semiconductor structure as claimed in claim 7, which is characterized in that the semiconductor structure further includes:Positioned at described First body contact zone of one isolation structure far from first grid structure side, a part for first body contact zone are located at In first well region;
Positioned at second body contact zone of second isolation structure far from second grid structure side, the second body contact The part in area is located in second well region.
9. semiconductor structure according to any one of claims 8, which is characterized in that the grid are grounded n type field effect transistor, are used for electrostatic Protection;
The well region, the first body contact zone and the second body contact zone Doped ions type be p-type, the drain region and source electrode The type of area's Doped ions is N-type.
10. a kind of electrostatic discharge protective circuit, which is characterized in that including:
Electrostatic input terminal;
Ground terminal;
Claim 6 to 9 any one of them semiconductor structure, the substrate, source area and gate structure are connected to ground terminal, institute Drain region is stated to be electrical connected with electrostatic input terminal.
CN201610056876.7A 2016-01-27 2016-01-27 Semiconductor structure and forming method thereof, electrostatic discharge protective circuit CN105489503B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN102315217A (en) * 2010-06-29 2012-01-11 上海宏力半导体制造有限公司 Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031799B1 (en) * 2009-05-28 2011-04-29 주식회사 바우압텍 Electro-Static Discharge Protection Device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN102315217A (en) * 2010-06-29 2012-01-11 上海宏力半导体制造有限公司 Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit

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