CN101821543A - 发光二极管阵列 - Google Patents
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Abstract
一维发光二极管(LED)(102)阵列(100)被配置成将LED彼此紧邻地(例如150μm或者更小)放置并且紧邻衬底边缘(107)地(例如150μm或者更小)放置LED的至少一个侧面。由于LED靠近衬底的边缘,因而可以并排地将多个一维阵列接合在一起以形成二维阵列(160),其中来自邻近的一维阵列的LED被靠近地放置在一起。通过最小化相同一维阵列与邻近一维阵列上的LED之间的间隙,改善了器件的亮度,从而使得器件适合用于高辐射度的应用。而且,使用一定数量的一维阵列以形成更大的二维阵列相对于常规的单片二维阵列提高了成品率。
Description
技术领域
本发明涉及发光器件阵列,特别地,涉及可以被组合以形成不同尺寸的二维阵列的一维发光二极管阵列。
背景技术
诸如发光二极管(LED)之类的半导体发光器件是高效的光源。对于许多应用而言,尤其是对于具有大于3mm2sr的光学径角性(etendue)的高视亮度应用而言,经常希望的是将多个LED放置在阵列中。由于亮度是LED彼此邻近程度的函数,因而希望的是在这样的阵列中将LED靠近地放置在一起。为了按常规方法形成阵列,直接地或者通过使用居间的基座(intervening submount)将LED单独地安装到单片衬底上。然而,精确地将大量LED结合到单个衬底上是困难的并且具有相对较低的成品率(yield)。例如,对于每LED 10%的故障率,将15个LED安装到3x5二维阵列中导致大约21%(90%^15)的成品率。
因此,希望的是产生改进的LED阵列,使得LED可以彼此紧邻地放置并且提高总的成品率。
发明内容
依照一个实施例,一维发光二极管(LED)阵列被配置成将LED彼此紧邻地(例如150μm或者更小)放置并且紧邻阵列的衬底边缘地(例如150μm或者更小)放置LED的至少一个侧面。由于LED靠近衬底的边缘,因而可以并排地将多个一维阵列接合(join)在一起以形成二维阵列,其中来自邻近一维阵列的LED靠近地放置在一起。通过最小化相同一维阵列与邻近一维阵列上的LED之间的间隙,改善了器件的亮度,从而使得器件适合用于高辐射度的应用。而且,使用一定数量的一维阵列以形成更大的二维阵列相对于常规的单片二维阵列提高了成品率。
附图说明
图1示出了一维发光二极管(LED)阵列的俯视图。
图2示出了并排地组合以形成二维阵列的多个一维阵列。
图3示出了热沉的俯视图,图2中示出的二维阵列可以安装到该热沉。
图4为安装到衬底上的二维阵列的侧视图,其中冷却接口耦合到上覆的LED。
图5为图4中所示二维阵列的顶视图。
图6示出了用于图1的一维阵列的衬底的俯视图。
图7示出了图1和图6的一维阵列的一部分的更近的视图。
图8示出了安装LED并且切割成单独的一维阵列之前在单个瓦状物(tile)上产生的多个衬底的顶视图。
图9示出了一维阵列的另一实施例的俯视图,其中接触引线位于衬底顶面的相同侧。
图10为所述一维阵列沿着图9中的直线A-A的截面图。
图11示出了使用一定数量的一维阵列产生的二维阵列的实例。
图12示出了由两个串联耦合的1x3一维阵列形成的2x3二维阵列。
图13示出了一维阵列的另一实施例,其中LED并联地耦合在一起。
具体实施方式
图1示出了一维发光二极管(LED)阵列100的俯视图,该阵列包括装有多个发光二极管(LED)102的衬底104。衬底104包括具有顶面的绝缘底座106,所述顶面覆盖有图案化导电层以便形成LED 102的N接触引线108lead和P接触引线110lead以及N触点108和P触点110,其在图1中被LED 102隐藏,但是显示在图6中。LED 102串联地耦合在一起,N接触引线108lead和P接触引线110lead位于衬底104的相对侧。
在图1中,一维阵列100被示为能够容纳高达七个LED 102。然而,如果希望的话,阵列100可以被配置成容纳更多或更少的LED 102。一维阵列100通常可以被称为1xN阵列,其中N≥2。根据本公开,可以产生与图1中所示阵列100类似但是具有不同数量N的LED的阵列。而且,如果希望的话,一维阵列100上的LED安装位置中的一个或多个可以未被占用(unpopulated)以及短路,这在图1中由LED 102a中的交叉影线示出。如图2所示,多个一维1xN阵列100可以进行组合,即彼此邻近地安装,以便形成二维MxN阵列200,其中M≥2。用来产生二维阵列200的一维阵列100可以装有相同数量的LED 102,或者可替换地,一维阵列100中的一个或多个可以具有不同数量的LED102以产生希望的阵列配置。
使用许多单独的一维阵列100以形成二维阵列的优点在于,提高了总的成品率。例如,具有15个LED的常规单片二维阵列(例如3x5阵列)可以具有21%(90%^15)的成品率,而假设紧密地安装和电连接五条带的成品率为99%,那么使用五个一维1x3阵列可以得到69%(90%^3*99%^5)的成品率。
图3示出了热沉210的俯视图,MxN阵列200可以安装到该热沉。热沉210可以由热传导材料(例如铝或铜或者其合金)制成。热沉210包括电隔离的引线212,其例如通过线焊或者通过底面衬底104上的焊料回流电耦合到单独的1xN阵列100的N和P接触引线108、110,其中衬底104中的通孔(未示出)提供到顶面上的N和P触点108、110的电接触。可以将一维阵列100的衬底104焊接到热沉210以便提供从LED 102通过一维阵列100的衬底到热沉210的良好的热接触和低热阻。
图4为阵列200’的侧视图,该阵列类似于图2中示出的阵列200,并且耦合到直接键合铜(DBC)衬底120,该衬底在LED的位置之下具有孔以便提供与热管122或者其他适当的冷却接口的热接触。由图4可知,线焊124提供DBC衬底120与N和P接触引线108和110之间的电接触。可替换地,DBC衬底120与N和P接触引线108和110之间的电接触利用衬底104中用虚线所示的通孔126来实现。
图5为图4中所示的阵列200’的顶视图,其中圆示出热管122的位置。由图5可知,阵列200’可以包括一个或多个具有变化数量的LED102的一维阵列100,这可以有利于优化热接口或者只是产生希望的阵列面积。所述圆可替换地可以代表光学系统(例如圆弧形(round)聚光灯)的形状,其中每条带使用变化数量的LED有助于实现该光学系统的理想的形状。
图6示出了用于一维阵列100的衬底104的俯视图。衬底104包括底座106,该底座可以为例如陶瓷、Al2O3、AlN、氧化铝或者氮化硅。底座106覆盖有图案化导体区域109以形成LED的电隔离的N触点108和P触点110,其与它们之间的导电桥111串联设置。导体区域109可以常规地用平版印刷方法例如由Au或Cu或者适当的金属或金属合金沉积和图案化,并且可以具有例如2μm的厚度。LED位点(site)处的N和P触点108和110上镀有凸块(bump)112,其在将LED 102安装到衬底104上时提供与LED 102的电接触。电镀的凸块112可以为例如Au镀层,其为15-30μm厚,具有例如50%的面积覆盖。
图7示出了阵列100的一部分的更近的视图,其中LED 102的若干部分被切除。阵列100被配置成使得LED 102可以靠近地安装在一起以便提高器件的亮度,使得阵列100适合用于高辐射度器件(例如背投影系统)以及高流明/瓦特系统(例如袖珍投影仪)。通常,亮度L=通量/(面积*π)并且MxN阵列的面积为面积=(M*LED的宽度+(M-1)*间隙宽度)*(N*LED的长度+(N-1)*间隙长度)。因此,假设来自LED的总的通量相同,那么间隙长度或间隙宽度越大,则面积越大并且亮度L越低。
形成N触点108和P触点110,使得当安装到衬底104上时,LED102之间的间隙(距离Dgap)为150μm或更小,优选地为100μm或更小,例如75μm或50μm。为了最小化距离Dgap,两个邻近LED位点的N触点110被配置成靠近在一起,例如距离Dcontacts。在确定最小距离Dcontacts以及因而距离Dgap方面,必须考虑具有例如±15μm的公差的LED管芯的放置。如果距离Dcontacts太小,那么在LED管芯的放置期间LED管芯可能短路或者彼此接触。电镀的凸块112的放置的制造公差也增加了所述公差,例如±15μm。通过最小化衬底104上的LED 102之间的间隙,增加了阵列100的亮度。
此外,衬底104被配置成使得LED 102的边缘与底座106的至少一条边缘107之间的距离Dedge最小化,例如150μm或更小,优选地为100μm或更小,例如75μm或50μm。通过最小化距离Dedge,来自两个邻近的一维阵列100的LED 102之间的距离将不超过300μm。为了最小化距离Dedge,N触点108被配置成使得它们最小地或者根本不延伸出LED 102的边缘之外,即距离D102小于50μm,优选地为25μm或更小,例如0.0μm,除了与相邻LED位点之下的P触点110形成电接触或者与N接触引线108lead形成电接触的桥111之外。通过配置金属N触点108使得它们完全位于LED 102之下,衬底104的底座106可以被锯切成非常靠近LED 102的边缘而不接触金属触点材料,其将干扰底座106的锯切,以及当靠近地放置在一起时具有与相邻阵列短路的风险。应当理解的是,当前实施例基于N触点位于LED管芯的参数(parameter)上的LED倒装芯片配置。对于其他的配置,例如P触点位于LED管芯的参数上,或者N触点和P触点位于LED管芯的相对侧,可以根据本公开内容适当地改变N触点108和P触点110的配置。
在制造中,可以同时从单个大的瓦状物产生多个衬底104。图8通过实例示出了在安装LED 102并且切割成单独的阵列100之前在单个瓦状物160上产生的多个衬底104的顶视图。在形成衬底104之后,形成了接触区域109和电镀的凸块112(图6),LED 102设置在瓦状物160上。LED 102可以是任何希望的倒装芯片设计,并且优选地为III族氮化物器件,其常规上在蓝宝石、碳化硅或者III氮化物衬底上外延生长。一旦安装了LED 102,那么可以执行常规的环氧树脂底层填充工艺,其后例如使用激光剥离或者其他适当的工艺去除生长衬底。然后,使用例如光电化学(PEC)或者其他适当的工艺粗糙化LED 102的其余顶面以便改善光提取。然后,可以例如使用锯切工艺切割单独的一维阵列100,对其测试,并且以多个1xN单元将其安装和电连接在热沉上。
此外,衬底104的设计消除了对于线焊的需要,并且避免了在离LED 102阵列的近参数内放置比LED高的部件,比如瞬态电压抑制器(TVS)。因此,诸如透镜之类的光学部件可以放置得靠近LED的顶面,例如100μm或更小。
图9示出了一维(1x3)阵列300的另一实施例的俯视图,其中N接触引线302lead和P接触引线304lead位于衬底306的相同侧。图10为图9中一维阵列300沿着直线A-A的截面图。应当理解的是,阵列300的尺寸可以相对于所示的改变,例如,该阵列可以为1x2、1x4或者更大。图11示出了使用四个一维1x3阵列300和四个一维1x2阵列301产生的二维4x5阵列350的实例。当然,可以使用更大或更小的一维阵列以及使用更少或附加的一维阵列产生不同尺寸的二维阵列。
如图10所示,衬底306由具有2μm厚的例如Au或Cu的导电底层312的例如硅的底座310形成。绝缘层314覆盖在底层312之上。绝缘层314可以是例如1.5μm厚的氧化硅层或者其他合适材料层。由图10可见,两个Au或其他合适材料的通孔316a、316b存在于绝缘层314中。通孔316a位于P接触引线304之下,而通孔316b位于阵列中最远的LED的P接触区块(area)之下。图案化导体区域318位于绝缘层314之上,其形成LED的接触引线302lead和304lead以及N触点302和P触点304。电镀的凸块320位于导体区域318之上,其提供与LED的电接触。
图12示出了两个安装在一起以形成2x3二维阵列400的1x3一维LED 403阵列402的俯视图。一维阵列402可以以类似于图1所述阵列100的方式形成,例如图案化金属触点覆盖在绝缘底座上。所述两个一维阵列402通过导电带状物(ribbon)405和407串联耦合在正极引线404和负极引线406之间,跨接线408将一个阵列的N触点410耦合到另一个阵列的正极触点412。阵列402安装在用于散热的金属块(slug)414上并且被塑料或其他合适材料的模制体416包围。一维阵列402还包括TVS二极管418。由图12可见,阵列402被配置成使得LED 403的仅仅一个侧面靠近衬底的边缘。而且,高于LED 403的部件(例如跨接线408、带状物405和407以及TVS二极管4018)置于LED的近参数之外,例如大于0.5mm,更特别地大于1mm或2mm。因此,诸如透镜之类的光学部件可以放置得靠近(例如100μm或更小)LED阵列,而没有来自跨接线408、带状物405和407以及TVS二极管4018的干扰。
图13示出了一维阵列500的另一实施例,其中LED 501(仅仅LED的一部分被示出)通过N触点502和P触点504并联耦合到N接触引线502lead和P接触引线504lead。因此,N触点502耦合在一起并且P触点504耦合在一起。
尽管出于教导的目的结合特定实施例说明了本发明,但是本发明并不限于此。在不脱离本发明的范围的情况下,可以做出各种调整和修改。因此,所附权利要求的精神和范围并不限于前面的描述。
Claims (14)
1.一种设备,包括:
一维发光二极管阵列,该一维阵列包括:
衬底,其具有底座和多个设置在底座上的导电接触区域;
多个发光二极管,每个发光二极管具有倒装芯片配置并且安装在所述多个导电接触区域之一上,其中每个发光二极管与另一个发光二极管分开150μm或更小,并且其中每个发光二极管具有与底座的侧面分开150μm或更小的边缘。
2.权利要求1的设备,还包括位于底座顶面的相对侧的正极接触引线和负极接触引线。
3.权利要求1的设备,还包括位于底座顶面的相同侧的正极接触引线和负极接触引线。
4.权利要求1的设备,其中所述接触区域被配置成使得一个发光二极管之下的正极接触区块电耦合到邻近发光二极管之下的负极接触区块。
5.权利要求1的设备,其中所述多个发光二极管通过所述接触区域并联地电耦合在一起,从而一个发光二极管之下的正极接触区块电耦合到邻近发光二极管之下的正极接触区块。
6.权利要求1的设备,其中每个接触区域具有不相对于上覆的发光二极管的边缘延伸超过50μm的侧面。
7.权利要求1的设备,其中每个发光二极管与另一个发光二极管分开100μm或更小,并且其中每个发光二极管具有与底座的侧面分开100μm或更小的边缘。
8.权利要求1的设备,还包括被配置成形成二维发光二极管阵列的多个一维发光二极管阵列,其中每个一维阵列上的发光二极管相距邻近一维阵列上的发光二极管不到300μm。
9.权利要求1的设备,其中所述一维阵列中的至少一个与其余一维阵列具有不同数量的发光二极管。
10.权利要求1的设备,其中所述发光二极管具有一定高度,并且其中不存在相距所述发光二极管之一比2mm更近、高度大于所述发光二极管高度的部件。
11.一种二维发光二极管阵列,包括:
多个一维发光二极管阵列,每个一维发光二极管阵列包括多个安装在衬底上的倒装芯片发光二极管,其中衬底上的每个发光二极管与相同衬底上的另一个发光二极管分开150μm或更小,并且其中每个发光二极管与邻近一维阵列上的发光二极管分开300μm或更小。
12.权利要求11的二维发光二极管阵列,其中该二维阵列为MxN阵列,其中M≥2并且N≥2,其中存在M个一维阵列并且所述M个一维阵列中的每一个为1xN阵列。
13.权利要求11的二维发光二极管阵列,其中每个一维阵列还包括位于发光二极管之下的衬底上的导电接触区域,每个接触区域具有不相对于上覆的发光二极管的边缘延伸超过50μm的侧面。
14.权利要求11的二维发光二极管阵列,其中这些发光二极管具有一定高度,并且其中不存在相距所述发光二极管之一比2mm更近、高度大于所述发光二极管高度的部件。
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US11/844,279 US20090050921A1 (en) | 2007-08-23 | 2007-08-23 | Light Emitting Diode Array |
US11/844279 | 2007-08-23 | ||
PCT/IB2008/053387 WO2009024951A1 (en) | 2007-08-23 | 2008-08-22 | Light emitting diode array |
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CN (1) | CN101821543A (zh) |
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- 2008-08-22 RU RU2010110808/28A patent/RU2010110808A/ru unknown
- 2008-08-22 EP EP08789620A patent/EP2183521A1/en not_active Withdrawn
- 2008-08-22 WO PCT/IB2008/053387 patent/WO2009024951A1/en active Application Filing
- 2008-08-22 KR KR1020107006249A patent/KR20100047324A/ko not_active Application Discontinuation
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KR20100047324A (ko) | 2010-05-07 |
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US20090050921A1 (en) | 2009-02-26 |
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