CN101794268A - Processing module capable of reconstructing signals based on VPX bus - Google Patents
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Abstract
The invention relates to a processing module capable of reconstructing signals based on a VPX bus, comprising a high-speed board card, a front panel, a radiating cover board, a module lifter, a positioning pin and a locking mechanism part. The high-speed board card comprises a VPX 6U standard high-speed printing board, a power supply circuit, an MPC7448 processor chip, an MV64460 bridging chip, a FPGA (Field Programmable Gate Array) chip, a DDR SDRAM (Digital Data Receiver Synchronous Dynamic Random Access) and FLASH, a high-speed high density electric connector, an opto-electrical converter and a kilomega Ethernet interface. The high-speed board card comprises four processing nodes, each processing node comprises one MPC7448 processor chip, one MV64460 bridging chip and the DDR SDRAM; the MV64460 bridging chip is respectively connected with the MPC7448 processor chip and a storage DDR SDRAMFPGA through a CPU interface, the DDR SDRAM interface and a Device interface.
Description
Technical field
The present invention relates to a kind ofly, belong to digital processing field based on VPX bus, restructural signal processing module.
Background technology
Digital Signal Processing is mainly realized the signal Processing to time domain, frequency domain and spatial domain, for example electronic system equipment such as Radar Signal Processing, electronic countermeasure, communication.Signal Processing operand in these fields is big, the algorithm structure complexity, and this just requires digital information processing system to possess stronger processing capability in real time and high-speed data communications ability.In order to satisfy the growing requirement of application system, need development digital signal processing module of new generation to signal handling capacity.
Summary of the invention
1, technical matters to be solved:
The invention provides a kind of based on VPX bus, restructural signal processing module at above problem.
2, technical scheme:
A kind ofly comprise high speed integrated circuit board, front panel, heat radiation cover plate, module plug-in and pull-out device, register pin, latch mechanism parts based on VPX bus, restructural signal processing module;
The high speed integrated circuit board comprises a high speed printed board and welds superincumbent device that the profile of high speed printed board is a VPX 6U standard template; The welding device comprises feed circuit, general processor, bridging chip, FPGA (Field Programmable Gate Array) (FPGA) chip, storer, the highly dense electric connector of high speed, electrooptical device, gigabit ethernet interface;
Feed circuit are made up of ten power modules, and they are: 1 PTH04040WAH, 3 PTH05050WAH, 1 PTH08T241WAD, 4 LT3021ES8,1 MIC37139-1.8BS;
General processor is the MPC7448 processor chips of FreeScale company;
Bridging chip is the MV64460 chip of Marvell company;
FPGA (Field Programmable Gate Array) (FPGA) chip is the PGA chip of XILINX company, and model is XC5VLX110T;
Storer has two kinds of DDR SDRAM and FLASH, and DDR SDRAM chipset is made up of for the MT46V64M16TG-6TIT chip four models, and memory capacity is 2G; The FLASH chipset is made up of for the S29GL256N10TFI01 chip four models, and memory capacity is 512M;
The highly dense electric connector of high speed has seven, item in the high speed printed board is XP0-XP6, XP0 provides modular power source, XP1 provides the high speed serial port of 8 road intermodules interconnection, XP2 provides VME interface, XP4 provides high speed serial port and two gigabit ethernet interfaces that interconnect between 4 tunnel systems, and XP5 provides GPIO and serial ports, and XP3, XP6 are self-defined;
The electrooptical device model is LTP-ST11MB;
Front panel has six openings, the interface that is welded on two multimode electrooptical devices of high speed printed board, 9 core electric connectors, an Ethernet interface, a reset button and eight signal lamps exposes from opening portion, is used for debugging and and other system integration and test.Wherein 9 core electric connectors are used for debug serial port, and its model is J30J-9TJWP7-J.Ethernet interface can be connected with workbench computing machine or other system, carries out data communication.
The heat radiation cover plate covers in the high speed printed board, for module provides heat abstractor.
Module plug-in and pull-out device, register pin, latch mechanism are fixed in the high speed printed board by fixator, for module provides plug-in and pull-off device, make things convenient for the plug of module.
Described high speed integrated circuit board has four processing nodes, and each processing node comprises a slice PowerPC series MPC7448 general processor, a slice MV64460 bridging chip, the DDR SDRAM of 512MB;
The MPC7448 processor chips are connected with the cpu i/f of MV64460 bridging chip, are 64 MPX 100MHz buses between MPC7448 processor chips and the MV64460 bridging chip, are used for data transmission and addressing; The DDR sdram interface of storer DDRSDRAM and MV64460 bridging chip is connected, 64 of bit wides, and speed 100Mhz is used for data access; The Device interface of MV64460 bridging chip is connected with FPGA, and FPGA internal register and Flash chip unified addressing conduct interviews to it by the Device interface; FPGA is connected with loading Flash chip, and FPGA realizes respectively handling the arbitration control that node visit loads Flash; During the module electrifying startup, each processing node loads Flash by the arbitration sequential by each MV64460 bridging chip Device port addressing, and operation starts guidance code, operation system image is moved to node memory operation realization system normally start; The MPP interface of MV64460 bridging chip is connected with FPGA, and the FPGA inner function module is triggered and controls;
Interconnection mode between the inside modules processing node is the PCI-X bus, four groups of hypervelocity PCI-X buses are provided between four MV64460 bridging chips, between first node and the Section Point, between Section Point and the 3rd node, be 64 100MHz hypervelocity PCI-X buses between the 3rd node and the 4th node, be 32 100MHz hypervelocity PCI-X buses between first node and the 4th node;
The interface shape of communication has three kinds between the module: high-speed serial channel Rocket IO, VME bus, gigabit Ethernet network agreement, GPIO RS232 interface;
High-speed serial channel Rocket IO is provided by FPGA, and every road transfer rate can reach 2.5Gbps, supports the Aurora serial communication protocol of XILINX company, has 14 the tunnel; 8 the tunnel by VPX socket XP1 realization backplane interconnect, and XP1 is eight groups of high-speed serial channels by the VITA46.3 protocol definition, by other integrated circuit board communication in backboard and the same cabinet; 4 road high-speed serial channel Rocket IO are connected with the back outlet board by the VPX electric connector, realize and back outlet board communication; 2 road high-speed serial channel RocketIO link to each other with two electrooptical devices, and the optical fiber interface of electrooptical device panel optical fiber interface in the past exposes, and can realize optical-fibre communications with other system by optical fiber; The Sync fifo interface of every MV64460 bridging chip is connected with FPGA respectively, by the inner conversion that realizes MV64460 bridging chip Sync fifo interface to high-speed serial channel Rocket IO of FPGA, the switching fabric of support software configuration is realized by FPGA, can realize that by switching fabric arbitrary passage is set up communication link among the Sync fifo interface of bridging chip MV64460 in arbitrary node and 14 road high-speed serial channel Rocket IO, thereby realize the high-speed data communications of intermodule;
XP2 is the VME parallel bus by the VITA46.1 protocol definition, the relevant pins of FPGA realizes backplane interconnect by XP2, VME bus controller with principal and subordinate's function is realized by the FPGA design, the Device interface of processing main chip MPC7448 links to each other with FPGA, in the inner conversion that realizes parallel bus to the VME bus of FPGA;
First and the Giga Ethernrt interface of managing MV64460 bridging chip in the node everywhere is connected with Gigabit Ethernet transceiver (GPHY) respectively and realizes two gigabit ethernet interfaces, front panel provides a network interface, rear socket provides two network interface outlets, and wherein the network interface of rear socket network interface and front panel is that alternative uses;
GPIO RS232 interface is realized by FPGA, links to each other with PC by high-speed high-density connector, realizes the debugging to this module.
3, beneficial effect:
1) the present invention adopts four MPC7448 processor chips, has powerful processing power, can satisfy the demand of signal processing system to various algorithm complexes, real-time, has improved the processing speed of signal processing system;
2) data transmission interface adopts the high speed serial communication technology, and the HSSI High-Speed Serial Interface module of FPGA inside is supported the high speed serial communication agreement, has increased substantially the exchanges data bandwidth;
3) realize a kind of topological structure flexibly by FPGA inner exchanging network, be used to make up different signal processing systems, can satisfy the requirement of different application, be convenient to system upgrade and safeguard, shorten the lead time, reduce development cost signal handling capacity;
4) this module external interface is a standard vita46 interface, has stronger versatility;
5) provide complete module bottom layer driving function interface, made things convenient for application layer to design and develop.
Description of drawings
Fig. 1 is the system chart based on VPX bus, restructural signal processing module.
Fig. 2 is the structural representation of module application of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is done explanation in further detail.
This module comprises high speed integrated circuit board, front panel, heat radiation cover plate, module plug-in and pull-out device, register pin, latch mechanism parts.
The high speed integrated circuit board comprises a high speed printed board and welds superincumbent device that the profile of high speed printed board is a VPX 6U standard template.The welding device comprises feed circuit, general processor, bridging chip, FPGA (Field Programmable Gate Array) (FPGA) chip, storer, the highly dense electric connector of high speed, electrooptical device, gigabit ethernet interface.
Feed circuit are made up of ten power modules, and they are: 1 PTH04040WAH, 3 PTH05050WAH, 1 PTH08T241WAD, 4 LT3021ES8,1 MIC37139-1.8BS.
General processor is the MPC7448 processor chips of FreeScale company.
Bridging chip is the MV64460 chip of Marvell company.
FPGA (Field Programmable Gate Array) (FPGA) chip is the PGA chip of XILINX company, and model is XC5VLX110T, and it is the core component of whole module, realizes the functions such as control, data dispatch, communications protocol conversion to module.
Storer has two kinds of DDR SDRAM and FLASH.DDR SDRAM chipset is made up of for the MT46V64M16TG-6TIT chip four models, and memory capacity is 2G; The FLASH chipset is made up of for the S29GL256N10TFI01 chip four models, and memory capacity is 512M.
The highly dense electric connector of high speed has seven, item in the high speed printed board is XP0-XP6, XP0 provides modular power source, XP1 provides the high speed serial port of 8 road intermodules interconnection, XP2 provides VME interface, XP4 provides high speed serial port and two gigabit ethernet interfaces that interconnect between 4 tunnel systems, and XP5 provides GPIO and serial ports, and XP3, XP6 are self-defined.
The electrooptical device model is LTP-ST11MB, and the serial rate of each passage can be used for carrying out communication with other subsystem up to 2.5GBPS.
Front panel has six openings, the interface that is welded on two multimode electrooptical devices of high speed printed board, 9 core electric connectors, an Ethernet interface, a reset button and eight signal lamps exposes from opening portion, is used for debugging and and other system integration and test.Wherein 9 core electric connectors are used for debug serial port, and its model is J30J-9TJWP7-J.Ethernet interface can be connected with workbench computing machine or other system, carries out data communication.
The heat radiation cover plate covers in the high speed printed board, for module provides heat abstractor.
Module plug-in and pull-out device, register pin, latch mechanism are fixed in the high speed printed board by fixator, for module provides plug-in and pull-off device, make things convenient for the plug of module.
The high speed integrated circuit board is a carrier of realizing whole functions of modules, system chart as shown in Figure 1, its function structure is described below:
Four processing nodes, each processing node comprise a slice PowerPC series MPC7448 general processor, a slice MV64460 bridging chip, the DDR SDRAM of 512MB.
The work clock of MPC7448 is by 100MHz crystal oscillator phase locking frequency multiplying, and the work dominant frequency is by resistance choosing weldering selection of configuration, and the default work dominant frequency of module is 1000MHz.
The interface of MV64460 bridging chip comprises cpu i/f, DDR sdram interface, Device interface, Ethernet interface, jtag interface, MPP interface, Sync fifo interface.
The MPC7448 processor chips are connected with the cpu i/f of MV64460 bridging chip, are 64 MPX 100MHz buses between MPC7448 processor chips and the MV64460 bridging chip, are used for data transmission and addressing.The DDR sdram interface of storer DDRSDRAM and MV64460 bridging chip is connected, 64 of bit wides, and speed 100Mhz is used for data access.The Device interface of MV64460 bridging chip is connected with FPGA, and FPGA internal register and Flash chip unified addressing conduct interviews to it by the Device interface.FPGA is connected with loading Flash chip, and FPGA realizes respectively handling the arbitration control that node visit loads Flash.During the module electrifying startup, each processing node loads Flash by the arbitration sequential by each MV64460 bridging chip Device port addressing, and operation starts guidance code, operation system image is moved to node memory operation realization system normally start.Module provides complete bottom layer driving function interface, direct access hardware devices, it has comprised processor reset, initialization, serial port drive program, network port driving program, Flash chip driver program and necessary clock handles, and makes things convenient for the developer to develop complexity, high-end real-time system according to demand.The MPP interface of MV64460 bridging chip is connected with FPGA, and the FPGA inner function module is triggered and controls.
The communications protocol of module mainly comprises the aurora agreement of PCI agreement, VME agreement, gigabit Ethernet agreement, XILINX company, SMBUS agreement.
Interconnection mode between the inside modules processing node is the PCI-X bus, four groups of hypervelocity PCI-X buses are provided between four MV64460 bridging chips, between first node and the Section Point, between Section Point and the 3rd node, be 64 100MHz hypervelocity PCI-X buses between the 3rd node and the 4th node, be 32 100MHz hypervelocity PCI-X buses between first node and the 4th node.
The interface shape of communication has three kinds between the module: high-speed serial channel Rocket IO, VME bus, gigabit Ethernet network agreement, GPIO RS232 interface.
High-speed serial channel Rocket IO is provided by FPGA, and every road transfer rate can reach 2.5Gbps, supports the Aurora serial communication protocol of XILINX company, has 14 the tunnel.8 the tunnel by VPX socket XP1 realization backplane interconnect, and XP1 is eight groups of high-speed serial channels by the VITA46.3 protocol definition, by other integrated circuit board communication in backboard and the same cabinet.4 road high-speed serial channel Rocket IO are connected with the back outlet board by the VPX electric connector, realize and back outlet board communication.2 road high-speed serial channel RocketIO link to each other with two electrooptical devices, and the optical fiber interface of electrooptical device panel optical fiber interface in the past exposes, and can realize optical-fibre communications with other system by optical fiber.The Sync fifo interface of every MV64460 bridging chip is connected with FPGA respectively, by the inner conversion that realizes MV64460 bridging chip Sync fifo interface to high-speed serial channel Rocket IO of FPGA, the switching fabric of support software configuration is realized by FPGA, can realize that by switching fabric arbitrary passage is set up communication link among the Sync fifo interface of bridging chip MV64460 in arbitrary node and 14 road high-speed serial channel Rocket IO, thereby realize the high-speed data communications of intermodule.
XP2 is the VME parallel bus by the VITA46.1 protocol definition, the relevant pins of FPGA realizes backplane interconnect by XP2, VME bus controller with principal and subordinate's function is realized by the FPGA design, the Device interface of processing main chip MPC7448 links to each other with FPGA, in the inner conversion that realizes parallel bus to the VME bus of FPGA.A plurality of modules are formed signal processing system, and the VME master controller transmits mode of operation, control command and parameter by the VME bus and gives other module, realizes the control function of each module of total system
First and the Giga Ethernrt interface of managing MV64460 bridging chip in the node everywhere is connected with Gigabit Ethernet transceiver (GPHY) respectively and realizes two gigabit ethernet interfaces, front panel provides a network interface, rear socket provides two network interface outlets, and wherein the network interface of rear socket network interface and front panel is that alternative uses.
GPIO RS232 interface is realized by FPGA, links to each other with PC by high-speed high-density connector, realizes the debugging to this module.
Can make up randomly topologically structured signal processing system based on this module and interconnection mode thereof, based on certain Radar Signal Processing subsystem that VPX bus, restructural signal processing module make up, its structure as shown in Figure 2.Under the VPX bus architecture, this system is made of five modules of the present invention and a VPX High speed rear panel, and in addition, power supply, oscillograph, switch, G4 emulator, FPGA cable, computing machine are as the commissioning device of this system.The zero channel mould piece of VPX High speed rear panel is as the VME controller, support high-speed serial bus and the communication of VME parallel bus in the system, utilize this system can finish signal processing functions such as pulse pressure, Doppler's processing, CFAR detection, residual spur figure processing, target accumulation detection, target extraction.
Though the present invention with preferred embodiment openly as above; but they are not to be used for limiting the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the invention; from when can doing various variations or retouching, so being as the criterion of should being defined with the application's claim protection domain of protection scope of the present invention.
Claims (2)
1. one kind based on VPX bus, restructural signal processing module, it is characterized in that: high speed integrated circuit board, front panel, heat radiation cover plate, module plug-in and pull-out device, register pin, latch mechanism parts;
The high speed integrated circuit board comprises a high speed printed board and welds superincumbent device that the profile of high speed printed board is a VPX 6U standard template; The welding device comprises feed circuit, general processor, bridging chip, FPGA (Field Programmable Gate Array) (FPGA) chip, storer, the highly dense electric connector of high speed, electrooptical device, gigabit ethernet interface;
Feed circuit are made up of ten power modules, and they are: 1 PTH04040WAH, 3 PTH05050WAH, 1 PTH08T241WAD, 4 LT3021ES8,1 MIC37139-1.8BS;
General processor is the MPC7448 processor chips of FreeScale company;
Bridging chip is the MV64460 chip of Marvell company;
FPGA (Field Programmable Gate Array) (FPGA) chip is the PGA chip of XILINX company, and model is XC5VLX110T;
Storer has two kinds of DDR SDRAM and FLASH, and DDR SDRAM chipset is made up of for the MT46V64M16TG-6TIT chip four models, and memory capacity is 2G; The FLASH chipset is made up of for the S29GL256N10TFI01 chip four models, and memory capacity is 512M;
The highly dense electric connector of high speed has seven, item in the high speed printed board is XP0-XP6, XP0 provides modular power source, XP1 provides the high speed serial port of 8 road intermodules interconnection, XP2 provides VME interface, XP4 provides high speed serial port and two gigabit ethernet interfaces that interconnect between 4 tunnel systems, and XP5 provides GPIO and serial ports, and XP3, XP6 are self-defined;
The electrooptical device model is LTP-ST11MB;
Front panel has six openings, the interface that is welded on two multimode electrooptical devices of high speed printed board, 9 core electric connectors, an Ethernet interface, a reset button and eight signal lamps exposes from opening portion, is used for debugging and and other system integration and test.Wherein 9 core electric connectors are used for debug serial port, and its model is J30J-9TJWP7-J.Ethernet interface can be connected with workbench computing machine or other system, carries out data communication.
The heat radiation cover plate covers in the high speed printed board, for module provides heat abstractor.
Module plug-in and pull-out device, register pin, latch mechanism are fixed in the high speed printed board by fixator, for module provides plug-in and pull-off device, make things convenient for the plug of module.
2. according to claim 1 based on VPX bus, restructural signal processing module, it is characterized in that: described high speed integrated circuit board has four processing nodes, each processing node comprises a slice PowerPC series MPC7448 general processor, a slice MV64460 bridging chip, the DDR SDRAM of 512MB;
The MPC7448 processor chips are connected with the cpu i/f of MV64460 bridging chip, are 64 MPX 100MHz buses between MPC7448 processor chips and the MV64460 bridging chip, are used for data transmission and addressing; The DDR sdram interface of storer DDRSDRAM and MV64460 bridging chip is connected, 64 of bit wides, and speed 100Mhz is used for data access; The Device interface of MV64460 bridging chip is connected with FPGA, and FPGA internal register and Flash chip unified addressing conduct interviews to it by the Device interface; FPGA is connected with loading Flash chip, and FPGA realizes respectively handling the arbitration control that node visit loads Flash; During the module electrifying startup, each processing node loads Flash by the arbitration sequential by each MV64460 bridging chip Device port addressing, and operation starts guidance code, operation system image is moved to node memory operation realization system normally start; The MPP interface of MV64460 bridging chip is connected with FPGA, and the FPGA inner function module is triggered and controls;
Interconnection mode between the inside modules processing node is the PCI-X bus, four groups of hypervelocity PCI-X buses are provided between four MV64460 bridging chips, between first node and the Section Point, between Section Point and the 3rd node, be 64 100MHz hypervelocity PCI-X buses between the 3rd node and the 4th node, be 32 100MHz hypervelocity PCI-X buses between first node and the 4th node;
The interface shape of communication has three kinds between the module: high-speed serial channel Rocket IO, VME bus, gigabit Ethernet network agreement, GPIO RS232 interface;
High-speed serial channel Rocket IO is provided by FPGA, and every road transfer rate can reach 2.5Gbps, supports the Aurora serial communication protocol of XILINX company, has 14 the tunnel; 8 the tunnel by VPX socket XP1 realization backplane interconnect, and XP1 is eight groups of high-speed serial channels by the VITA46.3 protocol definition, by other integrated circuit board communication in backboard and the same cabinet; 4 road high-speed serial channel Rocket IO are connected with the back outlet board by the VPX electric connector, realize and back outlet board communication; 2 road high-speed serial channel RocketIO link to each other with two electrooptical devices, and the optical fiber interface of electrooptical device panel optical fiber interface in the past exposes, and can realize optical-fibre communications with other system by optical fiber; The Sync fifo interface of every MV64460 bridging chip is connected with FPGA respectively, by the inner conversion that realizes MV64460 bridging chip Sync fifo interface to high-speed serial channel Rocket IO of FPGA, the switching fabric of support software configuration is realized by FPGA, can realize that by switching fabric arbitrary passage is set up communication link among the Sync fifo interface of bridging chip MV64460 in arbitrary node and 14 road high-speed serial channel Rocket IO, thereby realize the high-speed data communications of intermodule;
XP2 is the VME parallel bus by the VITA46.1 protocol definition, the relevant pins of FPGA realizes backplane interconnect by XP2, VME bus controller with principal and subordinate's function is realized by the FPGA design, the Device interface of processing main chip MPC7448 links to each other with FPGA, in the inner conversion that realizes parallel bus to the VME bus of FPGA;
First and the Giga Ethernrt interface of managing MV64460 bridging chip in the node everywhere is connected with Gigabit Ethernet transceiver (GPHY) respectively and realizes two gigabit ethernet interfaces, front panel provides a network interface, rear socket provides two network interface outlets, and wherein the network interface of rear socket network interface and front panel is that alternative uses;
GPIO RS232 interface is realized by FPGA, links to each other with PC by high-speed high-density connector, realizes the debugging to this module.
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| CN102486723A (en) * | 2010-12-01 | 2012-06-06 | 研祥智能科技股份有限公司 | Method for realizing ChMC (Chassis Management Controller) and VMC (VPX Manager Controller) on VPX (Versatile Protocol Switch) platform veneer and VPX platform |
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