CN105933219A - Heterogeneous multi-source high-speed data exchange adapter - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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Abstract
The invention discloses a heterogeneous multi-source high-speed data exchange adapter. According to the adapter, a processor at least comprises a first high-speed transceiver and a second high-speed transceiver and is used for triggering the second high-speed transceiver to read data packets from the first high-speed transceiver according to an address mapping relation between the first high-speed transceiver and the second high-speed transceiver when the first high-speed transceiver receives data packets, and forwarding the data packets; a first connector is electrically connected with the first high-speed transceiver; a second connector is electrically connected with the second high-speed transceiver; a first interface daughter card is electrically connected with the first connector and is used for receiving the data packets and transmitting the data packets to the first high-speed transceiver through the first connector; and a second interface daughter card is electrically connected with the second connector and is used for receiving data packets forwarded by the second high-speed transceiver and the second connector. With the heterogeneous multi-source high-speed data exchange adapter adopted, technical problems in communication between high-speed networks adopting different protocols in a high-performance computing platform can be solved.
Description
Technical field
The present embodiments relate to high performance computing system technical field, especially relate to a kind of different
Structure multi-source high-speed data exchange adaptive device.
Background technology
In order to meet growing application demand, high performance computing system scale constantly expands.
Along with the increase of system scale, the performance of internet becomes all the more the bottleneck that systematic function promotes.
In a big system, interference networks can be divided into again calculating node interconnection network, storage by function
Node interconnection network, management and control node interconnection network etc..Owing to its functional requirement is different, and it is subject to
It is limited to commercial criterion product, generally uses different procotols.Generally adopt between memory node
Interconnect with InfiniBand or Ethernet.Calculate internodal interconnection except using
Outside InfiniBand, also can use many customization high speed protocols, the tofu such as Fujitsu is mutual
Even etc..So, calculate between memory node from the communication calculated between node, different interference networks
The problem that the communication of node all there may be high speed protocol conversion.
At present, high speed protocol is changed generally following several solution: one, directly buys business
Use high speed protocol transition card, such as InfiniBand-PCIe card, 10,000,000,000 net-PCIe cards etc., its
Deficiency is that interface shape is single, and optional protocol conversion type is limited；Two, select
The protocol conversion chip such as RapidIO-PCIe bridge chip of IC manufacturer, carries out autonomous board level
Design, its deficiency is that design cycle length, cost are high；Three, select processor to carry out different association
The parsing of the bag of view and forwarding.The maximum deficiency of above-mentioned existing solution is underaction,
The need that communicate between multiple different agreement express network in high-performance calculation platform cannot be met simultaneously
Ask.
FPGA (Field-Programmable Gate Array) is a kind of programmable logic device
Part, has abundant logical resource and high-speed transceiver resource.Present inventor considers will
In the flexible configurability of FPGA and high-performance calculation platform multiple different agreement express network it
Between communication issue combine.
In view of this, the special proposition present invention.
Summary of the invention
The main purpose of the embodiment of the present invention is to provide a kind of isomerous multi-source high-speed data exchange
Adaptive device, to solve multiple different agreement HVN in high-performance calculation platform at least in part
The technical problem of communication between network.
To achieve these goals, according to an aspect of the invention, it is provided techniques below side
Case:
A kind of isomerous multi-source high-speed data exchange adaptive device, described device at least includes:
Processor, at least includes the first high-speed transceiver and the second high-speed transceiver, and is used for
In the case of described first high-speed transceiver receives packet, according to described first high-speed transceiver
And the address mapping relation between described second high-speed transceiver, trigger the described second transmitting-receiving at a high speed
Device reads described packet to described first high-speed transceiver, and forwards described packet；
First adapter, electrically connects with described first high-speed transceiver；
Second adapter, electrically connects with described second high-speed transceiver；
First interface subcard, electrically connects with described first adapter, and is used for receiving described data
Described packet is also transmitted to described first high-speed transceiver by bag through described first adapter；
Second interface subcard, electrically connects with described second adapter, and for receiving via described
Second high-speed transceiver and described second adapter forward the described packet of coming.
Compared with prior art, technique scheme at least has the advantages that
The embodiment of the present invention includes the first high-speed transceiver and the second high-speed transceiver by setting
Processor, the first and second adapters and the first and second interface subcards, first at a high speed
In the case of transceivers packet, according to the first high-speed transceiver and the second high-speed transceiver
Between address mapping relation, trigger the second high-speed transceiver to first high-speed transceiver read number
According to bag, and packet is forwarded, thus solve multiple difference in high-performance calculation platform
Communication issue between agreement express network, has and uses hardware resource high speed few, that support to connect
Mouthful protocol type is many, highly versatile, cost performance high, flexible configuration and high excellent of data bandwidth
Point.
Accompanying drawing explanation
Fig. 1 is to exchange adaptation dress according to the isomerous multi-source high-speed data shown in an exemplary embodiment
The structural representation put；
Fig. 2 is the connection signal according to a piece of FPGA shown in an exemplary embodiment with adapter
Figure；
Fig. 3 is according to the processor internal structure schematic diagram shown in an exemplary embodiment；
Fig. 4 is according to being fitted by the exchange of isomerous multi-source high-speed data shown in an exemplary embodiment
Equipped putting realizes the schematic diagram of data exchange between SRIO and ten thousand mbit ethernets；
Fig. 5 is according to being fitted by the exchange of isomerous multi-source high-speed data shown in an exemplary embodiment
Equipped putting realizes data between exchange network based on SRIO and exchange network based on 10GbE
The schematic diagram of exchange.
Detailed description of the invention
Below in conjunction with the accompanying drawings and the embodiment of the present invention is solved the technical problem that by specific embodiment,
The technical scheme used and the technique effect of realization carry out clear, complete description.Obviously,
Described embodiment is only a part of embodiment of the application, is not whole embodiments.
Based on the embodiment in the application, those of ordinary skill in the art are not paying creative work
Under premise, other equivalents all obtained or the embodiment of obvious modification all fall within the guarantor of the present invention
In the range of protecting.The embodiment of the present invention can be according to the multiple difference being defined and covered by claim
Mode embodies.
It should be noted that the art in description and claims of this specification and above-mentioned accompanying drawing
Language " first ", " second " etc. are for distinguishing similar object, without being used for describing spy
Fixed order or precedence.Should be appreciated that the data of so use in the appropriate case can be mutual
Change, in order to embodiments of the invention described herein can be with except here illustrating or describing
Order beyond those is implemented.Additionally, term " includes " and his any deformation, it is intended that
It is to cover non-exclusive comprising, such as, contains series of steps or the process of unit, side
Method, system, product or equipment are not necessarily limited to those steps or the unit clearly listed, but
Can include that the most clearly list or intrinsic for these processes, method, product or equipment
Other step or unit.
Also, it should be noted embodiment in the application and technical characteristic thereof are in the feelings do not conflicted
Can be combined under condition and or split and constitute technical scheme.
What Fig. 1 was exemplary shows a kind of isomerous multi-source high-speed data exchange adaptive device 10.
As it is shown in figure 1, this device 10 includes processor the 11, first and second adapter 12,13
With the first and second interface subcards 14,15.Wherein, processor at least includes that first receives at a high speed
Send out device 112 and the second high-speed transceiver 114, and for receiving at the first high-speed transceiver 112
In the case of packet, according to the first high-speed transceiver 112 and the second high-speed transceiver 114 it
Between address mapping relation, trigger the second high-speed transceiver 114 to the first high-speed transceiver 112
Read data packet, and packet is forwarded.First adapter 12 and the first transmitting-receiving at a high speed
Device 112 electrically connects.Second adapter 13 electrically connects with the second high-speed transceiver 114.First
Interface subcard 14 electrically connects with the first adapter 12, and is used for receiving packet and by packet
Transmit to the first high-speed transceiver 112 through the first adapter 12.Second interface subcard 15 and
Two adapters 13 electrically connect, and connect via the second high-speed transceiver 114 and second for receiving
Connect device 13 and forward the packet of coming.
Multiple different agreement high speed in high-performance calculation platform is solved by the embodiment of the present invention
Communication issue between network；And there is flexible configuration, advantage that data bandwidth is high.
It will be understood by those skilled in the art that above-mentioned isomerous multi-source high-speed data exchanges adaptive device
Also include some other known features, such as power module, clock module, RAM etc., in order to
Unnecessarily obscuring and embodiment of the disclosure, structure known to these is not shown in FIG. 1.
It should be understood that processor, adapter and interface subcard in Fig. 1 and high-speed transceiver
Quantity is only schematically.According to actual needs, can have any number of processor,
Adapter and interface subcard and high-speed transceiver.
In an optional embodiment, above-mentioned processor can also include controller and route mould
Block, and the first high-speed transceiver include first interface, first receive FIFO and first send
FIFO；Second high-speed transceiver includes that the second interface, the second reception FIFO and second send FIFO.
Wherein, first interface is used for receiving packet, and resolves packet, and by packet
Be stored in the first reception FIFO, and by source ID and purpose ID or source MAC and
Target MAC (Media Access Control) address or source IP address and purpose IP address are sent to controller.Routing module
For storing the address mapping relation between first interface and the second interface, carry out for controller
Address lookup.Controller is for based on source ID and purpose ID or source MAC and mesh
MAC Address or source IP address and purpose IP address, and the ground stored by routing module
Location mapping relations determine whether that the second interface sends packet, the most then trigger second and connect
Mouth reads the data in the first reception FIFO, and data are stored in the second transmission FIFO.The
Two interfaces are for the source ID received according to controller and purpose ID or source MAC
With target MAC (Media Access Control) address or source IP address and purpose IP address, send second in FIFO
The data of storage package and give out a contract for a project.
In the above-described embodiments, processor includes but not limited to FPGA
(Field-Programmable Gate Array, field programmable logic device), DSP
(Digital Signal Processing, digital signal processor) and single-chip microcomputer.Process
Device can support PCIe, SRIO, XAUI, ten thousand mbit ethernets, 40Gbit Ethernet, 100Gbit
The agreements such as Ethernet, and all use full-duplex mode.
Preferably, the first high-speed transceiver and the second high-speed transceiver can be that GTH type is received at a high speed
Send out device.
In the above-described embodiments, adapter includes but not limited to that QTH type adapter, FMC type are even
Connect device.
In actual applications, can arrange 4n high-speed transceiver is one group (n takes positive integer),
And this 4n high-speed transceiver is connected on same adapter.
In the above-described embodiments, resolve with organize bag all carry out according to standard agreement.
What Fig. 2 was exemplary shows the connection diagram of a piece of FPGA and adapter.Wherein,
Assume that FPGA20 has 32 high-speed transceivers.High-speed transceiver type is GTH.Every 8
High-speed transceiver is one group, and is connected to FMC adapter 21, on 22,23,24.
In the above-described embodiments, interface subcard includes but not limited to SFP (Small
The small-sized form factor of Form-factor Pluggable is pluggable)+interface subcard, QSFP (Quad
Small Form-factor Pluggable, the small-sized form factor of four-way is pluggable)/QSFP+
Interface subcard, 40Gbit ethernet PHY subcard, 100Gbit ethernet PHY subcard.Wherein,
SFP+ interface subcard supports ten thousand mbit ethernets etc..QSFP/QSFP+ interface subcard supports SRIO
(Serial Rapid IO, serial interlinkage framework), XAUI (Extended Auxi liary Unit
Interface, the interface of the auxiliary device of extension), ten thousand mbit ethernets etc..40Gbit ether
Net PHY subcard supports 40Gbit Ethernet.100Gbit ethernet PHY subcard supports 100Gbit
Ethernet.SRIO identifies port by No. ID.XAUI identifies port by MAC Address.
Ten thousand mbit ethernets, 40Gbit Ethernet, 100Gbit Ethernet pass through MAC Address or IP
Address identifies port.In specific implementation process, the available mode tabled look-up realize No. ID,
MAC Address, IP address are mated with corresponding port.
By use technique scheme, it is possible to realize multiple high-speed interface real time data receive,
Resolve and forward.Only need to select corresponding I/O interface subcard, the corresponding procotol of exampleization
Functional module, configures processor, can realize between required multiple express networks
Conversion.
Fig. 3 schematically illustrates processor internal structure schematic diagram.Wherein, processor includes
Oneth SRIO interface the 32, the 2nd SRIO interface the 35, the 3rd SRIO interface 34,10,000,000,000 with
Too network interface 33, controller 30, routing module 31, reception FIFO321,331,341,
351, FIFO322 is sent, 332,342,352.
Wherein, SRIO interface uses x4 pattern.The speed of each SRIO interface up to
25Gb/s.Ten thousand mbit ethernet interfaces take a GTH type high-speed transceiver, and speed is 10Gb/s.
Oneth SRIO interface the 32, the 2nd SRIO interface the 35, the 3rd SRIO interface 34 and 10,000,000,000 with
Too network interface 33 has an independent reception FIFO321, and 331,341,351 and send FIFO322,
332,342,352.Reception FIFO321,331,341,351 and transmission FIFO322,332,
342,352 all comprise interfaces different on multiple virtual fifo, and corresponding same interface subcard.
Controller determines to which interface (such as: the second interface) to send out by routing module
The working method sending out packet can have three kinds:
The first working method is the rule of protocol conversion one to one.To receive with SRIO interface
Packet to ten thousand mbit ethernet interfaces forward as a example by illustrate.SRIO interface 0 is by data
Be forwarded to 10,000,000,000 network interfaces 0, SRIO interface 1 forwards the data to 10,000,000,000 network interfaces 1 ...,
SRIO interface 5 forwards the data to 10,000,000,000 network interfaces 5.SRIO agreement uses No. ID and identifies
Different ports, and represent with 16bit number；10000000000 fidonetFido MAC Address identify not
Same port, each MAC Address is 48bit.Routing table is as shown in Table 1.
Table one:
If SRIO interface 0 receives a packet, its purpose ID is 80, and source ID is 01.
Controller is by searching routing table, and it is converted into the 10000000000 corresponding purposes of fidonetFido
MAC Address is AA:BB:CC:DD:80, and source MAC is AA:BB:CC:DD:
01.Then, this packet is forwarded by controller triggering 10,000,000,000 network interfaces 0.
If 10,000,000,000 network interfaces 0 receive a packet, its target MAC (Media Access Control) address is
AA:BB:CC:DD:21, source MAC is AA:BB:CC:DD:80.
Controller passes through routing module, and it is converted into corresponding purpose ID of SRIO agreement is 21,
Source ID is 80.Then, controller can trigger SRIO interface 0 this packet is carried out turn
Send out.
The second working method is: forward according to destination address, such as: SRIO interface 0
The packet received may be forwarded to 10,000,000,000 network interfaces 0, it is also possible to is forwarded to 10,000,000,000 nets
Mouth 1 ... or 10,000,000,000 network interfaces 7.
When SRIO protocol conversion become 10,000,000,000 fidonetFidos transmission time, according to 10,000,000,000 in routing table with
Too net mac address table selects destination interface；Pass when 10,000,000,000 fidonetFidos are converted into SRIO agreement
Time defeated, select destination interface according to the SRIO ID table in routing table.Wherein, each interface
The destination address scope being responsible for is as shown in Table 2.
Table two:
If SRIO interface 0 receives a packet, its purpose ID is 80, and source ID is 01.
Controller searches routing table by routing module, and its corresponding target MAC (Media Access Control) address is AA:
BB:CC:DD:80, source MAC is AA:BB:CC:DD:01, thus notifies ten thousand
This packet is forwarded by million network interfaces 3.
If 10,000,000,000 network interfaces 0 receive a packet, its target MAC (Media Access Control) address is
AA:BB:CC:DD:21, source MAC is AA:BB:CC:DD:80.Controller is by searching
Routing table two understands, and its corresponding purpose ID is 21, and source ID is 80, thus controller touches
Send out SRIO interface 1 this packet is forwarded.
The third working method is: forward according to source address.Such as: SRIO interface 0
The packet received may be forwarded to 10,000,000,000 network interfaces 0, it is also possible to is forwarded to 10,000,000,000 nets
Mouth 1 ... or 10,000,000,000 network interfaces 7.
When SRIO protocol conversion becomes 10,000,000,000 fidonetFido transmission, according to the SRIO ID in routing table
Table selects destination interface；When 10,000,000,000 fidonetFidos are converted into SRIO protocol transmission, according to road
Destination interface is selected by 10,000,000,000 net mac address tables in table.Wherein, each interface is responsible for
Destination address scope is as shown in Table 3.
Table three:
If SRIO interface 0 receives a packet, its purpose ID is 80, and source ID is 01.
Controller, by searching routing table three, notifies that this bag is carried out turning by 10,000,000,000 network interfaces 0
Sending out, its corresponding target MAC (Media Access Control) address is AA:BB:CC:DD:80, and source MAC is
AA:BB:CC:DD:01.
If 10,000,000,000 network interfaces 0 receive a packet, its target MAC (Media Access Control) address is
AA:BB:CC:DD:21, source MAC is AA:BB:CC:DD:80.
Controller is by searching routing table three, and this bag is carried out turning by notice SRIO interface 2
Sending out, its corresponding purpose ID is 21, and source ID is 80.
Below with a preferred embodiment, describe the transformation process between distinct interface in detail.
It is that as a example by ten thousand mbit ethernet agreements, its transformation process may is that by SRIO protocol conversion
After oneth SRIO interface 32 receives packet, packet is resolved, obtain data and
Routing iinformation；Then, the data after resolving are stored in reception FIFO321.Oneth SRIO connects
Routing iinformation (it includes source ID and purpose ID) is sent to controller 30 by mouth 32.
Then, controller 30, by routing module and according to source ID and purpose ID, finds out
With source ID and No. ID corresponding source MAC of purpose and target MAC (Media Access Control) address and 10,000,000,000 ether
Network interface 33.Controller inquires about whether ten thousand mbit ethernet interfaces 33 are ready to, if offhand
Good, inquire about the most always；If being ready to, then controller is by source MAC and purpose MAC
Address sends to ten thousand mbit ethernet interfaces 33, and triggers ten thousand mbit ethernet interfaces and go to read first
Data in the reception FIFO321 of SRIO interface 32, and it is stored in ten thousand mbit ethernet interfaces 33
Transmission FIFO332.Finally, ten thousand mbit ethernet interfaces 33 are according to source MAC and purpose
Data are packaged and give out a contract for a project by MAC Address.
Fig. 4 schematically illustrates the isomerous multi-source high speed number provided by the embodiment of the present invention
The data exchange between SRIO and ten thousand mbit ethernets is realized according to exchange adaptive device.
Here, single isomerous multi-source high-speed data exchange adaptive device is referred to as NIC (Network
Interface Card).Multiple SRIO port and multiple ten thousand mbit ethernet ports are had on NIC40.
SRIO port on NIC40 is linked in exchange network 41 based on SRIO.Based on SRIO
Exchange network 41 by each calculating node 42 interconnect.Ten thousand mbit ethernet ports on NIC40
Connect storage server 43.In the present embodiment, storage server 43 is used for storing each and calculates
The result of calculation of node 42.The agreement that NIC40 achieves between SRIO and ten thousand mbit ethernets turns
Change, it is possible to realize each and calculate high speed real-time Communication for Power between node and storage server, it is to avoid
Extra exchange network expense.
In the high-performance calculation application that system scale is the biggest, the number between different exchange networks
Also it is great according to exchange bandwidth.To this, the embodiment of the present invention can realize based on SRIO
Data exchange between exchange network and exchange network based on 10GbE, as shown in Figure 5.Logical
Cross NIC0, NIC1 ... NICn (n takes positive integer) achieves exchange network based on SRIO
Conversion between 51 and exchange network based on 10GbE 52.Exchange network based on SRIO
51 are connected with calculating node 53.Exchange network 52 based on 10GbE and memory node 54 phase
Even.Thus, it is achieved that calculate the data communication between node 53 and memory node 54.Based on
The exchange network exchange network based on SRIO 51 of SRIO and based on 10GbE (such as 10,000,000,000 with
Too net) exchange network 52 between data communication efficiency depend on NIC50.Can be by configuring n
Individual NIC50 meets system bandwidth demand.
In actual applications, any number of high speed protocol is if desired realized (such as: SRIO, ten thousand
Million nets, PCIe, XAUI etc.) between protocol conversion；Then need to connect phase on a processor
The interface subcard answered, and configure corresponding SRIO, 10,000,000,000 nets, PCIe, XAUI to processor
Etc. the bottom firmware of agreement, thus realize the conversion between high speed protocol.By configuring multiple connecing
Openning card, the embodiment of the present invention can be effectively improved data exchange total throughout (namely data
Bandwidth is high).
The present invention is not limited to above-mentioned embodiment, in the situation without departing substantially from flesh and blood of the present invention
Under, those of ordinary skill in the art it is contemplated that any deformation, improve or replace and each fall within this
The protection domain of invention.
Claims (4)
1. an isomerous multi-source high-speed data exchange adaptive device, it is characterised in that described dress
Put and at least include:
Processor, at least includes the first high-speed transceiver and the second high-speed transceiver, and is used for
In the case of described first high-speed transceiver receives packet, according to described first high-speed transceiver
And the address mapping relation between described second high-speed transceiver, trigger the described second transmitting-receiving at a high speed
Device reads described packet to described first high-speed transceiver, and forwards described packet；
First adapter, electrically connects with described first high-speed transceiver；
Second adapter, electrically connects with described second high-speed transceiver；
First interface subcard, electrically connects with described first adapter, and is used for receiving described data
Described packet is also transmitted to described first high-speed transceiver by bag through described first adapter；
Second interface subcard, electrically connects with described second adapter, and for receiving via described
Second high-speed transceiver and described second adapter forward the described packet of coming.
Device the most according to claim 1, it is characterised in that described processor also wraps
Including controller and routing module, described first high-speed transceiver includes first interface, the first reception
FIFO and first sends FIFO；Described second high-speed transceiver includes the second interface, second connects
Receive FIFO and second and send FIFO；Wherein:
Described first interface, is used for receiving described packet, and resolves described packet,
And described packet to be stored in described first reception FIFO, and by source ID and purpose ID
Number or source MAC and target MAC (Media Access Control) address or source IP address and purpose IP address send
To controller；
Described routing module, for storing the ground between described first interface and described second interface
Location mapping relations, carry out address lookup for described controller；
Described controller, for based on described source ID and purpose ID or source MAC
With target MAC (Media Access Control) address or source IP address and purpose IP address, and by described routing module
The described address mapping relation of storage determines whether that described second interface sends described data
Bag, the most then trigger described second interface and read the data in described first reception FIFO,
And described data are stored in described second transmission FIFO；
Described second interface, for the described source ID received according to described controller and mesh
No. ID or source MAC and target MAC (Media Access Control) address or source IP address and purpose IP ground
Location, sends described second the described data of storage in FIFO and packages and give out a contract for a project.
Device the most according to claim 1 and 2, it is characterised in that described processor
For FPGA.
Device the most according to claim 2, it is characterised in that described controller is also used
In determining whether according to the rule of protocol conversion one to one or destination address or source address
Described second interface sends described packet.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106973059A (en) * | 2017-04-01 | 2017-07-21 | 山东超越数控电子有限公司 | A kind of ten thousand mbit ethernets and Rapid I/O networks switching control system and method |
| CN108628800A (en) * | 2018-05-08 | 2018-10-09 | 济南浪潮高新科技投资发展有限公司 | A kind of the intelligence computation cluster and its configuration method of dynamic reconfigurable |
| CN110291512A (en) * | 2016-12-19 | 2019-09-27 | 赛峰电子与防务公司 | Equipment for being loaded into data from data source in computer processor unit |
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