CN101770987A - 半导体集成电路装置的制造方法 - Google Patents

半导体集成电路装置的制造方法 Download PDF

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CN101770987A
CN101770987A CN201010004653A CN201010004653A CN101770987A CN 101770987 A CN101770987 A CN 101770987A CN 201010004653 A CN201010004653 A CN 201010004653A CN 201010004653 A CN201010004653 A CN 201010004653A CN 101770987 A CN101770987 A CN 101770987A
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stress
integrated circuit
grid structure
electrode
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CN101770987B (zh
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柯志欣
李文钦
葛崇祜
陈宏玮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一半导体集成电路装置的制造方法，包括：形成一第一阱于半导体基底中；提供一第一栅极结构于半导体基底上，且第一栅极结构延伸离开半导体基底，其中包括提供一应力源于第一栅极结构中，应力源提供一第一应力于第一阱中，且还包括提供一第一栅极电极于第一栅极结构中并位于第一阱上且介于应力源与半导体基底之间；形成一第二阱于半导体基底中；提供一第二栅极结构于半导体基底上，第二栅极结构比第一栅极结构高，且其包括一第二栅极电极位于第二阱上；以及形成一材料层其与第二栅极结构接触且产生一第二应力于第二阱中。通过本发明的半导体集成电路装置及其制造方法能够对晶体管沟道施加所需的张应力或压应力。

Description

半导体集成电路装置的制造方法
本发明为申请号为“200810083369.8”且发明名称为“半导体集成电路装置及其制造方法”的中国申请的分案。
技术领域
本发明涉及半导体集成电路，尤其涉及半导体体电路中的应变沟道晶体管。
背景技术
MOS晶体管的性能可通过在沟道区中产生一适合的应力而提升，因此制造出所谓的应变沟道晶体管。例如可通过在晶体管的沟道区产生一张应力来增强n沟道晶体管的性能，以及可通过在晶体管的沟道区产生一压应力来增强p沟道晶体管的性能。
一些常见的沟道晶体管使用一高应力盖层(high-stress capping layer)覆盖于晶体管上，以产生需要的应力。其它常见的应变沟道晶体管则在栅极结构上使用硅化应力源，以产生需要的应力。在U.S.专利No.6,890,808中有在栅极结构上使用硅化应力源的叙述。
在使用CMOS晶体管对的集成电路中，需在p沟道晶体管的沟道区中提供一压应力，且在n沟道晶体管的沟道区中提供一张应力，才能提升两种类型的晶体管的性能。然而，使用传统方法很难制造出p沟道晶体管受到压应力而n沟道晶体管受到张应力的CMOS晶体管对。
因此业界急需改善制造半导体集成电路的方式，以对晶体管沟道施加所需的张应力或压应力。
发明内容
本发明提供一种半导体集成电路装置，包括：一半导体基底；一第一晶体管，其包括一第一阱形成于该半导体基底中与一第一栅极结构位于该半导体基底上且延伸离开该半导体基底，其中该第一栅极结构包括一第一栅极电极在该第一阱上，且该第一栅极结构还包括一应力源，其产生一第一应力于该第一阱中，且该第一栅极电极介于该应力源与半导体基底之间；一第二晶体管，其包括一第二阱形成在该半导体基底中与一第二栅极结构于该半导体基底上且延伸离开该半导体基底，其中该第二栅极结构包括一第二栅极电极在该第二阱上，且该第二栅极结构比该第一栅极结构高；以及一材料层，其与该第二栅极结构接触，该材料层产生一第二应力于该第二阱中。
根据所述的半导体集成电路装置，其中该第一应力为一压应力，且该第二应力为一张应力。
根据所述的半导体集成电路装置，其中该材料层包括一介电材料。
根据所述的半导体集成电路装置，其中该第二栅极结构至少比该第一栅极结构高
根据所述的半导体集成电路装置，其中该应力源与该第一栅极电极接触。
根据所述的半导体集成电路装置，其中该应力源包括一硅化材料形成于该第一栅极电极上。
根据所述的半导体集成电路装置，其中该第二栅极电极结构包括一硅化材料形成于该第二栅极电极上。
根据所述的半导体集成电路装置，其中该第一晶体管为一p沟道晶体管，且该第二晶体管为n沟道晶体管。
本发明还提供一种半导体集成电路装置的制造方法，包括：形成一第一阱于该半导体基底中；提供一第一栅极结构于该半导体基底上，且该第一栅极结构延伸离开该半导体基底，其中包括提供一应力源于该第一栅极结构中，该应力源提供一第一应力于该第一阱中，且还包括提供一第一栅极电极于该第一栅极结构中并位于该第一阱上且介于该应力源与该半导体基底之间；形成一第二阱于该半导体基底中；提供一第二栅极结构于该半导体基底上，该第二栅极结构比该第一栅极结构高，且其包括一第二栅极电极位于该第二阱上；以及形成一材料层其与该第二栅极结构接触且产生一第二应力于该第二阱中。
根据所述的半导体集成电路装置的制造方法，其中该提供该应力源的步骤包括提供该应力源与该第一栅极电极接触。
根据所述的半导体集成电路装置的制造方法，其中该提供该应力源的步骤包括形成一硅化材料于该第一栅极电极上。
根据所述的半导体集成电路装置的制造方法，其中该提供该第一栅极电极与第二栅极电极的步骤包括：提供一栅极电极材料，该栅极电极材料具有一第一部分与一第二部分；选择性蚀刻该第一部分以减少其部分高度；以及图案化该第一与第二部分以分别形成该第一栅极电极与第二栅极电极，其中该第一栅极电极比该第二栅极电极低。
通过本发明的半导体集成电路装置及其制造方法能够对晶体管沟道施加所需的张应力或压应力。
为了让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举优选实施例，并结合所附图示，作详细说明如下：
附图说明
图1显示本发明实施例的半导体集成电路装置。
图2显示一栅极电极沉积的步骤。
图3和图4显示注入栅极的步骤。
图5显示一栅极蚀刻步骤。
图6显示沉积一硬掩模的步骤。
图7显示通过图案化产生结构与栅极形成的步骤。
图8显示一间隙壁形成的步骤。
图9显示图8移除间隙壁后的剩余结构。
图10显示一硅化程序，其可用于图1的装置的制造。
其中，附图标记说明如下：
1    浅沟槽隔离结构
3    硅化物
5    P栅极
7    N栅极
a    N栅极7的高度
b    P栅极5的高度
9          栅极介电层
11         半导体基底
12         n沟道晶体管
13         p型阱
14         p沟道晶体管
15         n型阱
17         应力源
19         盖层
21         栅极电极材料
21A、21B   栅极电极材料21的一部分
31、41     栅极掩模
33         n型栅极电极注入
43         p型栅极电极注入
51         掩模
81         介电衬层
82         间隙壁
91         硅化程序
101        源/漏极区
具体实施方式
本发明实施例可通过调整应力的本质与大小来有效提升n沟道与p沟道晶体管的性能。如上所述，n沟道晶体管的沟道中需要引发一纵向(即源极至漏极的方向)张应力，p沟道晶体管的沟道中也需引发一纵向压应力。根据本发明的一些实施例，位于栅极电极上的多晶硅可引发纵向压应力于一p沟道晶体管的沟道中，且一张力盖层可引发一纵向张应力于n沟道晶体管的沟道中。而此实施例显示于图1。
在图1的结构中，n沟道晶体管12与p沟道晶体管14分别包括一p型阱13与一n型阱15。p型阱13与n型阱15形成在一半导体基底11中，且通过隔离结构-浅沟槽隔离结构(shallow trench isolation structure，STI)1来彼此分隔。晶体管14的栅极结构18包括一硅化物3位于晶体管14的栅极电极5(P栅极)上。晶体管12的栅极16具有一结构与栅极18的相似，但栅极结构16的栅极电极7(N栅极)从基底延伸的高度高于栅极电极5(P栅极)。
栅极电极7(N栅极)具有一高度“a”以及栅极电极5(P栅极)具有一高度“b”，其中b＜a。在一些实施例中，N栅极7的高度“a”至少大于P栅极5的高度“b”约
Figure G2010100046539D00051
。通过过度蚀刻(over-etching)P栅极电极可达到此高度的差异。如在U.S.专利No.6,890,808中所述，硅化物形成在经过度蚀刻的栅极电极(如图1中的P栅极5)上当可作一应力源，且产生一纵向压应力于晶体管沟道(图1中的p型沟道15)中。
如图1所示，盖层19(在一些实施例中为介电层)一般位于栅极结构16与18上，且包围着栅极结构16与18并与其接触。本技术领域的技术人员已知，可使用一盖层例如层19来引发位于其下方的晶体管沟道中所需的应力(张力或压力)。在一些实施例中，图1中的盖层19包括一纵向张应力于p型阱13中。因此通过盖层19与应力源17的结合，本发明实施例可于n型阱15中产生纵向压应力且在p型阱13中产生纵向张应力。
图2-图10概略显示根据本发明实施例，可用来制作图1结构的工艺。
首先，在半导体基底11中形成n型掺杂与p型掺杂阱(未显示)分别当作n沟道晶体管12与p沟道晶体管14的有源区。接着形成栅极介电层9，如图2所示。在许多实施例中可通过热氧化(thermal oxidation)、热氧化与氮化、化学气相沉积、溅射或本技术领域所熟知的其它技术来形成栅极介电层9。在许多实施例中，栅极介电层9包括一常见材料，例如二氧化硅、或氮氧化硅，且其厚度为约
Figure G2010100046539D00052
。在一实施例中，栅极氧化物的厚度约为8-10
Figure G2010100046539D00053
在另一实施例中，栅极介电层9包括一高介电常数材料，其等效的氧化厚度约为。高介电常数材料包括氧化铝(A12O3)、氧化铪(HfO2)、氧化锆(ZrO2)、氮氧化铪(HfON)、硅酸铪氧化合物(HfSiO4)、硅酸锆氧化合物(ZrSiO4)与氧化镧(La2O3)。
如图2所示，在形成栅极介电层9之后，沉积一栅极电极材料21。栅极电极材料21通过栅极介电层9与半导体基底11电性分离。在许多实施例中，栅极电极材料包括多晶硅、多晶硅锗、耐火材料、化合物与其它导电材料，其中耐火材料例如是钼与钨，而化合物例如是氮化钛。在一些实施例中，栅极电极材料为多晶硅，且栅极电极为氮氧化硅。在一些实施例中，可将注入物，如已知的功函数(workfunction)注入物导入栅极电极材料中以改变电极的功函数。
如图3所示，将一栅极掩模31沉积于栅极电极材料21的一部分21A上，此部分21A是用来形成p沟道晶体管14。之后，执行图3中的n型栅极电极注入33。接着，如图4所示，移除栅极掩模31，且沉积一栅极掩模41位于栅极电极材料21的一部分21B上，此部分21B是用来形成n沟道晶体管12。然后执行p型栅极电极注入(使用如硼、镓或铟)43。
如图5所示，在p型栅极电极注入之后，通过使用反应离子蚀刻(reactiveion etching)来蚀刻栅极电极材料21的一部分21A。p型电极的厚度为
Figure G2010100046539D00061
，而PMOS电极与NMOS电极的厚度比为1/5-4/5。p型电极的优选厚度为50nm，而PMOS电极与NMOS电极的优选厚度比为1/2。如图6所示，在蚀刻后的部分21A上沉积一掩模51。之后使用一般方式图案化与蚀刻，以产生栅极电极P栅极5与N栅极7。所产生的结构显示于图7中。在一实施例中，可利用含氯或硼的等离子体蚀刻来蚀刻栅极电极材料，以对栅极介电层提供高蚀刻选择比。
在形成栅极电极之后，形成源/漏极延伸区与口袋区(未显示)。在一实施例中，可以离子注入、等离子体浸没离子注入(plasma immersion ionimplantation，PIII)与其它本技术领域已知的技术来达成上述的工艺。接着，通过沉积与选择性蚀刻在栅极电极的侧壁上形成介电衬层(dielectric liner)81与间隙壁82，其剖面如图8所示。在一些实施例中，间隔材料(spacer material)包括一介电材料，例如氮化硅或二氧化硅。在间隙壁形成后注入深源/漏极区(未显示)。
如图9所示，在注入源/漏极区后，移除间隙壁82。之后，在一实施例中，执行一硅化程序91以形成硅化物，如图9所示。在一实施例中，可使用一自对准硅化物工艺(self-aligned silicide process)来形成硅化工艺的导电材料。在其它实施例中，可使用其它材料沉积工艺来形成硅化工艺的导电材料(此叙述代表不同硅化工艺)。如图10所示，硅化材料形成在源/漏极区101上以及栅极电极N栅极7与P栅极5上。
于栅极电极N栅极7与P栅极5上执行的硅化程序完成了晶体管12的栅极电极16与晶体管14的栅极电极18(参见图1)。
接着，将图1中的盖层19形成在晶体管12与14上。在一实施例中，盖层19为一高应力(high-stress)薄膜，例如氮化硅或任何其它适合高应力的材料。在许多实施例中，通过盖层19所给予的应力在本质上不是张力就是压力，且其范围约0.1-4Gpa。在一实施例中，可通过化学气相沉积来形成高应力薄膜，例如低压化学气相沉积(low-pressure CVD，LPCVD)或等离子体增强化学气相沉积(plasma-enhanced CVD，PECVD)。在形成盖层19之后，如同一般传统工艺，执行接触窗蚀刻、金属化(metallization)与钝化工艺(passivation)以完成元件的制作。
虽然本发明已以优选实施例揭示如上，然而其并非用以限定本发明，任何所属领域的技术人员，在不脱离本发明的精神和范围内，应当可作些许的更动与润饰，因此本发明的保护范围应当视后附的权利要求范围所界定的内容为准。

Claims (4)

1.一种半导体集成电路装置的制造方法，包括：
形成一第一阱于半导体基底中；
提供一第一栅极结构于该半导体基底上，且该第一栅极结构延伸离开该半导体基底，其中包括提供一应力源于该第一栅极结构中，该应力源提供一第一应力于该第一阱中，且还包括提供一第一栅极电极于该第一栅极结构中并位于该第一阱上且介于该应力源与该半导体基底之间；
形成一第二阱于该半导体基底中；
提供一第二栅极结构于该半导体基底上，该第二栅极结构比该第一栅极结构高，且其包括一第二栅极电极位于该第二阱上；以及
形成一材料层，其与该第二栅极结构接触且产生一第二应力于该第二阱中。
2.如权利要求1所述的半导体集成电路装置的制造方法，其中该提供该应力源的步骤包括提供该应力源与该第一栅极电极接触。    
3.如权利要求2所述的半导体集成电路装置的制造方法，其中该提供该应力源的步骤包括形成一硅化材料于该第一栅极电极上。
4.如权利要求1所述的半导体集成电路装置的制造方法，其中该提供该第一栅极电极与第二栅极电极的步骤包括：提供一栅极电极材料，该栅极电极材料具有一第一部分与一第二部分；选择性蚀刻该第一部分以减少其部分高度；以及图案化该第一与第二部分以分别形成该第一栅极电极与第二栅极电极，其中该第一栅极电极比该第二栅极电极低。
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