CN101741720A - Device and method for multichannel cell time slot multiplexing - Google Patents
Device and method for multichannel cell time slot multiplexing Download PDFInfo
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- CN101741720A CN101741720A CN200910209696.8A CN200910209696A CN101741720A CN 101741720 A CN101741720 A CN 101741720A CN 200910209696 A CN200910209696 A CN 200910209696A CN 101741720 A CN101741720 A CN 101741720A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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Abstract
The invention discloses a device and a method for multichannel cell time slot multiplexing. The device comprises an input memory module for caching and outputting the input cells, a strobe network module for strobe output of the cells from the input memory module, an output memory module for caching and parallel outputting the cells from the strobe network module and a control logic module for transmitting read-out signals to the input memory module when identifying cells are input the input memory module, controlling strobe output through preset beat signals and controlling the output memory module to parallel output the input data when identifying the strobe output is completed. With the technical scheme of the invention adopted, cells simultaneously or randomly input can be received and parallel output; in addition a plurality of multiplexers and memory submodules are used to replace a single large multiplexer, so that multiplexer dimension and circuit design difficulty are reduced.
Description
Technical field
The present invention relates to the communications field, more specifically, relate to a kind of apparatus and method of multichannel cell time slot multiplexing.
Background technology
In the modern communication network, become more and more general based on the exchange and the processing mode of cell (fixed length grouped data).Adopt cell to have the efficiency of transmission height, handle characteristic of simple as the communicating circuit of primitive.
Based on sharing storage is exchange chip a kind of structure commonly used, and the shared a slice memory space of a plurality of input/output ports of its inside has the memory rate with high advantage.
Existing patent documentation comprises: the patent No. is 200520078701.3 Chinese patent application " the multiplexing decomposition circuit of synchronous digital signal ".In this patent, the timeslot multiplex of multichannel cell adopts is to go here and there earlier and change, and carries out the method for gating again by multiplexer.
This method has following shortcoming:
1, under the continuous situation of signal on input and output clock synchronization and the input link, this method requires the cell on each input link to stagger each other the time of advent, and the cell on each bar link can not arrive simultaneously, has limited the flexibility of input.
2, under the bigger situation of cell length, it is very big that the circuit scale of multiplexer and time-delay can become, and increases the complexity of design.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of apparatus and method of multichannel cell time slot multiplexing, can receive simultaneously or the cell of input at random and itself and line output, and adopt a plurality of multiplexers and memory submodule to substitute single big multiplexer, reduced the scale and the circuit design difficulty of multiplexer.
For solving the problems of the technologies described above, according to an aspect of the present invention, provide a kind of device of multichannel cell time slot multiplexing, comprising: the input memory module is used for the cell of input is carried out buffer memory and output; The gating network module is used for the cell from the input memory module is carried out gating output; The output memory module is used for the cell from the gating network module is carried out buffer memory and line output cell; And control logic module, be used for inputing to input and sending read output signal to the input memory module during memory module defining cell, and be used for, and be used for when definite gating output has been finished control output memory module and will import data parallel and export with predetermined tempo signal controlling gating output.
Wherein, the input memory module comprises a plurality of first-in first-out FIFO submodules, is used for the multichannel cell of buffer memory input, and wherein, when cell was imported, the FIFO submodule generated the non-NULL status signal.
Wherein, control logic module comprises: the internal control signal generation module is used for predetermined tempo signal controlling gating network module; And output control signal generation module, be used under the control of predetermined tempo signal, generating the control signal that control output memory module will be imported data parallel output according to the non-NULL status signal.
Wherein, the gating network module comprises a plurality of multiplexers, is used under the control of the predetermined tempo signal of control logic module the cell gating output with input, and sends to the output memory module.
Wherein, the output memory module comprises a plurality of random access memory rams, is used for the cell of buffer memory gating network module gating output, and under the control of the control signal of control logic module and the line output cell.
According to another aspect of the present invention, provide a kind of method of multichannel cell time slot multiplexing, it is characterized in that, may further comprise the steps: the input memory module receives cell and exports the non-NULL status signal; Control logic module is controlled input memory module output cell after detecting the non-NULL status signal; Under the control of control logic module, the multiplexer of gating network inside modules is opened in turn, with will import according to endless form in the memory module cell respectively gating export to output memory module each submodule; And after the gating output of determining cell had been finished, each submodule was under the control of control logic module and the line output cell.
Wherein, control logic module is controlled input memory module output cell and is comprised after detecting the non-NULL status signal: the cell of buffer memory is exported in the mode of ladder.
Wherein, this method comprises that further control logic generates the output control signal, and determines according to the output control signal also whether the cell of line output is effective.
Wherein, comprise a plurality of fifo fifo modules in the input memory module, the cell of buffer memory exported in the mode of ladder comprises: for the cell among the FIFO, at a beat in the cycle, simultaneously the address number among the FIFO# 0 to FIFO#k is respectively n, n-1, n-2 ..., n-k and address number be that data in the address of nonnegative integer send to gating network, if n＞j+1, then since 0 circulation change, wherein, k is the numbering of FIFO, j+1 is the degree of depth of FIFO, and n is a positive integer.
Wherein, the gating output of determining cell has been finished and has been comprised: determine according to the frequency of the control signal of the length of cell and control logic module that gating is exported and finish.
The present invention utilizes the input storage to carry out buffer memory, adopts gating network and output storage to finish the timeslot multiplex of multichannel cell jointly, can handle the timeslot multiplex of multichannel cell under any relativeness in real time, has improved the processing flexibility.Simultaneously, adopt a plurality of multiplexers and memory submodule to substitute the method for single big multiplexer, reduced the scale and the circuit design difficulty of multiplexer.
This invention is suitable for the cell of all lengths, only the degree of depth of FIFO and the quantity of multiplexer and sub module stored is changed on circuit, has improved design flexibility.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the structural representation according to the device of multichannel cell time slot multiplexing of the present invention;
Fig. 2 is according to the inner structural representation of input storage of the present invention;
Fig. 3 is the structural representation according to gating network of the present invention inside;
Fig. 4 is according to the inner structural representation of output storage of the present invention;
Fig. 5 is the structural representation according to control logic of the present invention inside;
Fig. 6 is the schematic diagram according to data transmission method of the present invention;
Fig. 7 is the flow chart according to data processing method of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Multichannel timeslot multiplex device of the present invention comprises with lower module:
Input storage, it comprises several first-in first-out submodules (FIFO), in order to the input data on each link are carried out buffer memory, and under certain time sequence control, the data of inside is read out to gating network;
Gating network, it comprises several multiplexers (mux), in order to reading the data in the input storage, and it is transferred to the output memory module;
The output storage, it comprises several sub module stored, can be made of ram or register.In order to the data of corresponding multiplexer input in the reception gating network, and after certain time sequence, the multiplexing data of finishing are exported;
Control logic is in order to provide the control information of input memory module, gating network, output memory module;
Wherein, the flow direction of data is: input port, input storage, gating network, output storage, output port.
The method of multichannel timeslot multiplex of the present invention:
Steps A, the input memory module receives cell from input port
Step B, the FIFO in the input memory module carries out buffer memory to data, and provides the indication of FIFO non-NULL.
Step C, control logic is carried out poll to the data in 0～k FIFO, if this FIFO is that non-NULL is just read interior data, does not read if sky does not then carry out data.
Step D, the multiplexer of gating network inside is opened successively according to 0～j number order, and each multiplexer mails to corresponding output sub module stored in the mode of circulation respectively with the data in 0～k FIFO.
Step e, the sub module stored in the output memory module is kept in data, under the control of control logic counter, circularly with the output of the data in 0～j address in all sub module stored, finishes the timeslot multiplex of a plurality of passage cells.
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme:
As shown in Figure 1, the multiplexing device of cell of the present invention comprises:
As shown in Figure 2, input storage 101 inside are made of several FIFO, and the degree of depth of each FIFO is the length of 1 cell, and input links to each other with the input of whole device.FIFO is having received after data import, with the set of non-NULL index signal.FIFO is being carried out data when reading, control logic is inquired about the non-NULL index signal of FIFO according to the order of 0～k successively by the beat control signal, and the non-NULL index signal is offered control logic 104.
As shown in Figure 3, gating network 102 inside are made of several mux, and the input number of each mux is identical with the FIFO quantity that input is stored in 101, and the quantity of mux is identical with the FIFO degree of depth that input is stored in 101.When mux was controlled, control logic started mux by the beat control signal successively according to the order of 0～j.Each mux order by 0～K after starting is carried out gating output to input signal successively.
As shown in Figure 4, output storage 103 is made up of with register several RAM and is formed, and the input of each RAM links to each other with gating network, and the output of all RAM binds together, and has constituted the output of the multiplexing device of cell.The number of each RAM is identical with the length of cell, and the degree of depth is identical with the input port number of input storage 101.After accepting the data of gating network, 0#～j#RAM is exported together by control logic data that it is inner after the regular hour, finishes timeslot multiplex.
As shown in Figure 5, control logic 104 by internal control signal generate 501 and the output control signal generate 502 modules and form.The internal control signal generation module comprises counter and some control circuits, is used to produce the beat control signal, outputs to input storage 101, gating network 102 and output storage 103, and these 3 modules are controlled.Output control signal generation module 502 generates under the 501 cadence signal controls that produced at internal control signal, and the non-dummy status of FIFO in the input storage 101 is carried out gating output, generates the output control signal.
The data transmission method of multichannel cell time slot multiplexing device of the present invention as shown in Figure 6, the initial time slot_0 after the electrification reset after the data on No. 0 address on the FIFO# 0 are read, stores in No. 0 address on the ram# 0 constantly; At time slot_1 constantly, No. 1 address on the FIFO# 0 and two data on the 0th address on the FIFO#1 are read, store in No. 0 address and No. 1 address on the ram# 0 on the ram#1; After time slot_j, in each clock cycle among each FIFO all with sense data, wherein the data in the n address will store ram#n into (among the n≤j) in the m address among the FIFO#m.
As shown in Figure 7, for the cell data that enters multichannel cell time slot multiplexing device of the present invention, its handling process is as follows:
Step 1, the FIFO in the input storage 101 receives the cell data of input.
Step 2, the FIFO in the input storage 101 carries out buffer memory to cell, and waits for read output signal.
Step 3, the FIFO in the input storage 101 receives read output signal, and data are exported to gating network 102.
Multiplexer in the step 4, gating network carries out gating output with the signal that receives under the control of the cadence signal of control logic 104, be sent to output storage 103.
Step 5, the data that output storage 103 receives in the gating network, the row cache of going forward side by side.
Step 6 is judged output time, if reach, the data that then will export in the storage 103 are exported.
Step 7, the cell after timeslot multiplex finished is exported.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the device of a multichannel cell time slot multiplexing is characterized in that, comprising:
The input memory module is used for the cell of input is carried out buffer memory and output;
The gating network module is used for the described cell from described input memory module is carried out gating output;
The output memory module is used for the described cell from described gating network module is carried out buffer memory and the described cell of line output; And
Control logic module, be used for when defining cell and input to described input memory module, sending read output signal to described input memory module, and be used for, and be used for determining that described gating output controls described output memory module described input data parallel is exported when having finished with the output of the described gating of predetermined tempo signal controlling.
2. device according to claim 1 is characterized in that, described input memory module comprises a plurality of first-in first-out FIFO submodules, is used for the multichannel cell of buffer memory input,
Wherein, when cell was imported, described FIFO submodule generated the non-NULL status signal.
3. device according to claim 2 is characterized in that, described control logic module comprises:
The internal control signal generation module is used for the described gating network module of described predetermined tempo signal controlling; And
Output control signal generation module is used for generating the control signal of the described output memory module of control with described input data parallel output according to described non-NULL status signal under the control of described predetermined tempo signal.
4. device according to claim 3, it is characterized in that, described gating network module comprises a plurality of multiplexers, is used for the described cell gating output that will import under the control of the described predetermined tempo signal of described control logic module, and sends to described output memory module.
5. device according to claim 1, it is characterized in that, described output memory module comprises a plurality of random access memory rams, is used for the described cell of the described gating network module of buffer memory gating output, and under the control of the described control signal of described control logic module and the described cell of line output.
6. the method for a multichannel cell time slot multiplexing is characterized in that, may further comprise the steps: the input memory module receives cell and exports the non-NULL status signal;
Control logic module is controlled described input memory module and is exported described cell after detecting described non-NULL status signal;
Under the control of described control logic module, the multiplexer of gating network inside modules is opened in turn, with according to endless form with the cell in the described input memory module respectively gating export to output memory module each submodule; And
After the gating output of determining described cell had been finished, described each submodule was under the control of described control logic module and the described cell of line output.
7. method according to claim 6 is characterized in that, control logic module is controlled described input memory module and exported described cell and comprise after detecting described non-NULL status signal:
The described cell of buffer memory is exported in the mode of ladder.
8. method according to claim 6 is characterized in that, this method comprises that further described control logic generates the output control signal, and determines according to described output control signal also whether the described cell of line output is effective.
9. method according to claim 7 is characterized in that, comprises a plurality of fifo fifo modules in the described input memory module, the described cell of buffer memory is exported in the mode of ladder comprise:
For the cell among the FIFO, at a beat in the cycle, simultaneously the address number among the FIFO#0 to FIFO#k is respectively n, n-1, n-2 ..., n-k and address number be that data in the address of nonnegative integer send to gating network, if n＞j+1, then since 0 circulation change, wherein, k is the numbering of FIFO, j+1 is the degree of depth of FIFO, and n is a positive integer.
10. method according to claim 6 is characterized in that, the gating output of described definite described cell has been finished and comprised:
Determine that according to the frequency of the control signal of the length of described cell and control logic module described gating output finishes.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209696.8A CN101741720B (en) | 2009-11-06 | 2009-11-06 | Device and method for multichannel cell time slot multiplexing |
| PCT/CN2010/078258 WO2011054273A1 (en) | 2009-11-06 | 2010-10-29 | Device and method for multi-cell time slot multiplexing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200910209696.8A CN101741720B (en) | 2009-11-06 | 2009-11-06 | Device and method for multichannel cell time slot multiplexing |
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| CN101741720A true CN101741720A (en) | 2010-06-16 |
| CN101741720B CN101741720B (en) | 2013-01-16 |
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| WO (1) | WO2011054273A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011054273A1 (en) * | 2009-11-06 | 2011-05-12 | 中兴通讯股份有限公司 | Device and method for multi-cell time slot multiplexing |
| CN103731224A (en) * | 2012-10-11 | 2014-04-16 | 中兴通讯股份有限公司 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
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| GB9613473D0 (en) * | 1996-06-27 | 1996-08-28 | Mitel Corp | ATM cell transmit priority allocator |
| CN1233134C (en) * | 1997-05-21 | 2005-12-21 | 冲电气工业株式会社 | ATM signal exchange device |
| JP3774042B2 (en) * | 1997-09-11 | 2006-05-10 | 富士通株式会社 | Short cell multiplexer |
| US6999464B2 (en) * | 2001-08-28 | 2006-02-14 | Axiowave Networks, Inc. | Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor |
| CN100393052C (en) * | 2002-06-05 | 2008-06-04 | 中兴通讯股份有限公司 | Cell multiplexing circuit and method on asynchronous transmission mode |
| CN100444577C (en) * | 2004-09-06 | 2008-12-17 | 中兴通讯股份有限公司 | Data transmission converter of communication system |
| CN100407699C (en) * | 2005-04-01 | 2008-07-30 | 华为技术有限公司 | Signal disconnection and combination method and apparatus |
| CN2792037Y (en) * | 2005-04-29 | 2006-06-28 | 西安大唐电信有限公司 | Synchronous digital signal multiplexing-decomposition circuit |
| CN1819523A (en) * | 2006-02-20 | 2006-08-16 | 中国人民解放军国防科学技术大学 | Parallel interchanging switching designing method |
| CN101741720B (en) * | 2009-11-06 | 2013-01-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
-
2009
- 2009-11-06 CN CN200910209696.8A patent/CN101741720B/en active Active
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- 2010-10-29 WO PCT/CN2010/078258 patent/WO2011054273A1/en active Application Filing
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011054273A1 (en) * | 2009-11-06 | 2011-05-12 | 中兴通讯股份有限公司 | Device and method for multi-cell time slot multiplexing |
| CN103731224A (en) * | 2012-10-11 | 2014-04-16 | 中兴通讯股份有限公司 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
| WO2014056362A1 (en) * | 2012-10-11 | 2014-04-17 | 中兴通讯股份有限公司 | Device and method for supporting time-slot multiplexing of multichannel variable-length cells |
| CN103731224B (en) * | 2012-10-11 | 2017-02-08 | 中兴通讯股份有限公司 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
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| Publication number | Publication date |
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| CN101741720B (en) | 2013-01-16 |
| WO2011054273A1 (en) | 2011-05-12 |
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