CN2792037Y - Synchronous digital signal multiplexing-decomposition circuit - Google Patents
Synchronous digital signal multiplexing-decomposition circuit Download PDFInfo
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- CN2792037Y CN2792037Y CN 200520078701 CN200520078701U CN2792037Y CN 2792037 Y CN2792037 Y CN 2792037Y CN 200520078701 CN200520078701 CN 200520078701 CN 200520078701 U CN200520078701 U CN 200520078701U CN 2792037 Y CN2792037 Y CN 2792037Y
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Abstract
The utility model discloses a synchronous digital signal multiplexing-decomposition circuit, wherein a synchronous signal multiplexing circuit comprises a frame alignment delay circuit, a multiplexing address generation circuit, a multiplexing serial-to-parallel switching circuit and a multi-way selection circuit; a synchronous signal decomposition circuit comprises a decomposition address generation circuit and a decomposition serial-to-parallel switching circuit. The multiplexing serial-to-parallel switching circuit can realize the buffer memory of multi-way synchronous digital signals through a plurality of RAM memories, and the multi-way selection circuit realizes the framing of one-way serial synchronous digital signals. The decomposition serial-to-parallel switching circuit can realize the buffer memory of multibyte of the one-way synchronous digital signals through the RAM memories, and the one-way synchronous digital signals are decomposed into multi-way parallel synchronous digital signals. The multiplexing-decomposition circuit realizes the buffer memory of byte through the RAM memories, and can save a large amount of triggers. The utility model has the advantages of simple design of the circuit.
Description
Technical field
The utility model relates to the signal multiplexing decomposition circuit of field of telecommunications, is specifically related to a kind of multiplexing decomposition circuit of synchronous digital signal.
Background technology
At present, in field of telecommunications, the normal response mode of basic rate 2.048Mbps is widely used in communication network, but usually adopts 8.192Mbps and 32.768Mbps sync frame transmission technology in telecommunication exchange equipment internal transmission system.Adopt this transmission technology, will use the decomposition multiplex technology of multichannel synchronous digital signal, realize the conversion between the different rates frame signal, this decomposition multiplex technology generally comprises that bit is multiplexing, frame is multiplexing or byte is multiplexing, and bit is multiplexing seldom to be adopted in synchronous transmission is multiplexing.In actual applications, owing to a large amount of buffer memory of the multiplexing needs of frame is used not too extensive, and the byte multiplex technique flexibly, to take resource few and be widely adopted, publication number is the circuit that the Chinese patent literature " multiplexed decomposition circuit " of CN 1085710A provides the multiplexing decomposition of bit of the multiplexed decomposition of a kind of serial data stream, adopt serial-parallel conversion method, realize the bit buffer memory with d type flip flop.This multiplex circuit equally also is applicable to the multiplexing decomposition of synchronous digital signal byte, but the shift register that this circuit need take in the application of reality is made buffer memory, promptly take a large amount of d type flip flop unit, realize cost height, Logic Circuit Design complexity so require to adopt the large capacity field programmable gate array.
The utility model content
Defective or deficiency at above-mentioned prior art existence, the purpose of this utility model provides a kind of synchronous digital signal decomposition multiplex circuit, the RAM resource that makes full use of field programmable gate array realizes multiplexing decomposition, can save a large amount of d type flip flop unit, have characteristics such as Logic Circuit Design is simple, economical and practical.
For achieving the above object, the utility model provides a kind of synchronous digital signal decomposition multiplex circuit, and the synchronizing signal multiplex circuit comprises:
The frame synchronization delay circuit, input clock is connected with frame synchronization delay circuit input respectively with frame synchronizing signal, the frame synchronizing signal that the output of frame synchronization delay circuit is new;
Multiplexing address produces circuit, and new frame synchronizing signal is connected with the input of multiplexing address generation circuit respectively with clock, and multiplexing address produces multiplexing address signal, multiplexing writing address signal and the multiplexing enable signal read of circuit output;
Multiplexing serial-parallel conversion circuit, multiplexing address signal, multiplexing writing address signal, clock and the multichannel read treats that multiplexing digital synchronization signal is connected with the input of multiplexing serial-parallel conversion circuit, multiplexing serial-parallel conversion circuit output multi-path parallel signal;
Multiplexer circuit, multi-path parallel signal, clock and multiplexing enable signal are connected with the input of multiplexer circuit respectively, the single channel digital synchronization signal after multiplexer circuit output is multiplexing.
The synchronizing signal decomposition circuit comprises:
Decompose address production electric circuit, clock signal and frame synchronizing signal are connected to the input that decomposes address production electric circuit respectively, decompose address production electric circuit output branch and understand address signal, decompose writing address signal and decompose enable signal;
Decompose serial-parallel conversion circuit, clock, the input that divides deciphering address signal, decomposition writing address signal, decomposition enable signal and single channel synchronous digital signal to be decomposed to be connected to the decomposition serial-parallel conversion circuit respectively decompose the synchronous digital signal after serial-parallel conversion circuit is exported the multichannel decomposition.
Described frame synchronization delay circuit is formed by the coincidence counter cascade with door.
Described multiplexing address produces circuit, is made up of coincidence counter cascade and d type flip flop.
Described multiplexing serial-parallel conversion circuit is made up of RAM memory and d type flip flop.
Described multiplexer circuit is made up of multiselect one selector and d type flip flop.
Described multiplexing serial-parallel conversion circuit is by the buffer memory of a plurality of RAM memories realization multichannel synchronous digital signals, and multiplexer circuit is realized the framing of single channel serial synchronous digital signal.
Described decomposition address production electric circuit is made up of coincidence counter cascade, inverter and decoder.
Described decomposition serial-parallel conversion circuit is made up of the RAM memory.
Described decomposition serial-parallel conversion circuit is realized the multibyte buffer memory of single channel synchronous digital signal by the RAM memory, and is decomposed into the multidiameter delay synchronous digital signal.
Described frame synchronization delay circuit, multiplexing address produce circuit, multiplexing serial-parallel conversion circuit, multiplexer circuit, decomposition address production electric circuit and decompose serial-parallel conversion circuit is to be realized by a programmable logic device.
As the above, because multiplexing decomposition circuit described in the utility model has been realized the buffer memory of byte with the RAM memory, compare with the method that adopts shift register realization byte buffer memory, can save a large amount of d type flip flops, realize the multiplexing decomposition of multichannel synchronous digital signal so adopt the utility model, needn't select jumbo field programmable device, have characteristics such as circuit design is simple, economical and practical.
Description of drawings
Fig. 1 represents multiplex circuit functional module structure figure;
Fig. 2 represents decomposition circuit functional module structure figure;
Fig. 3 represents multiplex circuit embodiment functional module structure figure;
Fig. 4 represents the multiplex circuit timing diagram;
Fig. 5 represents decomposition circuit embodiment functional module structure figure;
Fig. 6 represents the decomposition circuit timing diagram;
Fig. 7～Figure 11 represents embodiment F PGA design principle figure.
Embodiment
Understand the utility model for clearer, the technical solution of the utility model is described further below in conjunction with accompanying drawing.Need to prove that present embodiment is example with a kind of four road 2.048Mbps synchronous digital signals to the multiplexing decomposition circuit of single channel 8.192Mbps synchronous digital signal, but present embodiment is not limited to this a kind of application mode.
As shown in Figure 1, the synchronizing signal multiplex circuit comprises: frame synchronization delay circuit, multiplexing address produce circuit, multiplexing serial-parallel conversion circuit and multiplexer circuit, multiplexing string and conversion are by the buffer memory of a plurality of RAM memories realization multichannel synchronous digital signals, and multiselect one selects circuit to realize the framing of single channel serial synchronous digital signal.
As shown in Figure 2, the synchronizing signal decomposition circuit comprises: decompose address production electric circuit and decompose serial-parallel conversion circuit, decompose serial-parallel conversion circuit and realize the multibyte buffer memory of single channel synchronous digital signal by the RAM memory, and be decomposed into the multidiameter delay synchronous digital signal.
As shown in Figure 3, multiplex circuit embodiment functional module comprises: the frame synchronization delay circuit, form the frame synchronization FCK signal of input 8.192M inversion clock N8MCLK and 8.192M, the 8.192M frame synchronizing signal 8MFCK after the output delay by the cascade of three 4 bit input coincidence counters; Multiplexing address produces circuit, form by two 4 bit input coincidence counter cascades and two d type flip flops, frame synchronizing signal 8MFCK after input 8.192M inversion clock N8MCLK and the delay exports multiplexing address signal, multiplexing writing address signal and the multiplexing enable signal read; Multiplexing serial-parallel conversion circuit is made up of four RAM memories, four d type flip flops; Multiplexer circuit selects a MUX and a d type flip flop to form by one four; Wherein each RAM memory size is 16 dark 1 bit widths, input 8.192M clock, frame synchronization FCK signal, multiplexing address signal, multiplexing writing address signal, multiplexing enable signal and four road 2.048M synchronous digital signals read, export one road 8.192M synchronous digital signal, promptly four road 2.048M synchronous digital signals are multiplexed with one road 8.192M synchronous digital signal.Four RAM memories are realized the byte buffer memory of four road synchronous digital signals respectively, and four select a selector to select output byte by the control of multiplexing enable signal, form the one-channel signal after multiplexing.Frame synchronization delay circuit input 8.192M inversion clock and frame synchronizing signal FCK export new frame synchronizing signal 8MFCK, postpone 95 clock cycle than FCK; Multiplexing address produces circuit, and input 8MFCK and 8.192M inversion clock, are read address R8A0-R8A3 and enabled control signal E0-E1 write address output W2A0-W2A3; In multiplexing serial-parallel conversion circuit, input 8.192M clock 8MCLK, write address, read the address, enable control signal and four road 2.048Mbps synchronous digital signals, export the 8.192Mbps synchronous digital signal after multiplexing, sequential relationship is as shown in Figure 4.
2MIN0 input data 11001001 write RAM0's successively
Data 11001001
Address 0000=0 0001=1 0010=2 0011=3 0100=4 0101=5 0110=6 0111=7
2MIN1 input data 10001100 write RAM1's successively
Data 10001100
Address 0000=0 0001=1 0010=2 0011=3 0100=4 0101=5 0110=6 0111=7
2MIN2 input data 00010011 write RAM2's successively
Data 00010011
Address 0000=0 0001=1 0010=2 0011=3 0100=4 0101=5 0110=6 0111=7
2MIN3 input data 00110110 write RAM3's successively
Data 00110110
Address 0000=0 0001=1 0010=2 0011=3 0100=4 0101=5 0110=6 0111=7
When write address was 0000-0111, reading the address was 1000-1111, and promptly the RAM data of reading this moment are the data that write preceding 32 clock cycle; After 32 8.192M clocks, when write address is 1000-1111, reading the address is 0000-0111, this moment read simultaneously RAM0 11001001, RAM1 10001100, RAM2 00010011, RAM3 00110110, trigger 0-trigger 3 is as the adjustment of sequential, multiplexing enable signal E0 and E1 select the data output of which RAM among the control RAM0-RAM3, realize the parallel serial output single channel synchronous digital signal that changes.
First 8 8.192M clock E0E1=00 selector output RAM0 data 11001001
Second 8 8.192M clock E0E1=01 selector output RAM1 data 10001100
The 3rd 8 8.192M clock E0E1=10 selector output RAM2 data 00010011
The 4th 8 8.192M clock E0E1=11 selector output RAM3 data 00110110
As shown in Figure 5, the synchronizing signal decomposition circuit comprises: decompose address production electric circuit, form by two 4 bit input coincidence counter cascades and a 2-4 line decoder, input 8.192M inversion clock and frame synchronization FCK signal, output divide to be understood address signal, decompose writing address signal and decomposes enable signal; Decompose serial-parallel conversion circuit, form by four RAM memories, wherein each RAM memory size is 16 bit depth, 1 bit widths, input 8.192M clock, frame synchronization FCK signal, branch are understood address signal, decompose writing address signal, are decomposed enable signal and single channel 8.192M synchronous digital signal, export four road 2.048M with the step number subsignal, promptly single channel 8.192M synchronous digital signal is decomposed into four road 2.048M synchronous digital signals.Four RAM memories are realized the buffer memory of four bytes of single channel synchronous digital signal, are converted to the output of four road parallel signals.
Decompose address production electric circuit, synchronous FCK of incoming frame and 8.192M inversion clock, are read address R2A0-R2A3 and are selected control signal G0-G4 write address output W8A0-W8A3; Decompose in the serial-parallel conversion circuit, input 8.192M clock 8MCLK, write address W8A0-W8A3, read address R2A0-R2A3, select the digital signal of control signal G0-G4 and single channel 8.192Mbps, four road 2.048Mbps synchronous digital signals that output is decomposed, sequential relationship such as Fig. 6.
First 8 8.192M clock G0 effective 11001001 write RAMa
Second 8 8.192M clock G1 effective 10001100 write RAMb
The 3rd 8 8.192M clock G2 effective 00010011 write RAMc
The 4th 8 8.192M clock G3 effective 00110110 write RAMd
Behind 32 clocks, as write address 1000-1111, read the address this moment is 0000-0111, read simultaneously RAMa 11001001, RAMb 10001100,00010011 and the RAMd of RAMc 00110110, the data that clock synchronization is read RAMa-RAMd are four road 2.048M synchronous digital signals after the decomposition.
Fig. 7～11 provide embodiment F PGA design principle figure, and wherein Fig. 7 is the frame synchronization delay circuit, and Fig. 8 produces circuit for multiplexing address, and Fig. 9 is multiplexing serial-parallel conversion circuit and multiplexer circuit; Figure 10 is for decomposing address production electric circuit, and Figure 11 is for decomposing serial-parallel conversion circuit.FPGA adopts the Spartan XCS05 of Xilinx to realize, U1 wherein, U2, U9, U10 is that CB4CLE is a coincidence counter, U4, U5, U6 is the X74161 coincidence counter, U3, U11, U13, U15 are not gates, and U12 is a 2-4 line decoder, U7 is a four-input terminal and door, and U8 is seven inputs and door, and U14 four selects a selector, D1-D7 is a d type flip flop, and RAM0-RAM3 is multiplexing RAM memory, and RAMa-RAMd is for decomposing the RAM memory.
Claims (10)
1, the multiplexing decomposition circuit of a kind of synchronous digital signal, it is characterized in that the synchronizing signal multiplex circuit comprises: the frame synchronization delay circuit, input clock is connected with frame synchronization delay circuit input respectively with frame synchronizing signal, the frame synchronizing signal that the output of frame synchronization delay circuit is new;
Multiplexing address produces circuit, and new frame synchronizing signal is connected with the input of multiplexing address generation circuit respectively with clock, and multiplexing address produces multiplexing address signal, multiplexing writing address signal and the selection enable signal read of circuit output;
Multiplexing serial-parallel conversion circuit, multiplexing address signal, multiplexing writing address signal, clock and the multichannel read treats that multiplexing digital synchronization signal is connected with multiplexing serial-parallel conversion circuit input, multiplexing serial-parallel conversion circuit output multi-path parallel signal;
Multiplexer circuit, multi-path parallel signal, clock and multiplexing enable signal are connected with the multiplexer circuit input respectively, the single channel digital synchronization signal after multiplexer circuit output is multiplexing;
The synchronizing signal decomposition circuit comprises:
Decompose address production electric circuit, clock signal and frame synchronizing signal are connected to the input that decomposes address production electric circuit respectively, decompose address production electric circuit output branch and understand address signal, decompose writing address signal and decompose enable signal;
Decompose serial-parallel conversion circuit, clock, the input that divides deciphering address signal, decomposition writing address signal, decomposition enable signal and single channel synchronous digital signal to be decomposed to be connected to the decomposition serial-parallel conversion circuit respectively decompose the same step number subsignal after serial-parallel conversion circuit is exported the multichannel decomposition.
2, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that described frame synchronization delay circuit forms by the coincidence counter cascade with door.
3, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that described multiplexing address produces circuit and is made up of coincidence counter cascade and d type flip flop.
4, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that described multiplexing serial-parallel conversion circuit is made up of RAM memory and d type flip flop.
5, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that described multiplexer circuit is made up of multiselect one selector and d type flip flop.
6, according to claim 1 or the multiplexing decomposition circuit of 4 or 5 described synchronous digital signals, it is characterized in that the buffer memory of described multiplexing serial-parallel conversion circuit by a plurality of RAM memories realization multichannel synchronous digital signals, multiplexer circuit is realized the framing of single channel serial synchronous digital signal.
7, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that described decomposition address production electric circuit is made up of coincidence counter cascade, inverter and decoder.
8, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that: described decomposition serial-parallel conversion circuit is made up of the RAM memory.
9, according to claim 1 or the multiplexing decomposition circuit of 8 described synchronous digital signals, it is characterized in that: described decomposition serial-parallel conversion circuit is realized the multibyte buffer memory of single channel synchronous digital signal by the RAM memory, and is decomposed into the multidiameter delay synchronous digital signal.
10, the multiplexing decomposition circuit of synchronous digital signal according to claim 1 is characterized in that: described frame synchronization delay circuit, multiplexing address produce circuit, multiplexing serial-parallel conversion circuit, multiplexer circuit, decomposition address production electric circuit, decompose serial-parallel conversion circuit is to be realized by a programmable logic device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200520078701 CN2792037Y (en) | 2005-04-29 | 2005-04-29 | Synchronous digital signal multiplexing-decomposition circuit |
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| CN 200520078701 CN2792037Y (en) | 2005-04-29 | 2005-04-29 | Synchronous digital signal multiplexing-decomposition circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232361B (en) * | 2008-01-11 | 2011-03-16 | 北京邮电大学 | Method and apparatus for multiplexing multi-path same grade heterogeny data |
| CN102117253A (en) * | 2010-12-30 | 2011-07-06 | 中国人民解放军海军工程大学 | System and method thereof for multiplexing inter-integrated circuit (IIC) devices with identical address |
| CN101741720B (en) * | 2009-11-06 | 2013-01-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
| CN103714031A (en) * | 2013-12-26 | 2014-04-09 | 中国电子科技集团公司第四十一研究所 | Method for achieving control over HDQ16 bus based on FPGA |
-
2005
- 2005-04-29 CN CN 200520078701 patent/CN2792037Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232361B (en) * | 2008-01-11 | 2011-03-16 | 北京邮电大学 | Method and apparatus for multiplexing multi-path same grade heterogeny data |
| CN101741720B (en) * | 2009-11-06 | 2013-01-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
| CN102117253A (en) * | 2010-12-30 | 2011-07-06 | 中国人民解放军海军工程大学 | System and method thereof for multiplexing inter-integrated circuit (IIC) devices with identical address |
| CN102117253B (en) * | 2010-12-30 | 2013-01-02 | 中国人民解放军海军工程大学 | System and method thereof for multiplexing inter-integrated circuit (IIC) devices with identical address |
| CN103714031A (en) * | 2013-12-26 | 2014-04-09 | 中国电子科技集团公司第四十一研究所 | Method for achieving control over HDQ16 bus based on FPGA |
| CN103714031B (en) * | 2013-12-26 | 2016-03-09 | 中国电子科技集团公司第四十一研究所 | A kind of control method of the HDQ16 bus based on FPGA |
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Expiration termination date: 20150429 Granted publication date: 20060628 |