CN1874292A - Exchange system based on crossbars with buffer - Google Patents
Exchange system based on crossbars with buffer Download PDFInfo
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- CN1874292A CN1874292A CNA2006100786293A CN200610078629A CN1874292A CN 1874292 A CN1874292 A CN 1874292A CN A2006100786293 A CNA2006100786293 A CN A2006100786293A CN 200610078629 A CN200610078629 A CN 200610078629A CN 1874292 A CN1874292 A CN 1874292A
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Abstract
The switching system thereof comprises an input port, a switching unit and an output port. Said input and output ports are respectively connected to a high speed series bus through a memory at the input, a memory at the output and said switch unit; said switch unit is made by using field programmable gate array IC or a dedicated application IC, and has the amounts of the entrances and exits twice than the amounts of the input and output ports. Wherein, said memory at the input comprises two static random access memories (SRAMs) or two first in first out (FIFO) memories, and sets a buffer queue for distinguishing output ports according to the amounts of output ports. Said memory at the output comprises two synchronization random access memories (DRAMs) or two FIFO memories, and sets a buffer queue for distinguishing priorities. Said input and the output each comprise two serial-parallel converters and two parallel -serial converters.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of switching system based on band buffer memory cross bar switch.
Background technology
Along with rapid development of network technology, people have higher requirement to router, and switching system also is faced with bigger challenge as the core of router.Switching system needs increasing exchange capacity can be provided on the one hand, and switching system needs to provide at the performance requirement of different business service quality guarantee in various degree on the other hand.
At present, commercial routers mostly makes up switching system based on cross bar switch (crossbar), and this is because cross bar switch has clog-free characteristic, realizes simply, and has ripe commercial chip directly to use, and the structure of this cross bar switch is shown in Fig. 5 A.The switching system that prior art makes up based on cross bar switch can be according to the difference of queuing mechanism, roughly be divided into output work queue's switching system, input queue's switching system, associating input/output queue switching system and Parallel packet switch system, its operation principle is described below respectively:
1, output work queue's switching system is meant that all buffering area formations are positioned over output port, and as shown in Figure 1, packets of information 110 enters input port 101, is sent to the buffer queue 105 of output port 104 after crosspoint 103 exchanges, is output scheduling subsequently.Because output work queue's switching system does not have the buffering area formation at input port 101, so all arrive the buffer queue 105 that packets of information 110 must be sent to output port 104 immediately.Output work queue's switching system very advantageous on performance can provide the service quality guarantee of aspects such as throughput, speed, time delay, so often is used as the normative reference of other switching systems energy.
Yet, output work queue's switching system for N * N, if wish that in a time slot N packets of information arrives same output port simultaneously, also promptly in a time slot, receive N packets of information, the memory of output buffer queue 105 just must be finished N time and writes in a time slot so, and the N that the speed that is sent to the crosspoint internal wiring of memory so also is necessary for this packets of information arrival rate doubly.Therefore, the crosspoint 103 that it is N that output work queue's switching system need be provided with an inner speed-up ratio, and be used to realize that the memory of output buffer queue 105 also must work in the extraordinarily fast state of N.These requirements make the realization cost prohibitive of output work queue's switching system when making up big capacity switching system can't realize sometimes even at all.Therefore, output work queue's switching system is not suitable for making up big capacity switching system.
2, with output work queue's switching system comparatively speaking, input queue's switching system provides a kind of very economic solution for making up big capacity switching system.Input queue's switching system is meant that all buffer queues are positioned over input port, as shown in Figure 2, packets of information 210 enters the buffer queue 202 of input port 201, is sent to crosspoint 203 exchanges by suitable scheduling mechanism, is sent to output port 204 outputs subsequently.Yet simple input queue's switching system can cause low throughput.This is because each input port 201 has only a buffer queue 202, and the head of the queue obstruction will take place when two formation header message bags will arrive same output port 204 simultaneously, and rear of queue will arrive the packets of information of idle output port and also can't send.In order to overcome the low shortcoming of throughput, input queue's switching system adopts virtual output work queue mode usually, and promptly for the switching network of N * N, each input port is provided with N buffer queue, respectively a corresponding N output port.The output port unanimity of all packets of information in each buffer queue can be sent to crosspoint from other buffer queue schedule information bags when the partial buffer formation takes place to block like this, the generation of therefore having avoided head of the queue to block.Input queue's switching system adopts virtual output work queue mode can improve the bandwidth of memory utilance, avoids head of the queue to block, thereby can be used for making up big capacity router, this switching system of the most employings of at present big capacity commercial routers.
Yet input queue's switching system need adopt central controlled scheduling mechanism, and this makes that the service quality guarantee that provides at input queue's switching system is very complicated.For example (MWM) dispatching algorithm is verified that 100% throughput can be provided for weight limit coupling, yet its complexity is O (N
3Log N), and provides service quality guarantee further also can increase the complexity of dispatching algorithm again, be difficult to have realistic meaning.Therefore input queue's switching system can only provide the priority service of coarseness usually, and its time delay, delay variation characteristic are all not as output work queue's switching system.
3, associating input/output queue switching system has carried out compromise preferably to output work queue's switching system and input queue's switching system, its basic thought is to make the acceleration mode that is operated in input queue's switching system to a certain degree, input port and output port at switching system are provided with buffer queue respectively, thereby reduce the complexity of dispatching algorithm.Associating input/output queue switching system as shown in Figure 3, packets of information 310 enters the buffer queue 302 of input port 301, be sent to crosspoint 303 exchanges by suitable input scheduling mechanism, be sent to the buffer queue 305 of output port 304 subsequently, again through suitable output scheduling mechanism scheduling output.Compare with the input queue switching system, associating input/output queue switching system can reduce the complexity of dispatching algorithm really, and the service quality guarantee of aspects such as throughput, speed, time delay can be provided.
Yet switching system simulation output work queue of associating input/output queue switching system need adopt centralized matching algorithm equally, still has high implementation complexity, is difficult in the engineering design and realizes, therefore only has theory significance.
4, the Parallel packet switch system is by carrying out parallel processing with traffic load sharing to a plurality of exchange planes, thereby further reduces the requirement to storage access speed and crosspoint operating rate, therefore can be used for making up the switching system of vast capacity.The Parallel packet switch system as shown in Figure 4, this system utilizes the less crosspoint of a plurality of capacity, for example: sub-crosspoint 411,412,413 is set up a jumbo switching system 410 by parallel processing, carry out traffic assignments by input port and realize load balance, parallel processing in each small-sized switching system, pass through the multiplexing of output port then, thereby make its equivalence or simulate output work queue's switching system.The Parallel packet switch system has very significant meaning for the switching system that makes up vast capacity.
Yet the parallel processing on a plurality of planes will cause the complexity in the control and management in the system, and in addition, parallel processing will cause the out of order problem of packets of information, and addressing this problem needs the extra hardware spending that switching system is realized that increases.Therefore, the Parallel packet switch system generally only just is used when other switching systems can't reach the router design capacity requirement.
In sum, all have separately deficiency based on the switching system of cross bar switch, it is that at all the cross bar switch that is adopted has certain limitation.In general the processing of the fixed length bag that cross bar switch can only support information Bao Changwei one fixed constant value, and the packets of information in the live network is the elongated bag of Bao Changwei variable value.Therefore, the deficiency that overcomes cross bar switch could fundamentally be improved the performance of switching system.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of switching system based on band buffer memory cross bar switch, to realize to support the processing of elongated packets of information, need not to quicken to simulate the output work queue's switching system that adopts any dispatching algorithm at aspect of performance, thereby overcome the deficiency of prior art based on the various switching systems of cross bar switch.
The technical scheme that realizes the object of the invention is as follows:
A kind of switching system based on band buffer memory cross bar switch, it comprises input port, crosspoint, reaches output port, and wherein: described input port is connected with this crosspoint with the output memory cell by the input memory cell respectively with output port; Described crosspoint is band buffer memory cross bar switch, and the number of its entrance and exit is respectively the twice of input port and output port number.
Wherein, described input memory cell comprises two static random access memorys or many formations pushup storage.
Wherein, described input memory cell comprises two strings and modular converter, is used for the serial data from input port is converted to the parallel mode write memory; And two parallel serial conversion modules, be used for that the parallel data that memory is read is converted to serial mode and be sent to crosspoint.
Wherein, described memory is provided with the buffer queue of distinguishing output port according to output port number.
Wherein, described output memory cell comprises two synchronous DRAMs or many formations pushup storage.
Wherein, described output memory cell comprises two strings and modular converter, is used for the serial data from the exchange unit is converted to the parallel mode write memory; And two parallel serial conversion modules, be used for that the parallel data that memory is read is converted to serial mode and be sent to output port.
Wherein, described memory is provided with the buffer queue of distinguishing priority.
Wherein, described crosspoint is realized by field programmable gate array.
Wherein, described crosspoint is realized by the integrated circuit of application-specific.
Wherein, described input port, input memory cell, crosspoint, output memory cell, and output port between adopt high-speed serial bus to connect.
The invention provides a kind of switching system based on band buffer memory cross bar switch, owing to adopt band buffer memory cross bar switch unit in return, the buffer unit of its each crossover node can bag the longest of buffer memory, thereby can be good at supporting the processing of elongated packets of information, thereby avoided the expense of burst reorganization, improved treatment effeciency.
In addition, the present invention is by disposing respectively and input memory cell that is connected with the buffer memory cross bar switch and output memory cell at input port and output port, and the number of the entrance and exit of band buffer memory cross bar switch is respectively the twice of input port and output port number, thereby guarantees to provide sufficient switching bandwidth for input port to output port.
By be provided with two strings and modular converter and two parallel serial conversion modules in the input memory cell, be provided with two strings and modular converter and two parallel serial conversion modules in the output memory cell accordingly, thereby realize that better the data between memory and the crosspoint transmit.
Because crosspoint can provide sufficient switching bandwidth, the buffer memory capacity demand of input memory cell is less, so two memories of each input port adopt static random access memory; In order better to support to distinguish the service of priority, the output memory cell need be provided with the memory of big buffer memory capacity, so two memories of each output port adopt synchronous DRAM.
In addition, by the buffer queue of distinguishing output port is set in input static random access memory inside, when the partial buffer formation takes place to block, can be sent to crosspoint, thereby avoid head of the queue to block from other buffer queue schedule information bags; And the buffer queue of distinguishing priority is set in output synchronous DRAM inside, make switching system of the present invention that in various degree service quality guarantee can be provided at the QoS requirement of different business.
In sum, switching system of the present invention is in the performance very advantageous of leavening dough, because memory and crosspoint all need not to work in acceleration mode, can simulate the output work queue's switching system that adopts any dispatching algorithm, so it is embodied as this and realizes that difficulty is all lower.
Below in conjunction with the drawings and specific embodiments the present invention is further described.
Description of drawings
Fig. 1 is a prior art output work queue switching system;
Fig. 2 is a prior art input queue switching system;
Fig. 3 is a prior art associating input/output queue switching system;
Fig. 4 is a prior art Parallel packet switch system;
Fig. 5 A, 5B are respectively cross bar switch and band buffer memory cross bar switch schematic diagram;
Fig. 6 is an embodiment of the invention hardware physical structure schematic diagram;
Fig. 7 is the switching system structure chart of the embodiment of the invention based on band buffer memory cross bar switch;
Fig. 8 is the switching system workflow diagram of the embodiment of the invention based on band buffer memory cross bar switch.
Embodiment
The present invention has adopted a kind of new thinking, the buffer memory of one constant volume promptly is set in the crosspoint inside of switching system, and, realize that the buffer memory of low capacity is not difficult in that crosspoint is inner along with the raising of chip technology level, be typically band buffer memory cross bar switch crosspoint.Fig. 5 B has provided the schematic diagram of band buffer memory cross bar switch, and it is to improve on the basis of the cross bar switch of no buffer memory, at each crossover node a little buffer memory is set, and is used for the packet that buffer memory is sent into from input interface.
The present invention is based on the n * n switching system of band buffer memory cross bar switch, wherein n can be any natural number, and described switching system is made of input port 1, input memory cell 2, crosspoint 3, output memory cell 4 and output port 5.Described input port 1, input memory cell 2, crosspoint 3, output memory cell 4, and output port 5 between adopt high-speed serial bus to connect.The number of the entrance and exit of the band buffer memory cross bar switch that described switching system adopts is respectively the twice of input port and output port number, and promptly the entrance and exit with the buffer memory cross bar switch is respectively 2n.
One embodiment of the present invention are 8 * 8 switching systems based on band buffer memory cross bar switch, and the physical structure of this switching system as shown in Figure 6.Wherein: crosspoint adopts the ASIC(Application Specific Integrated Circuit) (ASIC:Application Specific Integrated Circuit) of 16 * 16 band buffer memory cross bar switches to realize, but bag the longest of its each crossover node buffer unit buffer memory.The number of the entrance and exit of described band buffer memory cross bar switch is respectively the twice of input port and output port number, promptly the number of the entrance and exit of band buffer memory cross bar switch in the present embodiment is respectively 16, and the number of input port and output port is respectively 8.
Wherein, described input memory cell 2 comprises two strings and modular converter, two memories and two parallel serial conversion modules, and this string and modular converter are used for the serial data from input port is converted to the parallel mode write memory; This parallel serial conversion module is used for that the parallel data that memory is read is converted to serial mode and is sent to crosspoint.Corresponding with it, described output memory cell 4 also comprises two strings and modular converter, two memories and two parallel serial conversion modules, and this string and modular converter are used for the serial data from the exchange unit is converted to the parallel mode write memory; This parallel serial conversion module is used for converting the parallel data that memory is read to serial mode and is sent to output port.Because crosspoint provides sufficient switching bandwidth, the buffer memory capacity demand of input memory cell is less, so two memories of each input port adopt static random access memory (SRAM:Static Random AccessMemory) to realize.In order better to support to distinguish the service of priority, the output memory cell need be provided with the memory of big buffer memory capacity, so two memories of each output port adopt synchronous DRAM (SDRAM:Synchronous Dynamic Random Access Memory) to realize.
Fig. 7 has provided the concrete structure of the switching system that the present invention is based on band buffer memory cross bar switch.Because crosspoint adopts 16 * 16 band buffer memory cross bar switch realization, an input port of per two corresponding switching systems of inlet of crosspoint, therefore output ports of per two corresponding switching systems of outlet of crosspoint provide sufficient switching bandwidth for input port to the exchange of output port.Block for fear of inlet, the buffer queue of distinguishing output port is set in each static random access memory inside of input, promptly 8 buffer queues are set, respectively corresponding 8 output ports in each static random access memory inside at band buffered cross switch.Like this, when the partial buffer formation took place to block, packets of information can be sent to crosspoint from other buffer queue scheduling.In addition, the identical content of buffer memory in two memories of each input, when one of them memory is read a packets of information, another memory upgrades this packets of information of deletion by the pointer of memory.Accordingly, the buffer queue of distinguishing priority is set in output synchronous DRAM inside, promptly 6 buffer queues are set in each synchronous DRAM inside, (differentiated service belongs to a kind of request explanation (RFC that distinguishes for service quality that carries to six kinds of types of service that define in the corresponding respectively differentiated service, request for comment) document generally can be used as the normative reference of design.Usually the level of switching system engineering design consideration is defined as 6 macrospecies type service: EF, AF1, and AF2, AF3, AF4, BE).Like this, just can provide in various degree service quality guarantee at the QoS requirement of different business based on the switching system of band buffer memory cross bar switch.
Another embodiment of the present invention is based on 9 * 9 switching systems of band buffer memory cross bar switch.Its physical structure is similar with above-mentioned 8 * 8 switching systems, also is to be made of input port, input memory cell, crosspoint, output memory cell and friendship output port, and interconnects by high-speed serial bus.Wherein crosspoint adopts the employing field programmable gate array (FPGA:Field Programmable Gate Array) of 18 * 18 band buffer memory cross bar switches to realize, but bag the longest of its each crossover node buffer unit buffer memory.The number of the entrance and exit of described band buffer memory cross bar switch is respectively the twice of input port and output port number, promptly the number of the entrance and exit of band buffer memory cross bar switch in the present embodiment is respectively 18, and the number of input port and output port is respectively 9.
The operation principle of described 9 * 9 switching systems is also similar with above-mentioned 8 * 8 switching systems.Because crosspoint adopts 18 * 18 band buffer memory cross bar switch realization, an input port of per two corresponding switching systems of inlet of crosspoint, therefore output ports of per two corresponding switching systems of outlet of crosspoint provide sufficient switching bandwidth for input port to the exchange of output port.Block for fear of inlet at band buffered cross switch, the buffer queue of distinguishing output port is set in each many formations first-in first-out of input (FIFO:First In FirstOut) memory inside, promptly 9 buffer queues are set, respectively corresponding 9 output ports in each many formations pushup storage inside.Like this, when the partial buffer formation took place to block, packets of information can be sent to crosspoint from other buffer queue scheduling.In addition, the identical content of buffer memory in two memories of each input, when one of them memory is read a packets of information, another memory upgrades this packets of information of deletion by the pointer of memory.Accordingly, the buffer queue of distinguishing priority is set, promptly 6 buffer queues is set, respectively 6 priority services of corresponding differentiated service in each synchronous DRAM inside in output synchronous DRAM inside.Like this, just can provide in various degree service quality guarantee at the QoS requirement of different business based on the switching system of band buffer memory cross bar switch.
No matter be 8 * 8 switching systems, or 9 * 9 switching systems, its processing procedure to packets of information all is the same.As shown in Figure 8, describe the processing procedure of the switching system by the present invention is based on band buffer memory cross bar switch of packets of information in detail:
1, packets of information arrives input port, and input port receives this packets of information and delivers to the input memory cell;
2, string and the modular converter in the input memory cell is converted to parallel mode with serial data packet, is written to simultaneously in the memory of input memory cell;
3, parallel serial conversion module will be converted to serial mode from the parallel data that memory is read, and according to the empty full state indication of the crossover node buffer memory of band buffer memory cross bar switch, be written in the nodal cache of crosspoint;
4, the packets of information in the crossover node buffer memory is converted into parallel mode by the outlet output of suitable scheduling mechanism from crosspoint by string and modular converter, writes in the memory of output memory cell;
5, each output port is dispatched packets of information in the output memory by suitable priority scheduling mechanism, and is converted into serial data packet by parallel serial conversion module, delivers to output port.
The above-mentioned embodiment that the present invention provides has adopted ASIC(Application Specific Integrated Circuit) ASIC or on-site programmable gate array FPGA mode to constitute respectively based on band buffer memory cross bar switch, can select to adopt which kind of mode to constitute crosspoint in actual engineering arbitrarily; In addition, the input memory cell can adopt static random access memory or many formations pushup storage; Corresponding output memory cell can adopt synchronous DRAM or many formations pushup storage, and the selection of input memory and output memory also can be the combination in any of the above-mentioned type memory.
Above-described embodiment of the present invention does not constitute the qualification to protection range of the present invention.Any any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (10)
1, a kind of switching system based on band buffer memory cross bar switch, it comprises input port, crosspoint, reaches output port, and it is characterized in that: described input port is connected with this crosspoint with the output memory cell by the input memory cell respectively with output port; Described crosspoint is band buffer memory cross bar switch, and the number of its entrance and exit is respectively the twice of input port and output port number.
2, switching system as claimed in claim 1, wherein, described input memory cell comprises two static random access memorys or many formations pushup storage.
3, switching system as claimed in claim 2, wherein, described input memory cell comprises two strings and modular converter, is used for the serial data from input port is converted to the parallel mode write memory; And two parallel serial conversion modules, be used for that the parallel data that memory is read is converted to serial mode and be sent to crosspoint.
4, switching system as claimed in claim 2, wherein, described memory is provided with the buffer queue of distinguishing output port according to output port number.
5, switching system as claimed in claim 1, wherein, described output memory cell comprises two synchronous DRAMs or many formations pushup storage.
6, switching system as claimed in claim 5, wherein, described output memory cell comprises two strings and modular converter, is used for the serial data from the exchange unit is converted to the parallel mode write memory; And two parallel serial conversion modules, be used for that the parallel data that memory is read is converted to serial mode and be sent to output port.
7, switching system as claimed in claim 5, wherein, described memory is provided with the buffer queue of distinguishing priority.
8, switching system as claimed in claim 1, wherein, described crosspoint is realized by field programmable gate array.
9, switching system as claimed in claim 1, wherein, described crosspoint is realized by the integrated circuit of application-specific.
10, switching system as claimed in claim 1, wherein, described input port, input memory cell, crosspoint, output memory cell, and output port between adopt high-speed serial bus to connect.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115454889A (en) * | 2022-11-09 | 2022-12-09 | 中科声龙科技发展（北京）有限公司 | Storage access scheduling method, system and chip |
| WO2022261832A1 (en) * | 2021-06-15 | 2022-12-22 | 华为技术有限公司 | Data switching method and system |
| CN118300908A (en) * | 2024-06-06 | 2024-07-05 | 芯云晟(杭州)电子科技有限公司 | Multi-channel connector of serial-parallel transceiver and multi-channel connecting chip of serial-parallel transceiver |
-
2006
- 2006-04-28 CN CNA2006100786293A patent/CN1874292A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022261832A1 (en) * | 2021-06-15 | 2022-12-22 | 华为技术有限公司 | Data switching method and system |
| CN115454889A (en) * | 2022-11-09 | 2022-12-09 | 中科声龙科技发展（北京）有限公司 | Storage access scheduling method, system and chip |
| CN115454889B (en) * | 2022-11-09 | 2023-01-06 | 中科声龙科技发展（北京）有限公司 | Storage access scheduling method, system and chip |
| CN118300908A (en) * | 2024-06-06 | 2024-07-05 | 芯云晟(杭州)电子科技有限公司 | Multi-channel connector of serial-parallel transceiver and multi-channel connecting chip of serial-parallel transceiver |
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