CN2774017Y - 4-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system - Google Patents
4-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system Download PDFInfo
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- CN2774017Y CN2774017Y CN 200520039528 CN200520039528U CN2774017Y CN 2774017 Y CN2774017 Y CN 2774017Y CN 200520039528 CN200520039528 CN 200520039528 CN 200520039528 U CN200520039528 U CN 200520039528U CN 2774017 Y CN2774017 Y CN 2774017Y
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Abstract
The utility model relates to a 4-bit parallel frame synchronous coder/decoder in an optical synchronous digital transmission system, which is composed of eight D triggers and five exclusive OR gates, wherein seven D triggers R1, R2, R3, R4, R5, R6 and R7 are provided with set ends S, and one D trigger R0 is provided with a reset end. The utility model has simple logical representation, concise circuit realization, a compact derivation process and easy subsequent upgrade. The working frequency is decreased greatly, the system stability is enhanced, and the art realization is facilitated. The utility model can be applied to the SDH/SONET frame data processing with higher linear speed.
Description
Technical field
The utility model relates to a kind of adding/descrambler, and 4 parallel-by-bits that relate in particular in a kind of optical synchronization digital transmission system add/descrambler.
Background technology
Synchronous digital transmission system (being called for short SDH/SONET) generally is made up of transmission equipment and two kinds of basic equipments of network node, for synchronous optical transmission system, transmission equipment is exactly a cable system, network node is more complicated then, comprises termination equipment (TM), Cross Connect equipment (DXC), multiplexing equipment (ADM) etc.All be step-by-step (BIT) serial transfer signal in the synchronous digital transmission system, but do not transmit the clock signal of this node simultaneously that needed data of the receiving terminal of each node and clock all are to recover to come out from the data-signal that receives.Recover (CDR) principle according to data clock commonly used, clock recovery relies on the variation of data-signal along finishing, if there is long ' 1 ' or ' 0 ' sequence to occur in the data flow that receives, then the clock that recovers out by this principle is not really accurate, can cause losing of data message or mistake with such clock deal with data, therefore can to carry out Data Receiving and Clock Extraction exactly in order guaranteeing at receiving terminal, must to stop to have in the data flow transmitted appearance of long ' 1 ' or ' 0 ' sequence.International Telecommunication Association (CCITT) stipulates in the synchronous digital transmission system agreement for this reason: at transmitting terminal data are carried out scrambling, the data after the scrambling are transmitted by optical cable through electricity/light conversion back again; At receiving terminal the signal that transmits from optical cable is carried out light/electricity conversion, the data-signal after the conversion is carried out Clock Extraction, Data Receiving, descrambling and subsequent treatment again.CCITT agreement G.709 in also the regulation: (the most basic in the optical synchronization digital transmission system, most important module by signal is the STM-1 signal to STM-N, wire rate is 155.2Mbit/s, the STM-N signal is that wire rate is N*155.2Mbit/s with basic module signal STM-1 synchronous multiplexing, result after byte interleaves) 9xN byte of first row of section overhead do not carry out scrambler; Occur in case follow the highest order (MSB) of that byte of STM-N section overhead first last byte of row closely, scrambler should be set to " 1111111 " automatically; The generator polynomial of scrambler sequence is 1+X
6+ X
7, scrambler sequence length is 127.
In the book of " Optical synchronization digital transmission network " that the Wei Leping that the People's Press publishes writes (1998 December the 2nd edition) the 56th page provided a serial and added/function diagram of descrambler.See also Fig. 1,7 d type flip flops are used for displacement, d type flip flop R2, R3 ..., the input of R7 respectively with last d type flip flop R1, a R2 ...., the output of R6 links to each other, CLK is a STM-1 frame linearity clock signal, Reset is for deciding frame pulse, asserts signal; An XOR gate is in order to realize that mould 2 is carried out in the output of d type flip flop R7 and R6 adds (XOR), operation result feeds back to the input of d type flip flop R1, the output of d type flip flop R7 is scrambler sequence, and the linear speed data of it and STM-1 frame add/processing of descrambling.Can analyze from above-mentioned workflow and to draw: in the normal process stage, each scrambler all is to add operation result from the mould 2 before 7 timeticks, and at each linear speed timeticks, R7 exports 1 scrambler, and R7 exports 4 scramblers successively in 4 linear speed timeticks.This scrambler circuit structure is simple, but owing to be operated under the wire rate, the operating frequency height causes complex manufacturing, the production cost height, even manufacturing has proposed high requirement even common process can't be realized to integrated circuit (IC) technology under 622M, 2.5G, 10G or higher frequency clock, as adopt special process then development cost can increase greatly, thereby this circuit must handle be replaced by parallelization in actual clock.
The utility model content
The purpose of this utility model is to provide 4 parallel-by-bit frame synchronization in a kind of optical synchronization digital transmission system that can be used under the high-frequency clock to add/descrambler.
The purpose of this utility model realizes by following technical method: 4 parallel-by-bit frame synchronization add/descrambler is made up of 8 d type flip flops and 5 XOR gate, wherein d type flip flop R1, R2, R3, R4, R5, R6, R7 and 1 d type flip flop R0 that have reset terminal R of 7 band set end S.The input signal of d type flip flop R0 is the output signal after the output signal of the 3rd d type flip flop R2 and the 4th d type flip flop R3 is passed through XOR gate; The output signal of the 4th d type flip flop R3 and the 5th d type flip flop R4 is through after the XOR gate, as the input signal of the 2nd d type flip flop R1; The output signal of the 5th d type flip flop R4 and the 6th d type flip flop R5 is through after the XOR gate, as the input signal of the 3rd d type flip flop R2; The output signal of the 6th d type flip flop R5 and the 7th d type flip flop R6 is through after the XOR gate, as the input signal of the 4th d type flip flop R3; The output signal of the 7th d type flip flop R6 and the 8th d type flip flop R7 is through after the XOR gate, as the input signal of the 5th d type flip flop R4; The output signal of the 2nd d type flip flop R1 is as the input signal of the 6th d type flip flop R5; The output signal of the 3rd d type flip flop R2 is as the input signal of the 7th d type flip flop R6; The output signal of the 4th d type flip flop R3 is as the input signal of the 8th d type flip flop R7.The output Q4...Q7 of the 5th to the 8th d type flip flop R4...R7 has constituted the scrambler sequence of 4 parallel-by-bits.
4 parallel-by-bit frame synchronization disclosed in the utility model add/descrambler, and its advantage shows: logical expressions are simple, and circuit is realized simple and clear, and derivation is simple and direct, and is easy to subsequent upgrade; Reduce operating frequency greatly, enhanced system stability is convenient to technology and is realized.
Description of drawings
Fig. 1 existingly is operated in that frame synchronization adds under the wire rate/circuit structure diagram of descrambler.
Fig. 2 be adopt the utility model 4 parallel-by-bits add/the SDH equipment of descrambler in the Data Stream Processing flow chart of receiving terminal.
Fig. 3 be adopt the utility model 4 parallel-by-bits add/the SDH equipment of descrambler in the Data Stream Processing flow chart of transmitting terminal.
Fig. 4 is that the utility model 4 parallel-by-bits add/circuit structure diagram of descrambler.
Embodiment
Combination now is the scrambler sequence generator polynomial 1+X of middle regulation G.707
6+ X
7Be described in further detail.By the linear speed frame synchronization that Fig. 1 is provided add/analysis of decoder circuit structure can obtain: in the normal process stage, each scrambler all is to add computing from the mould 2 before 7 clocks; At scrambler of each linear speed clock output, in the clock cycle, export 4 scramblers successively at 4 linear speeds.Get any N clock, suppose that the Q end value of 7 d type flip flops among Fig. 1 is followed successively by d1
n, d2
n, d3
n, d4
n, d5
n, d6
n, d7
n, hold from N to N+4 clock cycle d type flip flop Q and the value of XOR it is as shown in the table successively with the value representation of N clock cycle:
| Cycle XOR Q1 Q2 Q3 Q4 Q5 Q6 Q7 N d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n N+1 d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n N+2 d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n N+3 d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n N+4 d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n |
Table one: derivation is disturbed/is decoded in serial
If from last table XOR is regarded as d type flip flop R0, then the value of XOR is exactly d0 when N clock cycle
n, the value of XOR is exactly d0 when N+4 clock cycle
N+4, but when giving d type flip flop R0, R0 is made as d6 to the R7 initialize
n^d7
n, just realized the parallelization processing that scrambler sequence is generated so like this.In order to be illustrated more clearly in, suppose that scrambler sequence generation system clock frequency (clk_sys) is 1/4 of a linear speed clock (clk_line), and N the cycle of current P system clock cycle and N linear speed clock is synchronization, then N+4 the cycle of P+1 system clock cycle and linear speed clock is synchronization, and the value of 4 d type flip flops is as shown in the table:
| Q6 | d2 p | d6 p |
| Q5 | d1 p | d5 p |
| Q4 | d6 p^d7 p | d4 p |
| Q3 | d5 p^d6 p | d3 p |
| Q2 | d4 p^d5 p | d2 p |
| Q1 | d3 p^d4 p | d1 p |
| Q0 | d2 p^d3 p | d0 p＝d6 p^d7 p |
Table 2:4BIT disturbs/decodes
The above-mentioned derivation method that the parallelization of serial scrambling code generator is realized is modal a kind of method, it is also not very complicated when the parallelization degree is relatively lower, but if realize 16,32,64,128 or just seem very complicated when higher, and the back of makeing mistakes is difficult for checking.
The derivation method that the serial scrambling code generator parallelization of adopting realizes is comparatively easy.The value of 8 d type flip flops is followed successively by d0 when supposing any N clock cycle
n... d7
nThe value of 8 d type flip flops is followed successively by d0 during N+M clock cycle
N+m... d7
N+m(M be respectively 0,1,2,4,8,16.....).The value that this clock of every row place is represented constantly during N+M clock cycle in table 3 equates, the value representation of d type flip flop during only with different clock cycle, as: the value d0 of Q0 during N+4 clock cycle
N+4=d2
n^d3
n=d4
N+2^d5
N+2=d6
N+4^d7
N+4, use the value representation of N, N+2, a N+4 clock cycle trigger respectively.From following table 3 is that 1,2 o'clock method is identical with top method at M as can be seen, is that derivation when just omitting the 3rd clock cycle at 4 o'clock is with the simplification of implementation procedure at M.When N+4 clock cycle, be example with Q0, establish N '=N+2,
Then by d0
N+2=d4
n^d5
n
Get d0
N '+2=d4
N '^d5
N1=d4
N+2^d5
N+2,
Know by following table again: d4
N+2=d2
n
d5
n+2＝d3
n
And then obtain: d0
N+4=d4
N '^d5
N1=d4
N+2^d5
N+2=d2
n^d3
n
In like manner can obtain the value of other triggers.
| Cycle Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 |
| N d0 n＝d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n |
| d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n |
| N+1 d0 n+1＝d6 n+1^d7 n+1 d1 n+1 d2 n+1 d3 n+1 d4 n+1 d5 n+1 d6 n+1 d7 n+1 |
| N+2 d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n |
| d5 n+1^d6 n+1 d6 n+1^d7 n+1 d1 n+1 d2 n+1 d3 n+1 d4 n+1 d5 n+1 d6 n+1 |
| d0 n+2＝d6 n+2^d7 n+2 d1 n+2 d2 n+2 d3 n+2 d4 n+2 d5 n+2 d6 n+2 d7 n+2 |
| d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n |
| N+4 d4 n+2^d5 n+2 d5 n+2^d6 n+2 d6 n+2^d7 n+2 d1 n+2 d2 n+2 d3 n+2 d4 n+2 d5 n+2 |
| d0 n+4＝d6 n+4^d7 n+4 d1 n+4 d2 n+4 d3 n+4 d4 n+4 d5 n+4 d6 n+4 d7 n+4 |
Table 3: great-jump-forward parallel disturbance code derivation method
Can obtain as shown in Figure 44 parallel-by-bits to add from above/circuit structure of descrambler.This adds/and descrambler is made up of 8 d type flip flops and 5 XOR gate, wherein d type flip flop R1, R2, R3, R4, R5, R6, R7 and 1 d type flip flop R0 that have reset terminal R of 7 band set end S.The input signal of d type flip flop R0 is the output signal after the output signal of the 3rd d type flip flop R2 and the 4th d type flip flop R3 is passed through XOR gate; The output signal of the 4th d type flip flop R3 and the 5th d type flip flop R4 is through after the XOR gate, as the input signal of the 2nd d type flip flop R1; The output signal of the 5th d type flip flop R4 and the 6th d type flip flop R5 is through after the XOR gate, as the input signal of the 3rd d type flip flop R2; The output signal of the 6th d type flip flop R5 and the 7th d type flip flop R6 is through after the XOR gate, as the input signal of the 4th d type flip flop R3; The output signal of the 7th d type flip flop R6 and the 8th d type flip flop R7 is through after the XOR gate, as the input signal of the 5th d type flip flop R4; The output signal of the 2nd d type flip flop R1 is as the input signal of the 6th d type flip flop R5; The output signal of the 3rd d type flip flop R2 is as the input signal of the 7th d type flip flop R6; The output signal of the 4th d type flip flop R3 is as the input signal of the 8th d type flip flop R7.The output Q4...Q7 of the 5th to the 8th d type flip flop R4...R7 has constituted the scrambler sequence of 4 parallel-by-bits.
Fig. 2 and Fig. 3 adopt the utility model 4 parallel-by-bits to add/receive in the SDH equipment of descrambler and the Data Stream Processing flow chart of transmitting terminal.
In Fig. 2, linear speed data behind the light signal process clock data restorer (CDR) that receives form the system data of 4 bit formats again through serial/parallel conversion after searching the frame processing, producing frame head, adding with 4 parallel-by-bits under the effect of control signal subsequently/descrambler produces 4 parallel-by-bits under system clock scrambler sequence step-by-step once finishes 4 XOR (i.e. decoding) computing, and the data behind descrambling are given the subsequent treatment module.In Fig. 2, disturb when beginning decoding concurrent frame is added/the d type flip flop R7 of descrambler synchronously.。。R0 is provided with initial value and is " FE ".Need first 4 of scrambler to carry out scrambling by turn or descrambling computing in " F " in this initial value and the SDH/SONET frame, until last data of every frame.
In Fig. 3,4 system data adding with 4 parallel-by-bits under the effect of control signal/and descrambler produces 4 parallel-by-bits under system clock scrambler sequence step-by-step once finishes 4 XOR (promptly raising the price) computing, data after the scrambling form bit stream after parallel/serial conversion, transmit on optical cable through electricity/light conversion back.
4 parallel-by-bits described in the utility model add/and descrambler can be implemented in system clock 155M (linear speed frequency 1/4) and generate scrambler sequence down and finish and add/descrambling operation in the 622M system data is handled; With FPGA (Field Programmable Gate Array, field programmable gate array): after the realization, finish and satisfy protocol requirement, and logical expressions are simple, circuit is realized simple and clear, and derivation is simple and direct, and is easy to subsequent upgrade; Because 4 parallel-by-bit processing reduce operating frequency greatly, enhanced system stability the more important thing is that being convenient to technology realizes, for cost is saved in the exploitation of chip.The utility model can be used in the higher SDH/SONET frame data of linear speed are handled.
Claims (2)
1. 4 parallel-by-bit frame synchronization in the optical synchronization digital transmission system add/descrambler, it is characterized in that: comprise 8 d type flip flops and 5 XOR gate, the input signal of the 1st d type flip flop (R0) is the output signal after the output signal of the 3rd d type flip flop (R2) and the 4th d type flip flop (R3) is passed through XOR gate; The output signal of the 4th d type flip flop (R3) and the 5th d type flip flop (R4) is through after the XOR gate, as the input signal of the 2nd d type flip flop (R1); The output signal of the 5th d type flip flop (R4) and the 6th d type flip flop (R5) is through after the XOR gate, as the input signal of the 3rd d type flip flop (R2); The output signal of the 6th d type flip flop (R5) and the 7th d type flip flop (R6) is through after the XOR gate, as the input signal of the 4th d type flip flop (R3); The output signal of the 7th d type flip flop (R6) and the 8th d type flip flop (R7) is through after the XOR gate, as the input signal of the 5th d type flip flop (R4); The output signal of the 2nd d type flip flop (R1) is as the input signal of the 6th d type flip flop (R5); The output signal of the 3rd d type flip flop (R2) is as the input signal of the 7th d type flip flop (R6); The output signal of the 4th d type flip flop (R3) is as the input signal of the 8th d type flip flop (R7); The output of the 5th to the 8th d type flip flop (R4......R7) has constituted the scrambler sequence of 4 parallel-by-bits.
2. 4 parallel-by-bit frame synchronization in the optical synchronization digital transmission system as claimed in claim 1 add/descrambler, it is characterized in that: d type flip flop R1, R2, R3, R4, R5, R6, R7 have set end S, d type flip flop R0 and have reset terminal R.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520039528 CN2774017Y (en) | 2005-02-04 | 2005-02-04 | 4-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system |
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|---|---|---|---|
| CN 200520039528 CN2774017Y (en) | 2005-02-04 | 2005-02-04 | 4-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system |
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| CN2774017Y true CN2774017Y (en) | 2006-04-19 |
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| CN 200520039528 Expired - Fee Related CN2774017Y (en) | 2005-02-04 | 2005-02-04 | 4-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system |
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2005
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| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060419 Termination date: 20120204 |