CN1141806C - Scrambler/descrambler for synchronizing parallel frames in synchronous optical digital transmission system - Google Patents
Scrambler/descrambler for synchronizing parallel frames in synchronous optical digital transmission system Download PDFInfo
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- CN1141806C CN1141806C CNB001140868A CN00114086A CN1141806C CN 1141806 C CN1141806 C CN 1141806C CN B001140868 A CNB001140868 A CN B001140868A CN 00114086 A CN00114086 A CN 00114086A CN 1141806 C CN1141806 C CN 1141806C
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Abstract
The present invention relates to a parallel frame synchronization scrambler/descrambler (401) in an optical synchronous digital transmission system, which comprises eight D triggers (R0 to R7) and eight exclusive-OR gates, wherein the D triggers (R0 to R7) are orderly inserted and connected in series between two input exclusive-OR gates, and form a feedback type circuit loop; the scrambler/descrambler (401) generates scrambling sequences and completes the scrambling /descrambling operation in the STM-1 frame data processing under the timing clocks of a parallel system. The present invention has the advantages of simple logical table and simple and clear circuit realization, and besides, the present invention enhances the system stability and reduces the cost and the power consumption. The present invention can be applied to the scrambling /descrambling operation in the STM-1 frame data processing with high linear speed.
Description
The invention belongs to optical synchronization digital transmission system (being called for short SDH/SONET), specifically, the frame synchronization that relates to wherein adds/descrambler.
Synchronous digital transmission system generally is made up of transmission equipment and two kinds of basic equipments of network node, for optical synchronization digital transmission system, transmission equipment is exactly a cable system, and network node is more complicated then, comprises termination equipment (TM), Cross Connect equipment (DXC), multiplexing equipment (ADM) etc.The most basic in the optical synchronization digital transmission system, most important module by signal is the STM-1 signal, wire rate is 155.520Mbit/s, the STM-N signal is that wire rate is N * 155.520Mbit/s with basic module signal STM-1 synchronous multiplexing, result after byte interleaves; These signals all are by BIT serial transfer signal in transmission course, but do not transmit the clock signal of this node.The Data Receiving that the receiving terminal of each node is required and the clock of subsequent treatment all are to recover to come out from the data-signal that receives.According to clock and data recovery (CDR) principle commonly used, clock recovery relies on the variation of data-signal along finishing, if have long-chain 0 or long-chain 1 sequence to occur in the data flow that receives, then the clock that recovers by this principle is no longer accurate, the clock deal with data of coming out with such recovery can cause losing of data message or mistake, therefore can to carry out Data Receiving and Clock Extraction accurately in order guaranteeing at receiving terminal, must to stop to have in the data flow transmitted long-chain 0 or long-chain 1 sequence to occur.
International Telecommunication Association's tissue (CCITT) is stipulated in the agreement of optical synchronization digital transmission system for this reason: will carry out scrambling at transmitting terminal to the data that transmit, the data after the scrambling are sent out by optical cable after electricity/light conversion again; At receiving terminal the signal that transmits from optical cable is carried out light/electricity conversion, the data-signal after the conversion is carried out Clock Extraction, Data Receiving, descrambling and subsequent treatment again.CCITT agreement G.709 in also the regulation: to the STM-N section overhead first the row 9 * N byte do not carry out scrambler; Occur in case follow the highest order (MSB) of that byte of STM-N section overhead first last byte of row closely, scrambler should be set to " 1111111 " automatically; The generator polynomial of scrambler sequence is 1+x
6+ x
7
Existing scrambler generally uses the reaction type shift register of being made up of 7 grades of d type flip flops to realize that its feedback arrangement is determined by generator polynomial.The serial clock of STM-N signal is added to the input end of clock of each grade trigger, and the output of scrambler is abundant randomized signal, this signal on statistical property very near white noise.At transmitting terminal, scrambler sequence and serial data are that starting point is carried out XOR in order by turn with the frame head, finish the data scrambling process; In like manner at receiving terminal, same scrambler sequence is carried out same computing with the serial data that receives, and then recovers True Data, finishes the descrambling process of data.
In " the Optical synchronization digital transmission network " of publish in the People's Telecon Publishing House, Wei Leping writing (93 year March the 1st edition) book, the 52nd page has provided a frame synchronization that is operated under the wire rate 155.52Mbit/s and has added/circuit structure of descrambler 101, as shown in Figure 1.7 d type flip flops are used for displacement, d type flip flop R2, R3 ..., R7 input respectively with last d type flip flop R1, a R2 ..., R6 output link to each other, CLK is a STM-1 frame linearity clock signal, Reset is for deciding frame pulse, asserts signal; An XOR gate is in order to realize that mould 2 is carried out in the output of d type flip flop R7 and R6 adds (XOR), operation result feeds back to the input of d type flip flop R1, the output of d type flip flop R7 is scrambler sequence, and the linear speed data (BIT form) of it and STM one 1 frames add/processing of descrambling.Can analyze from above-mentioned workflow and to draw: in the normal process stage, each (BIT) scrambler all is to add operation result from the mould 2 before 7 timeticks; At each linear speed timeticks, R7 exports 1 (BIT) scrambler, and in 8 linear speed timeticks, R7 exports 8 scramblers successively.Although this scrambler 101 circuit structures are simple, but because it is operated under the wire rate, the operating frequency height causes complex manufacturing, the production cost height, even under some high frequency clock, can't realize, thereby in actual use this circuit be substituted become inevitable.
In current SDH equipment, the main type of data flow has: before the conversion of transmitting terminal electricity/light and the wire rate of receiving terminal light/electricity after changing be that (wire rate of STM-N signal is N * 155.520Mbit/s) for the BIT serial data of 155.520Mbit/s, before the parallel/serial conversion of transmitting terminal and the parallel speed after the serial/parallel conversion of receiving terminal be the data (1/8 of the wire rate of STM-1 signal, STM-N signal can recover the STM-1 signal of N group through demultiplexing) of the BYTE form of 19.44Mbyte/s.If the BIT serial data stream to wire rate adds/the descrambling code processing, then the scrambler operating rate is necessary for wire rate; If to before the parallel/serial conversion of transmitting terminal and the BYTE data flow of parallel speed after the serial/parallel conversion of receiving terminal add/descrambling code handles, then the operating rate of scrambler is necessary for parallel speed.
Therefore, if directly add/descrambler by agreement regulation design G.709, then this scrambler is operated under the timeticks of wire rate, be that the clock frequency is 155.520MHz or 622MHz (STM-4 signal) or higher 2.5GHz (STM-16) etc., high like this frequency has proposed high requirement to the IC manufacturing process, even common process can't be realized, if adopt special process then development cost is increased greatly, so just a problem has been proposed the designer: how to design one and can satisfy the scrambler requirement, operational clock frequency is reduced greatly, be convenient to adding/descrambler of processes.
The object of the present invention is to provide the frame synchronization under the parallel speed in a kind of SDH system to add/descrambler, can address the above problem, promptly realize the low rate of scrambler operation, the low cost of processing technology.
For achieving the above object, concurrent frame of the present invention add synchronously/descrambler is made up of 8 d type flip flops and 8 XOR gate; 1 d type flip flop and 7 d type flip flop that have the set end that have reset terminal interleaves with the XOR gate of 8 two inputs according to the order of sequence and connects; The 1st trigger is the described d type flip flop that has reset terminal, its input signal is that the input signal of the input signal of the 8th d type flip flop and the 7th d type flip flop is through the output signal after the described XOR gate, the input signal of the output signal of described the 1st d type flip flop and described the 8th d type flip flop is through after the described XOR gate, as the input signal of the 2nd d type flip flop; The output signal of the output signal of described the 2nd d type flip flop and described the 1st d type flip flop is through after the described XOR gate, as the input signal of the 3rd d type flip flop; All the other by that analogy, the output signal of n d type flip flop and the output signal of (n-1) individual d type flip flop are through XOR gate, as the input signal of (n+1) individual d type flip flop, the value of n is 2～7, has so constituted the circuit loop of a reaction type;
Described concurrent frame adds synchronously/and descrambler is operated under system's parallel clock, and the frequency of described parallel clock is 1/8 of a linear speed frequency; The output of described 8 d type flip flops is exported corresponding scrambler position successively, realizes that each beat of system's parallel clock produces the scrambler of a byte (8BIT).
Below in conjunction with drawings and Examples, further describe the present invention.
Fig. 1 is operated in frame synchronization under the wire rate 155.52Mbit/s and adds/circuit structure of descrambler 101.
Fig. 2 is the flow chart that adopts the Data Stream Processing of receiving terminal in the SDH equipment of the adding of Fig. 1 structure/descrambling code maker 101.
Fig. 3 is the flow chart that adopts the Data Stream Processing of transmitting terminal in the SDH equipment of the adding of Fig. 1 structure/descrambling code maker 101.
Fig. 4 is that concurrent frame of the present invention adds/circuit structure of descrambler 401 synchronously.
Fig. 5 is the flow chart that adopts the Data Stream Processing of receiving terminal in the SDH equipment of the present invention.
Fig. 6 is the flow chart that adopts the Data Stream Processing of transmitting terminal in the SDH equipment of the present invention.
Frame synchronization shown in Figure 1 adds/circuit structure of descrambler 101, introduced in detail in front.
In Fig. 2, the linear speed data of the scrambling that receives (BIT form) are through light/electricity conversion and Clock Extraction, resolve into the clock and the signal of telecommunication, again through after the frame head seizure and deciding the frame pulse generation, with add by the frame synchronization under the linear speed/scrambler sequence step-by-step (BIT) that descrambler 101 produces carries out the descrambling computing, data behind the descrambling and clock signal form the system data of BYTE form through serial/parallel conversion, promptly 1/8 linear speed clock and with the corresponding data of 1/8 linear speed clock, for subsequent treatment ready.
In Fig. 3, the system data of BYTE form forms the linear speed data of BIT form through parallel/serial conversion, add again with by the frame synchronization under the linear speed/scrambler sequence step-by-step (BIT) that descrambler 101 produces carries out the scrambling computing, and the data after the scrambling are delivered to electric to optic converter and are created in the light signal that transmits on the optical cable.
Fig. 4 is that concurrent frame of the present invention adds/circuit structure of descrambler 401 synchronously.This adds/and descrambler 401 is made up of 8 d type flip flops and 8 XOR gate, 1 d type flip flop R0 that has a reset terminal R and 7 d type flip flop R1 that have set end S ..., R7, interleave with the XOR gate of 8 two inputs according to the order of sequence and connect, the input signal of d type flip flop R0 is the output signal after the input signal of d type flip flop R7 and R6 passes through XOR gate, the output signal of d type flip flop R0 and the input signal of R7 are through after the XOR gate, as the input signal of d type flip flop R1; The output signal of d type flip flop R1 and R0 is through after the XOR gate, as the input signal of d type flip flop R2; Go down like this, the output signal of d type flip flop R6 and R5 is through after the XOR gate, as the input signal of d type flip flop R7 always; So constituted the circuit loop of a reaction type.CLKP is system's parallel clock signal, and its frequency is 1/8 of a linear speed frequency; Reset is for to decide frame pulse, set-reset signal, and the output Q0～Q7 of 8 d type flip flops exports the scrambler position (8BIT) of a corresponding byte successively.
Fig. 5 and Fig. 6 are respectively the flow charts that adopts receiving terminal and transmitting terminal Data Stream Processing in the SDH equipment of the present invention.
In Fig. 5, the linear speed data of the BIT form that receives are after frame head is caught and decided the frame pulse generation, form the system data of BYTE form again through serial/parallel conversion, add subsequently with by the frame synchronization under the parallel speed/the scrambler sequence step-by-step (BIT) of the BYTE form that descrambler 401 produces once finishes the descrambling computing of a byte (8BIT), proceeds subsequent treatment through the data of descrambling.In Fig. 6, the system data of BYTE form with add by the frame synchronization under the parallel speed/the scrambler sequence step-by-step (BIT) of the BYTE form that descrambler 401 produces once finishes the scrambling computing of a byte (8BIT), data after the scrambling form the linear speed data of BIT form again through parallel/serial conversion, with after electricity/light conversion is created in the light signal that transmits on the optical cable.
With Fig. 5, Fig. 6 and Fig. 2, Fig. 3 compares, can find frame synchronization add/peripheral circuit of descrambler changes little, just changed string and conversion and and the string conversion with add/the front and back order of descrambler, add finishing/XOR gate of descrambling operation by an increase under the linear speed frequency eight during for parallel clock, as XOR gate Xorsa among Fig. 5 and the XOR gate Xorsb among Fig. 6, they can both finish adding/descrambling operation the data of a byte (8BIT) at each beat of parallel clock, do not increase the extra configuration of system in addition again, add on the contrary/operating frequency of descrambling circuit reduced, thereby improved the stability of system, and be easier to the technology realization.
Scrambler sequence generator polynomial 1+x below in conjunction with the agreement regulation
6+ x
7, the present invention is described in further detail for Fig. 1 and Fig. 4.
Add/analysis of descrambler 101 circuit structures by the linear speed frame synchronization that Fig. 1 is provided, can obtain mentality of designing of the present invention.Analyze in the above and draw: in the normal process stage, each (BIT) in order to add/scrambler of descrambling all is to add computing from the mould 2 before 7 clocks; At 1 (BIT) scrambler of each linear speed timeticks R7 output, in 8 linear speed timeticks, export 8 scramblers successively from R7.Scrambler sequence generator polynomial 1+x in conjunction with the agreement regulation
6+ x
7With Fig. 1 circuit structure, can further derive draws the result of table 1.Deciding frame signal is the asserts signal of d type flip flop R1～R7 in the linear speed frame synchronous scrambler 101, and the state of XOR gate is 0 during set.
Table 1
| Linear CLK | XOR | R1 | R2 | R3 | R4 | R5 | R6 | R7 |
| 0, set | R7^R6＝0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| … | … | … | … | … | … | … | … | … |
| Clock n | Q7^Q6 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | Q7 |
| Clock n+1 | Q6^Q5 | Q7^Q6 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 |
| Clock n+2 | Q5^Q4 | Q6^Q5 | Q7^Q6 | Q1 | Q2 | Q3 | Q4 | Q5 |
| Clock n+3 | Q4^Q3 | Q5^Q4 | Q6^Q5 | Q7^Q6 | Q1 | Q2 | Q3 | Q4 |
| Clock n+4 | Q3^Q2 | Q4^Q3 | Q5^Q4 | Q6^Q5 | Q7^Q6 | Q1 | Q2 | Q3 |
| Clock n+5 | Q2^Q1 | Q3^Q2 | Q4^Q3 | Q5^Q4 | Q6^Q5 | Q7^Q6 | Q1 | Q2 |
| Clock n+6 | Q1^Q7^Q6 | Q2^Q1 | Q3^Q2 | Q4^Q3 | Q5^Q4 | Q6^Q5 | Q7^Q6 | Q1 |
| Clock n+7 | Q7^Q6^Q6^Q 5 | Q1^Q7^ Q6 | Q2^Q1 | Q3^Q2 | Q4^Q3 | Q5^Q4 | Q6^Q5 | Q7^Q6 |
| Clock n+8 | Q6^Q5^Q5^Q 4 | Q7^Q6^ Q6^ Q5 | Q1^Q7 ^Q6 | Q2^Q1 | Q3^Q2 | Q4^Q3 | Q5^Q4 | Q6^Q5 |
| … | … | … | … | … | … | … | … | … |
In table 1, timeticks n+8 and timeticks n choose wantonly, each register R1, R2 of these two timeticks correspondences of comparison ..., R7 and XOR gate output state, it is as follows to obtain table 2, represents the state of XOR gate XOR in the table with X.
Table 2
| Linear speed timeticks n+8 | Linear speed timeticks n | |
| R7 | Q7 n+8＝Q6 n^Q5 n | Q7 n |
| R6 | Q6 n+8＝Q5 n^Q4 n | Q6 n |
| R5 | Q5 n+8＝Q4 n^Q3 n | Q5 n |
| R4 | Q4 n+8＝Q3 n^Q2 n | Q4 n |
| R3 | Q3 n+8＝Q2 n^Q1 n | Q3 n |
| R2 | Q2 n+8＝Q1 n^X n | Q2 n |
| R1 | Q1 n+8＝X n^Q6 n^Q5 n＝X n^Q7 n+8 | Q1 n |
| XOR | X n+8＝Q6 n^Q5 n^Q5n^Q4 n＝Q7 n+8^Q6 n+8 | X n＝Q7 n^Q6 n |
In table 2, if regard XOR as d type flip flop R0, X
nThen just be the value Q0 of timeticks n d type flip flop R0 constantly
n, X
N+8Then just be the value Q0 of timeticks n+8 d type flip flop R0 constantly
N+8For clearer explanation, suppose that linear speed timeticks n just is the p beat of parallel clock (linear speed clock 1/8), then linear speed timeticks n+8 be exactly parallel clock the p+1 beat constantly, and with XOR
With corresponding 8 XOR gate XOR
0～XOR
7Represent that it is as follows so to obtain table 3:
Table 3
| Parallel clock beat p+1 | Parallel clock beat p | Parallel clock beat p |
| Q7 p+1＝XOR 7 | XOR 7＝Q6 p^Q5 p | Q7 p |
| Q6 p+1＝XOR 6 | XOR 6＝Q5 p^Q4 p | Q6 p |
| Q5 p+1＝XOR 5 | XOR 5＝Q4 p^Q3 p | Q5 p |
| Q4 p+1＝XOR 4 | XOR 4＝Q3 p^Q2 p | Q4 p |
| Q3 p+1＝XOR 3 | XOR 3＝Q2 p^Q1 p | Q3 p |
| Q2 p+1＝XOR 2 | XOR 2＝Q1 p^Q0 p | Q2 p |
| Q1 p+1＝XOR 1 | XOR 1＝Q0 p^Q6 p^Q5 p＝Q0 p^XOR 7 | Q1 p |
| Q0 p+1＝XOR 0 | XOR 0＝Q6 p^Q5 p ^Q5 p^Q4 p＝XOR 7^XOR 6 | Q0 p |
Clearly, can directly obtain as shown in Figure 4 circuit structure from table 3: 8 d type flip flop R0, R1 ... R7 and 8 s' XOR gate interleaves series connection according to the order of sequence, output Q0～the Q7 of 8 d type flip flops once exports the scrambler position of a byte in a timeticks, each output signal is delivered to the input of corresponding XOR gate simultaneously, the output signal of XOR gate then is connected to the input of next d type flip flop, has constituted the circuit loop of a reaction type.This adds/and descrambler 401 is operated under the parallel speed, can draw among the output of 8 d type flip flops in a parallel clock beat and Fig. 1 linear speed frame synchronous scrambler 101 from table 3 is consistent from the code stream of R7 output in 8 linear speed timeticks, therefore this add/a parallel clock beat of descrambler 401 can realize the operation of linear speed frame synchronous scrambler 101 at 8 linear speed timeticks, thereby can replace linear speed frame synchronous scrambler 101 fully on the function.
In Fig. 1, to decide frame pulse signal Reset linear speed frame synchronization is added/d type flip flop R1～R7 set in the descrambler 101, this moment, the XOR gate state was 0, therefore preceding 8 (BIT forms) of the scrambler sequence that produces should be 1111_1110 successively, see Table 1; In Fig. 4, decide frame pulse signal Reset concurrent frame is added/d type flip flop R1～R7 set in the descrambler synchronously, R0 is resetted, therefore first scrambler byte (BYTE form) that produces is 1111_1110.As seen, the result that draws of these two kinds of scramblers when resetting (trigger set and) when deciding frame pulse signal and come into force also is on all four.First payload data (BYTE form, i.e. the tenth byte of first row) of this byte (1111_1110) value and first row (BIT) by turn carries out scrambling (or descrambling) computing, by that analogy, also finishes scrambling/descrambling operation up to last data of every frame.
In sum, concurrent frame of the present invention adds synchronously/descrambler in the STM-1 frame data are handled, can be implemented in parallel system clock (linear speed frequency 1/8) and generate scrambler sequence down and finish and add/descrambling operation; This adds/after descrambler is realized with FPGA, satisfy protocol requirement after tested fully, and logic of the present invention statement is simple, and the circuit implementation is simple and clear; Frame synchronization under the wire rate adds/descrambler relatively, and operating frequency drops to 1/8 of original frequency, has increased the stability of a system, reduced power consumption, the more important thing is that being easy to technology realizes that these all bring huge facility in the production application of reality, for cost has been saved in the production of machine system.Mentality of designing of the present invention in addition has generalization, and can being applied to linear speed, higher (the STM-N frame data of N * 155.520Mbit/s) adding/the descrambling code operation in handling, this phototiming transmission equipment to the more high-grade speed of development is significant.
Claims (3)
1. the concurrent frame in the optical synchronization digital transmission system adds/descrambler (401) synchronously, it is characterized in that: comprise 8 d type flip flops (R0, R1 ..., R7) and 8 XOR gate; Described d type flip flop (R0, R1 ..., R7) interleave with described XOR gate according to the order of sequence and connect;
The input signal of described the 1st d type flip flop (R0) is that the input signal of the input signal of described the 8th d type flip flop (R7) and described the 7th d type flip flop (R6) is through the output signal after the described XOR gate; The input signal of the output signal of described the 1st d type flip flop (R0) and described the 8th d type flip flop (R7) is through after the described XOR gate, as the input signal of the 2nd d type flip flop (R1); The output signal of the output signal of described the 2nd d type flip flop (R1) and described the 1st d type flip flop (R0) is through after the described XOR gate, as the input signal of the 3rd d type flip flop (R2); All the other by that analogy, the output signal of n d type flip flop and the output signal of (n-1) individual d type flip flop are through XOR gate, as the input signal of (n+1) individual d type flip flop, the value of n is 2～7 round numbers, has so constituted the circuit loop of a reaction type.
2. concurrent frame as claimed in claim 1 adds/descrambler (401) synchronously, it is characterized in that: described 8 d type flip flops (R0, R1 ..., R7) be 1 d type flip flop (R0) that has a reset terminal and 7 d type flip flops that have the set end (R1 ..., R7).
3. concurrent frame as claimed in claim 1 or 2 adds/descrambler (401) synchronously, it is characterized in that: and described concurrent frame adds synchronously/and descrambler is operated under system's parallel clock, and its system's parallel clock frequency is 1/8 of linear speed frequency 155.52Mbit/s.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1306732C (en) * | 2004-05-14 | 2007-03-21 | 西安邮电学院 | Frame synchronized parallel scrambler and parallel de-scrambler |
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| CN100452686C (en) * | 2004-04-22 | 2009-01-14 | 东南大学 | Parallel frame alignment circuit applied to optical synchronous digital transferring system |
| CN101018097B (en) * | 2006-02-07 | 2011-09-21 | 华为技术有限公司 | Disturbance code generation device |
| US8848913B2 (en) | 2007-10-04 | 2014-09-30 | Qualcomm Incorporated | Scrambling sequence generation in a communication system |
| CN102065055A (en) * | 2011-01-14 | 2011-05-18 | 复旦大学 | Superfast parallel scrambler and descrambler in MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) system |
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| CN1306732C (en) * | 2004-05-14 | 2007-03-21 | 西安邮电学院 | Frame synchronized parallel scrambler and parallel de-scrambler |
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Address after: 518057 Zhongxing building, science and technology south road, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee after: ZTE Corporation Address before: 518057 Zhongxing building, science and technology south road, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: Zhongxing Communication Co., Ltd., Shenzhen City |
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Granted publication date: 20040310 Termination date: 20140301 |