CN101018097B - Disturbance code generation device - Google Patents
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- CN101018097B CN101018097B CN2006100335000A CN200610033500A CN101018097B CN 101018097 B CN101018097 B CN 101018097B CN 2006100335000 A CN2006100335000 A CN 2006100335000A CN 200610033500 A CN200610033500 A CN 200610033500A CN 101018097 B CN101018097 B CN 101018097B
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Abstract
The related generator for disturbance code comprises a L-bit shift register, where L=MXX; M denotes the period of disturbance code sequence corresponding to generator polynomial; X should make L not less than N; and all of L, M and N are integers. This invention makes logic clock work on high frequency.
Description
Technical field
The present invention relates to a kind of disturbance code generation device, relate in particular to a kind of disturbance code generation device that is used for digital communication system scrambling and descramble signal.
Background technology
In the signal processing of digital communication system, scrambling and descrambling technology are very important and crucial technological means.Scrambling and descrambling technology are exactly the operation of multiplying each other with scrambler in simple terms, wherein mainly are the correlation properties of having utilized scrambler.Therefore the generation of scrambler is very crucial, scrambler is often given many important function in digital communication system, for example, synchronous support is provided in asynchronous communication system, the opposing wireless channel is to the interference of transmission signals in the ground wireless communication system, in code division multiple access system, distinguish different base station and user, at SDH (Synchronous Digital Hierarchy)/Synchronous Optical Network (Synchronous Digital Hierarchy/Synchronous OpticalNetwork, SDH/SONET) make in from the data-signal that receives, to recover clock accurately, thereby avoid losing or mistake of data message.Be example with the disturbance code generation device that is used for SDH/SONET below, the shortcoming that existing disturbance code generation device exists is described.
The most basic among the SDH/SONET, most important module by signal is STM-1 (Synchronous TransferMode, synchronous transfer mode) signal, wire rate is 155.520Mbit/s, obtain more senior STM-N signal after its synchronous multiplexing, byte being interleave, the wire rate of STM-N signal is N * 155.520Mbit/s again; These signals all are by bit BIT serial transfer signal in transmission course, but do not transmit the clock signal of present networks node.The Data Receiving that the receiving terminal of each network node is required and the clock of subsequent treatment all are to recover to come out from the data-signal that receives.Recover (Clock and DataRecovery according to clock commonly used and data, CDR) principle, clock recovery relies on the variation of data-signal along finishing, if have length 0 or long 1 sequence to occur in the data flow that receives, then the clock that recovers by this principle is no longer accurate, the clock deal with data of coming out with such recovery can cause losing of data message or mistake, therefore can to carry out Data Receiving and Clock Extraction accurately in order guaranteeing at receiving terminal, must to stop to have in the data flow transmitted length 0 or long 1 sequence to occur.
For this reason, (the CCITT of CCITT, be the present ITU-T of standardization department of international telecommunication union telecommunication) in the SDH/SONET agreement, stipulate: must comprise enough timing informations in the data flow of transmission so that network node can be realized the extraction of clock according to data flow, satisfy this requirement, must make and avoid length 0 or long 1 sequence to occur in the data flow.Suitable data stream can be realized by scrambling.
G.707/Y.1322, CCITT also stipulates STM-N (N=1,4,16,64,256 in the agreement at ITU-T ...) the scrambler sequence generator polynomial of disturbance code generation device is: 1+X
6+ X
7
Existing disturbance code generation device uses the reaction type shift register of being made up of 7 grades of d type flip flops to realize that its feedback arrangement is determined by generator polynomial usually.The serial clock of STM-N signal is added to the input end of clock of each grade trigger.At transmitting terminal, scrambler sequence and serial data that disturbance code generation device generates are that starting point is carried out XOR in order by turn with the frame head, finish the data scrambling process; In like manner at receiving terminal, same scrambler sequence is carried out same computing with the serial data that receives, and then recovers True Data, finishes the descrambling process of data.
See also Fig. 1, it is the circuit theory diagrams that existing frame synchronization adds descrambler.This frame synchronization adds descrambler and comprises disturbance code generation device and an XOR gate, and this disturbance code generation device comprises 7 d type flip flop D0～D6 that are used to be shifted, d type flip flop D1, D2 ... the input of D6 respectively with last d type flip flop D0, a D1 ... the output of D5 links to each other; This XOR gate is in order to realize that the output of d type flip flop D5 and D6 is carried out XOR, operation result feeds back to the input of d type flip flop D0, the output of d type flip flop D6 is the scrambler sequence of disturbance code generation device output, 7 trigger D0～D6 produce periodic scrambler sequence under the effect of the serial bit of STM-N clock, the bit XOR of the scrambler bit that generates and the STM-N of input draws the data behind the scrambler, and these scrambler data can guarantee to avoid length 0 or long 1 sequence to occur.
Because the scrambler multinomial provides serial algorithm: the bit clock of pressing STM-N, in actual applications, the STM-N data of input are parallel datas, therefore must make the scrambler algorithm into parallel algorithm, promptly under STM-N byte input clock, disturbance code generation device provides the M bit STM-N data of M bit (M is the byte data bit wide of STM-N) scrambler data and input to carry out XOR.The existing techniques in realizing way all is to extrapolate parallel algorithm by this serial algorithm.For the STM-1 business, its byte data bit wide is 8, therefore needs the parallel disturbance code algorithm of one 8 bit wide.
The derivation of parallel algorithm can be according to the serial algorithm method, as shown in table 1, if 8 scrambler registers are Q00～Q07, press G.707 protocol requirement, seven trigger initial values of disturbance code generation device are " 1111111 ", the initial value that just obtains parallel 8 scrambler registers after the 8 bat serial bit clocks is " 11111110 ", i.e. this train value of Q6; And the parallel disturbance code register value will be the function of Q07～Q00 afterwards:
Table 1
| Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | ? |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | Q07 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | Q06 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | Q05 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | Q04 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | Q03 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | Q02 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Q01 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | Q00 |
Table 2 is the parallel disturbance code function table: " ^ " presentation logic XOR, and N represents the current time value, N-1 represents the value of last clock register.
Table 2
| Q N | Q N-1 |
| Q07 | Q06^Q05 |
| Q06 | Q05^Q04 |
| Q05 | Q04^Q03 |
| Q04 | Q03^Q02 |
| Q03 | Q02^Q01 |
| Q02 | Q01^Q00 |
| Q01 | Q07^Q05 |
| Q00 | Q06^Q04 |
If the bit wide of STM-N is the 16bit position, then the parallel disturbance code algorithm just must be derived by 16bit, supposes that the 16bit disturbance code generation device is respectively Q17～Q10, Q07～Q00, Qnm=F (Q0k) then, n=1 or 0 wherein, m=0～7; K=0～7, i.e. 16 functions that disturbance code generation device all is Q07～Q00.And the like, for STM-256, the current logic chip generally adopts the 155Mhzx256bit bit wide, therefore, parallel derivation formula must be derived the algorithm of parallel 256 bit wides, divides into groups by 8 bits, need 32 groups, be made as Q317～Q310 ... Q07～Q00, each register are the functions of Q07～Q00.
From as can be known above-mentioned, when the scrambler sequence that existing disturbance code generation device produces adds descrambling to the STM-N parallel data, it must be derived respectively according to the variation of the byte data bit wide of STM-N and adapt to the parallel disturbance code formula that this bit wide requires, when a design needs the scrambler of compatible different bit wides simultaneously, during such as compatible STM-1 and STM-16, logical design just must comprise two scrambler algorithms simultaneously, therefore, existing disturbance code generation device can not be reused in a plurality of application scenarios, has increased the logical design scale.
Because that commonly used all is STM-1 at present, STM-4, STM-16, and the application of STM-64 product is fewer, for STM-256, on the market still less almost there be not related chip, therefore, derivation for parallel 256 bit wides of STM-256 will be a very loaded down with trivial details job, therefore, existing disturbance code generation device is very big to the workload that high-bit width is derived, and easily makes mistakes.
On parallel algorithm, each register of parallel algorithm all is the function of minimum 8bit register, and bit wide is wide more, and the logic load of low 8bit is big more, so the clock speed of logic chip is just low more.Therefore, existing disturbance code generation device is restricted to the logic working clock; Such as STM-256, requiring work clock is 155Mhz, just may not realize under the parallel disturbance code algorithm.
Because adopted a large amount of XOR gate in the existing disturbance code generation device, when the scrambler bit wide was wide more, the logical resource of these XOR gate expended very big, therefore, wide more when the scrambler bit wide, the resource occupation of existing disturbance code generation device is just many more.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of signal for different byte data bit wides to carry out scrambling and descrambling needn't be derived again, is easy to make the disturbance code generation device of logic working clock work on very high frequency.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of disturbance code generation device is provided, it adopts a bit wide is the shift register of L, L=M * X wherein, M is the scrambler sequence cycle of the generator polynomial correspondence of scrambler sequence, the value of X must satisfy L more than or equal to N, and N is the bit wide of the data of required adding/descrambling, and M, N and X are positive integer.
Above-mentioned shift register comprises L d type flip flop D
0～D
L-1With L MUX M
0～M
L-1, this L MUX M
0～M
L-1Output respectively corresponding with L d type flip flop D
0～D
L-1Input connect this L d type flip flop D
0～D
L-1Output respectively corresponding with L MUX M
0～M
L-1First input end connect this N d type flip flop D
0～D
N-1Output also respectively corresponding with N MUX M
L-N～M
L-1Second input connect this L-N d type flip flop D
N～D
L-1Output also respectively corresponding with L-N MUX M
0～M
L-N-1Second input connect this L MUX M
0～M
L-1Enable Pin link together, enable to control this L MUX M by scrambling
0～M
L-1Work, this L d type flip flop D
0～D
L-1Clock end link together.
The invention has the beneficial effects as follows: because disturbance code generation device of the present invention adopts the shift register that bit wide is L, L=M * X wherein, M is the scrambler sequence cycle of the generator polynomial correspondence of scrambler sequence, the value of X must satisfy L more than or equal to N, N is the bit wide of the data of required adding/descrambling, M, N and X are positive integer, therefore disturbance code generation device of the present invention is for the generator polynomial of all scrambler sequence, the scrambling algorithm all is to adopt same principle to realize, the too many derivation workload of expense not, special under a lot of situation of bit wide, and can be easy to guarantee the correctness that designs; And bit wide to the data of different required adding/descramblings, especially when bit wide less than the scrambler sequence of the generator polynomial correspondence of scrambler sequence during the cycle, can be with a design, various bit wide situations can be easy to adapt to by the bit wide parameter of revising displacement, every kind of bit wide form of deriving again needn't be; And adopt the mode of shift register also to be easy to make the logic working clock work on very high frequency; In addition, because the shift register that the present invention adopts comprises L d type flip flop D
0～D
L-1With L MUX M
0～M
L-1, do not need to do the processing of XOR, so the combined resource of using seldom, and size of code is very little, can save the operating time.
Description of drawings
Fig. 1 is the circuit theory diagrams that existing frame synchronization adds descrambler;
Fig. 2 is the schematic diagram of the scrambler algorithm of disturbance code generation device specific embodiment of the present invention;
Fig. 3 is the schematic diagram of the scrambler sequence of disturbance code generation device specific embodiment of the present invention;
Fig. 4 is the parallel logic block-diagram that adds the descrambler specific embodiment of frame synchronization that adopts disturbance code generation device of the present invention;
Fig. 5 is the parallel circuit theory diagrams that add the descrambler specific embodiment of frame synchronization that adopt disturbance code generation device of the present invention.
Embodiment
Be example to adopt disturbance code generation device of the present invention that STM-N (N=1,4,16,64,256) parallel data is carried out scrambler below, come disturbance code generation device of the present invention is done detailed explanation.
To carry out the scrambler sequence that scrambler then must produce 256bit to the STM-256 parallel data.Generator polynomial 1+X according to scrambler sequence
6+ X
7This scrambler sequence is that one-period is 127 pseudo random sequence as can be known, if the cycle 127 is numbered 0～126, then the scrambler algorithm is exactly as shown in Figure 2.Repeat 1 time behind the every 127bit of scrambler sequence, get 2 cycle 254bit add the 3rd cycle 0 and 1 and the 256bit of STM-256 parallel data of input carry out XOR, the 3rd cycle 126 after begin new 0～126 sequence again, therefore can scrambler sequence regard as one end to end, 3 cycles are that 127 pseudo random sequence is combined in one the data block of going round and beginning again, as shown in Figure 3.This data block bit wide is 127x3=381.Because the generator polynomial 1+X of scrambler sequence
6+ X
7127 place values be known, therefore every bit value of this data block also is known, when first time scrambling, get the front 256bit of this data block and the 256bit of input and carry out XOR, direction is rotated 256bit as shown in Figure 3 then, then for the second time gets 256bit from lighting, and is exactly the scrambling value of the needed parallel 256bit second time, this value and second 256bit data importing XOR mutually must arrive second data after the parallel scrambling, and the like.
Concrete logic block-diagram as shown in Figure 4, it is 381 shift register that disturbance code generation device of the present invention adopts a bit wide, its initial value can draw by the generator polynomial of scrambler sequence.It is as follows that scrambler produces operation principle: each STM-256 parallel clock cycle, get the 256bit parallel data XOR of the STM-256 of the low 256bit of shift register and input and realize scrambler, shift register is shifted simultaneously, displacement mode is the low 125bit that the high 125bit assignment of shift register is given shift register, low 256bit value assignment is given the high 256bit of shifting memory, thereby realizes the displacement of 256bit.
See also Fig. 5, be that parallel disturbance code with 256bit is an example, adopt the parallel circuit theory diagrams that add descrambler of frame synchronization of disturbance code generation device of the present invention, this frame synchronization is parallel to be added descrambler and comprises disturbance code generation device and 256 XOR gate, and this disturbance code generation device comprises 381 d type flip flop D0～D380 and 381 MUX M0～M380.These 381 MUX M0～M380 are 2 and select 1 selector, and the output of these 381 MUX M0～M380 is corresponding respectively to be connected with the input of 381 d type flip flop D0～D380.The output of these 381 d type flip flop D0～D380 is corresponding respectively to be connected with 0 input of 381 MUX M0～M380, the output of these 256 d type flip flop D0～D255 is also corresponding respectively to be connected with 1 input of 256 MUX M125～M380, and the output of these 125 d type flip flop D256～D380 is also corresponding respectively to be connected with 1 input of 125 MUX M0～M124.The Enable Pin of these 381 MUX M0～M380 links together, and is enabled to control the work of these 381 MUX M0～M380 by scrambling.These 381 d type flip flop D0～D380 have set function.The clock end of 381 d type flip flop D0～D380 links together, parallel clock by STM-256 is controlled, in each STM-256 parallel clock cycle, the output of getting these 256 d type flip flop D0～D255 is by data/address bus and the data of 256 STM-256 parallel datas being imported by bus behind output scrambler behind 256 XOR gate XORs, and these scrambler data can guarantee to avoid length 0 or long 1 sequence to occur.
When scrambling begins, the scrambler value in 381 trigger D0～3 cycles of D380 set (can calculate out according to the scrambler multinomial by each cycle occurrence, be total to 127bit, 3 cycles are 381bit), under the effect of scrambling enable signal (suppose effectively high), then d type flip flop D255～D0 totally 256 triggers currency in order assignment give D380～D125 totally 256 triggers; D type flip flop Q380～Q256 totally 125 triggers currency in order assignment give D124～D0 trigger totally 125 triggers; Top operation is under the parallel data clock effect of 256bit.Next cycle is if scrambling enables effectively then to repeat.When scrambler enables when invalid, each trigger keeps currency.The data that are used for parallel disturbance code then slave flipflop D255～D0 output are got, and are used for and import data and carry out XOR.
If the input data are to treat the data of scrambler, then output is exactly the data behind the scrambler, is equivalent to the scrambler process; If the input data are data that scrambler is crossed, output quite is the data behind the descrambling code, is equivalent to the descrambling code process.
In addition, if the STM-64 parallel data is carried out scrambler, adopt then that the frame synchronization of disturbance code generation device of the present invention is parallel to be added descrambler and comprise disturbance code generation device and 64 XOR gate, this disturbance code generation device comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126.These 127 MUX M0～M126 are 2 and select 1 selector, and the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126.The output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with 0 input of 127 MUX M0～M126, the output of these 64 d type flip flop D0～D63 is also corresponding respectively to be connected with 1 input of 64 MUX M63～M126, and the output of these 63 d type flip flop D64～D126 is also corresponding respectively to be connected with 1 input of 63 MUX M0～M62.The Enable Pin of these 127 MUX M0～M126 links together, and is enabled to control the work of these 127 MUX M0～M126 by scrambling.These 127 d type flip flop D0～D126 have set function.The clock end of 127 d type flip flop D0～D126 links together, parallel clock by STM-64 is controlled, in each STM-64 parallel clock cycle, the output of getting these 64 d type flip flop D0～D63 is by data/address bus and the data of 64 STM-64 parallel datas being imported by bus behind output scrambler behind 64 XOR gate XORs.
If the STM-16 parallel data is carried out scrambler, adopt then that the frame synchronization of disturbance code generation device of the present invention is parallel to be added descrambler and comprise disturbance code generation device and 16 XOR gate, this disturbance code generation device comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126.These 127 MUX M0～M126 are 2 and select 1 selector, and the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126.The output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with 0 input of 127 MUX M0～M126, the output of these 16 d type flip flop D0～D15 is also corresponding respectively to be connected with 1 input of 16 MUX M111～M126, and the output of these 111 d type flip flop D16～D126 is also corresponding respectively to be connected with 1 input of 111 MUX M0～M110.The Enable Pin of these 127 MUX M0～M126 links together, and is enabled to control the work of these 127 MUX M0～M126 by scrambling.These 127 d type flip flop D0～D126 have set function.The clock end of 127 d type flip flop D0～D126 links together, parallel clock by STM-16 is controlled, in each STM-16 parallel clock cycle, the output of getting these 16 d type flip flop D0～D15 is by data/address bus and the data of 16 STM-16 parallel datas being imported by bus behind output scrambler behind 16 XOR gate XORs.
If the STM-4 parallel data is carried out scrambler, adopt then that the frame synchronization of disturbance code generation device of the present invention is parallel to be added descrambler and comprise disturbance code generation device and 4 XOR gate, this disturbance code generation device comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126.These 127 MUX M0～M126 are 2 and select 1 selector, and the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126.The output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with 0 input of 127 MUX M0～M126, the output of these 4 d type flip flop D0～D3 is also corresponding respectively to be connected with 1 input of 4 MUX M123～M126, and the output of these 123 d type flip flop D4～D126 is also corresponding respectively to be connected with 1 input of 123 MUX M0～M122.The Enable Pin of these 127 MUX M0～M126 links together, and is enabled to control the work of these 127 MUX M0～M126 by scrambling.These 127 d type flip flop D0～D126 have set function.The clock end of 127 d type flip flop D0～D126 links together, parallel clock by STM-4 is controlled, in each STM-4 parallel clock cycle, the output of getting these 4 d type flip flop D0～D3 is by data/address bus and the data of 4 STM-4 parallel datas being imported by bus behind output scrambler behind 4 XOR gate XORs.
If the STM-1 parallel data is carried out scrambler, adopt then that the frame synchronization of disturbance code generation device of the present invention is parallel to be added descrambler and comprise disturbance code generation device and 1 XOR gate, this disturbance code generation device comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126.These 127 MUX M0～M126 are 2 and select 1 selector, and the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126.The output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with 0 input of 127 MUX M0～M126, the output of this d type flip flop D0 is connected with 1 input of MUX M126, and the output of these 126 d type flip flop D1～D126 is also corresponding respectively to be connected with 1 input of 126 MUX M0～M125.The Enable Pin of these 127 MUX M0～M126 links together, and is enabled to control the work of these 127 MUX M0～M126 by scrambling.These 127 d type flip flop D0～D126 have set function.The clock end of 127 d type flip flop D0～D126 links together, parallel clock by STM-1 is controlled, in each STM-1 parallel clock cycle, get the data of 1 STM-1 parallel data behind output scrambler behind 1 XOR gate XOR of output and the input of d type flip flop D0.
For STM-N (N=1,4,64), general practical application bit wide is 64bits to the maximum, therefore, shift register adopts the 127bit bit wide, takes out the data bit width that the bit wide that is used for scrambler is STM-N from shift register at every turn, it is for example the same with STM-256 to carry out the shifting function mode simultaneously, is the bit wide that the bit position of being moved equals the STM-N data.
In addition, to STM-N (N=1,4, when 64) parallel data is carried out scrambler, the d type flip flop of disturbance code generation device of the present invention and the quantity of MUX also can be 254,381 etc., when the STM-256 parallel data is carried out scrambler, the d type flip flop of disturbance code generation device of the present invention and the quantity of MUX also can be 508,635 etc., the quantity of the d type flip flop of disturbance code generation device of the present invention and MUX must be greater than the bit wide of the data of required adding/descrambling in a word, also must be simultaneously the scrambler sequence that adopted the generator polynomial correspondence the scrambler sequence cycle positive integer doubly.Above-mentioned d type flip flop also can be realized by the module that rest-set flip-flop or JK flip-flop are transformed into tool d type flip flop function.
Disturbance code generation device of the present invention is applicable to the generator polynomial of all scrambler sequence, for example g (x)=x
9+ x
8+ X
5+ x
4+ 1, g (x)=X
9+ X
4+ 1, g (x)=1+x
14+ x
15Or the like, the scrambler sequence of the generator polynomial correspondence of each scrambler sequence all has the cycle, for example the generator polynomial g of scrambler sequence (x)=X
9+ X
4+ 1, the cycle of its pairing scrambler sequence is 511.
In sum, can make following derivation: disturbance code generation device of the present invention adopts the shift register that bit wide is L, L=M * X wherein, M is the scrambler sequence cycle of the generator polynomial correspondence of scrambler sequence, the value of X must satisfy L more than or equal to N, N is the bit wide of the data of required adding/descrambling, and M, N and X are positive integer.This shift register comprises L d type flip flop D
0～D
L-1With L MUX M
0～M
L-1, this L MUX M
0～M
L-1Output respectively corresponding with L d type flip flop D
0～D
L-1Input connect this L d type flip flop D
0～D
L-1Output respectively corresponding with L MUX M
0～M
L-1First input end connect this N d type flip flop D
0～D
N-1Output also respectively corresponding with N MUX M
L-N～M
L-1Second input connect this L-N d type flip flop D
N～D
L-1Output also respectively corresponding with L-N MUX M
0～M
L-N-1Second input connect this L MUX M
0～M
L-1Enable Pin link together, enable to control this L MUX M by scrambling
0～M
L-1Work, this L d type flip flop D
0～D
L-1Clock end link together.
Disturbance code generation device of the present invention is for the generator polynomial of all scrambler sequence, the scrambling algorithm all is to adopt same principle to realize, the too many derivation workload of expense, special under a lot of situation of bit wide, and can be easy to guarantee the correctness that designs;
The size of code that disturbance code generation device of the present invention is realized is very little, also can save the operating time.
Disturbance code generation device of the present invention does not need to do the processing of XOR, and therefore the combined resource of using seldom.Adopt the mode of shift register also to be easy to make the logic working clock work on very high frequency.
Disturbance code generation device of the present invention is to the bit wide of the data of different required adding/descramblings, especially when bit wide less than the scrambler sequence of the generator polynomial correspondence of scrambler sequence during the cycle, can be with a design, various bit wide situations can be easy to adapt to by the bit wide parameter of revising displacement, every kind of bit wide form of deriving again needn't be.
Claims (9)
1. disturbance code generation device, it is characterized in that: it adopts a bit wide is the shift register of L, L=M * X wherein, M is the scrambler sequence cycle of the generator polynomial correspondence of scrambler sequence, the value of X must satisfy L more than or equal to N, N is the bit wide of the data of required adding/descrambling, and M, N and X are positive integer;
Described shift register comprises L d type flip flop D
0～D
L-1With L MUX M
0～M
L-1, this L MUX M
0～M
L-1Output respectively corresponding with L d type flip flop D
0～D
L-1Input connect this L d type flip flop D
0～D
L-1Output respectively corresponding with L MUX M
0～M
L-1First input end connect this N d type flip flop D
0～D
N-1Output also respectively corresponding with N MUX M
L-N～M
L-1Second input connect this L-N d type flip flop D
N～D
L-1Output also respectively corresponding with L-N MUX M
0～M
L-N-1Second input connect this L MUX M
0～M
L-1Enable Pin link together, enable to control this L MUX M by scrambling
0～M
L-1Work, this L d type flip flop D
0～D
L-1Clock end link together.
2. disturbance code generation device as claimed in claim 1, it is characterized in that: when M is 127, the data of required adding/descrambling are STM-256, be that N is 256 o'clock, the bit wide L of this shift register is 381, this shift register comprises 381 d type flip flop D0～D380 and 381 MUX M0～M380, the output of these 381 MUX M0～M380 is corresponding respectively to be connected with the input of 381 d type flip flop D0～D380, the output of these 381 d type flip flop D0～D380 is corresponding respectively to be connected with the first input end of 381 MUX M0～M380, the output of these 256 d type flip flop D0～D255 is also corresponding respectively to be connected with second input of 256 MUX M125～M380, the output of these 125 d type flip flop D256～D380 is also corresponding respectively to be connected with second input of 125 MUX M0～M124, the Enable Pin of these 381 MUX M0～M380 links together, enable to control the work of these 381 MUX M0～M380 by scrambling, the clock end of these 381 d type flip flop D0～D380 links together, and is controlled by the parallel clock of STM-256.
3. disturbance code generation device as claimed in claim 1, it is characterized in that: when M is 127, the data of required adding/descrambling are STM-64, be that N is 64 o'clock, the bit wide L of this shift register is 127, this shift register comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126, the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126, the output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with the first input end of 127 MUX M0～M126, the output of these 64 d type flip flop D0～D63 is also corresponding respectively to be connected with second input of 64 MUX M63～M126, the output of these 63 d type flip flop D64～D126 is also corresponding respectively to be connected with second input of 63 MUX M0～M62, the Enable Pin of these 127 MUX M0～M126 links together, enable to control the work of these 127 MUX M0～M126 by scrambling, the clock end of these 127 d type flip flop D0～D126 links together, and is controlled by the parallel clock of STM-64.
4. disturbance code generation device as claimed in claim 1, it is characterized in that: when M is 127, the data of required adding/descrambling are STM-16, be that N is 16 o'clock, the bit wide L of this shift register is 127, this shift register comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126, the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126, the output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with the first input end of 127 MUX M0～M126, the output of these 16 d type flip flop D0～D15 is also corresponding respectively to be connected with second input of 16 MUX M111～M126, the output of these 111 d type flip flop D16～D126 is also corresponding respectively to be connected with second input of 111 MUX M0～M110, the Enable Pin of these 127 MUX M0～M126 links together, enable to control the work of these 127 MUX M0～M126 by scrambling, the clock end of these 127 d type flip flop D0～D126 links together, and is controlled by the parallel clock of STM-16.
5. disturbance code generation device as claimed in claim 1, it is characterized in that: when M is 127, the data of required adding/descrambling are STM-4, be that N is 4 o'clock, the bit wide L of this shift register is 127, this shift register comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126, the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126, the output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with the first input end of 127 MUX M0～M126, the output of these 4 d type flip flop D0～D3 is also corresponding respectively to be connected with second input of 4 MUX M123～M126, the output of these 123 d type flip flop D4～D126 is also corresponding respectively to be connected with second input of 123 MUX M0～M122, the Enable Pin of these 127 MUX M0～M126 links together, enable to control the work of these 127 MUX M0～M126 by scrambling, the clock end of these 127 d type flip flop D0～D126 links together, and is controlled by the parallel clock of STM-4.
6. disturbance code generation device as claimed in claim 1, it is characterized in that: when M is 127, the data of required adding/descrambling are STM-1, be that N is 1 o'clock, the bit wide L of this shift register is 127, this shift register comprises 127 d type flip flop D0～D126 and 127 MUX M0～M126, the output of these 127 MUX M0～M126 is corresponding respectively to be connected with the input of 127 d type flip flop D0～D126, the output of these 127 d type flip flop D0～D126 is corresponding respectively to be connected with the first input end of 127 MUX M0～M126, the output of this d type flip flop D0 is connected with second input of MUX M126, the output of these 126 d type flip flop D1～D126 is also corresponding respectively to be connected with second input of 126 MUX M0～M125, the Enable Pin of these 127 MUX M0～M126 links together, enable to control the work of these 127 MUX M0～M126 by scrambling, the clock end of these 127 d type flip flop D0～D126 links together, and is controlled by the parallel clock of STM-1.
7. as each described disturbance code generation device of claim 1 to 6, it is characterized in that: described d type flip flop all has set function.
8. as each described disturbance code generation device of claim 1 to 6, it is characterized in that: described d type flip flop also can be for being transformed into the module of tool d type flip flop function by rest-set flip-flop or JK flip-flop.
9. as each described disturbance code generation device of claim 1 to 6, it is characterized in that: described MUX is 2 and selects 1 selector.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105530067A (en) * | 2015-12-08 | 2016-04-27 | 京信通信技术(广州)有限公司 | Parallel scrambling device and parallel scrambling method |
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| CN101610122B (en) * | 2009-07-03 | 2013-03-20 | 中兴通讯股份有限公司 | Parallel frame synchronous scrambling device and descrambling device thereof |
| CN101997570B (en) | 2009-08-12 | 2014-04-30 | 中兴通讯股份有限公司 | Method and device for generating scrambler |
| CN102025696B (en) * | 2009-09-16 | 2014-06-04 | 中兴通讯股份有限公司 | Parallel scrambling and descrambling processing device and method |
| CN102064912A (en) * | 2010-10-20 | 2011-05-18 | 武汉微创光电股份有限公司 | Line coding and decoding method for optical fibre transmission of high-speed digital signal |
| CN102065055A (en) * | 2011-01-14 | 2011-05-18 | 复旦大学 | Superfast parallel scrambler and descrambler in MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) system |
| CN104618051B (en) * | 2014-12-29 | 2018-03-30 | 曙光信息产业(北京)有限公司 | A kind of STM N frame B2 methods of calibration based on shift register |
| CN109586849A (en) * | 2018-12-17 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Data transmission method and device |
| CN114598416A (en) * | 2020-12-04 | 2022-06-07 | 华为技术有限公司 | Scrambling method, descrambling method, scrambling circuit and descrambling circuit |
| CN113613224A (en) * | 2021-07-23 | 2021-11-05 | 上海磐启微电子有限公司 | Bluetooth communication method based on 2.4G chip |
| CN114844599B (en) * | 2022-06-30 | 2022-12-02 | 北京国科天迅科技有限公司 | Method and device for synchronizing scrambler |
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