CN102025696B - Parallel scrambling and descrambling processing device and method - Google Patents

Abstract

The invention discloses a parallel scrambling and descrambling processing device and a parallel scrambling and descrambling processing method. The device comprises a generating module and a processing module, wherein the generating module is used for calculating to generate a k-bit parallel scrambling sequence according to a formula of Dn+k=Ak*Dn; and the processing module is used for performing scrambling and descrambling processing on the input data according to the k-bit parallel scrambling sequence generated by the generating module. Therefore, a fan-out coefficient of a low register can be reduced.

Description

Parallel disturbance code/descrambling code processing unit and method

Technical field

The present invention relates to communication field, relate in particular to a kind of parallel disturbance code/descrambling code processing unit and method.

Background technology

In communication system, signal is by bit serial transmission in transmitting procedure, but does not transmit the clock signal of this sending node, and the required data reception clock of receiving terminal is to extract the data-signal from receiving.According to conventional clock and data recovery (CDR) principle, clock recovery is to rely on the continuous variation (0 and 1) of data-signal to complete, if have long string 0 or long string 1 to occur in the data flow receiving, can not accurately recover receive clock, receive clock inaccuracy can cause loss of data or receive mistake.In order accurately to recover receive clock at receiving terminal, must in the data of transmission, prevent the appearance of long string 0 or long string 1.

For this reason, will carry out scrambled code to sending data at transmitting terminal, receiving terminal receives data-signal and carries out Clock Extraction, data receiver, descrambling and subsequent treatment again.In a Frame, some byte is without scrambled code, and some byte is wanted scrambled code.Which byte needs scrambled code, and different communication protocol is different to this regulation.As G.707 agreement regulation of ITU-T, the first row of STM-N Frame, without scrambled code, is carried out scrambled code since the second row, until a frame end.ITU-T G.709 agreement specifies, FAS (the Frame Alignment Signal of OTUk Frame, frame alignment signal) byte is without scrambled code, from MFAS (MultiFrame Alignment Signal, multiframe alignment signal) byte starts to carry out scrambled code, until a frame end.

Scrambler sequence generator polynomial can be expressed as conventionally $p\left(x\right)=x^p+c_{p-1}{x}^{p-1}+...+c_{1}x+1=\underset{i=0}{\overset{p}{\mathrm{\Σ}}}{c}_i{x}^i,$ Wherein c _iequal 0 or 1.If the ITU-T scrambler sequence generator polynomial that G.707 agreement is advised is x ⁷+ x ⁶+ 1, its circuit structure as shown in Figure 1.The ITU-T G.709 scrambler sequence generator polynomial of agreement suggestion is x ¹⁶+ x ¹²+ x ³+ x+1, its circuit structure as shown in Figure 2.In the time starting scrambler, all registers of scrambler should be set to 1, and the XOR logical calculated that the value of register is determined by multinomial afterwards obtains.Although the scrambler circuit structure shown in Fig. 1 and Fig. 2 is simple, but it is operated under wire rate, the high complex manufacturing that causes of operating frequency with high costsly even cannot realize under some high frequency clock, therefore must replace this serial scrambler with parallel disturbance code device in practice.

A kind of frame synchronization parallel disturbance code device of optical synchronization digital transmission system is provided in prior art.This scrambler generates parallel disturbance code sequence by 32 registers and 32 XOR gate, and the arithmetic logic of its 32 XOR gate closes and is:

d0 _n+32＝d2 _n^d3 _n^d4 _n^d6 _n

d1 _n+32＝d3 _n^d4 _n^d5 _n^d7 _n

d2 _n+32＝d1 _n^d4 _n^d5 _n^d6 _n^d7 _n

d3 _n+32＝d1 _n^d2 _n^d5 _n^d6 _n

d4 _n+32＝d2 _n^d3 _n^d6 _n^d7 _n

d5 _n+32＝d1 _n^d3 _n^d4 _n

d6 _n+32＝d2 _n^d4 _n^d5 _n

d7 _n+32＝d3 _n^d5 _n^d6 _n

d8 _n+32＝d4 _n^d6 _n^d7 _n

d9 _n+32＝d1 _n^d5 _n

d10 _n+32＝d2 _n^d6 _n

d11 _n+32＝d3 _n^d7 _n

d12 _n+32＝d1 _n^d4 _n^d7 _n

d13 _n+32＝d1 _n^d2 _n^d5 _n^d7 _n

d14 _n+32＝d1 _n^d2 _n^d3 _n^d6 _n^d7 _n

d15 _n+32＝d1 _n^d2 _n^d3 _n^d4 _n

d16 _n+32＝d2 _n^d3 _n^d4 _n^d5 _n

d17 _n+32＝d3 _n^d4 _n^d5 _n^d6 _n

d18 _n+32＝d4 _n^d5 _n^d6 _n^d7 _n

d19 _n+32＝d1 _n^d5 _n^d6 _n

d20 _n+32＝d2 _n^d6 _n^d7 _n

d21 _n+32＝d1 _n^d3 _n

d22 _n+32＝d2 _n^d4 _n

d23 _n+32＝d3 _n^d5 _n

d24 _n+32＝d4 _n^d6 _n

d25 _n+32＝d5 _n^d7 _n

d26 _n+32＝d1 _n^d6 _n^d7 _n

d27 _n+32＝d1 _n^d2 _n

d28 _n+32＝d2 _n^d3 _n

d29 _n+32＝d3 _n^d4 _n

d30 _n+32＝d4 _n^d5 _n

d31 _n+32＝d5 _n^d6 _n

Can find out d0 from the logical operation relation of above XOR gate _n+32～d31 _n+32value be all to pass through d1 _n～d7 _ncalculate, this must cause d0 _n～d7 _nthe XOR gate number driving is too much, and the fan-out of d0～d7 register is excessive.In the time that parallel figure place is higher (as 64 parallel-by-bit scramblers), d0～d7 will drive more XOR gate, causes this problem more serious.

Therefore,, for the above-mentioned excessive problem of low bit register fan-out, effective solution is not yet proposed in correlation technique.

Summary of the invention

Consider the prior art excessive problem of low bit register fan-out and make the present invention, for this reason, main purpose of the present invention is to provide a kind of parallel disturbance code/descrambling code processing unit and method, to solve the aforementioned problems in the prior.

According to an aspect of the present invention, provide a kind of parallel disturbance code/descrambling code processing unit.

According to the inventive system comprises: generation module, for according to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence; Processing module, carries out the processing of scrambler/descrambling code for the k parallel-by-bit scrambler sequence generating according to generation module to input data.

Preferably, scrambler sequence generation module comprises K/m scrambler sequence generation module, wherein, if the integral number power that the exponent number p of scrambler generator polynomial is 2, m=p; Otherwise, in the power that m value is 2, be greater than the minimum integer of p.

Preferably, each scrambler sequence generation module further comprises: buffer status computational logic module, for according to the value of each register in present clock period register group, utilize formula D _n+k=A ^k* D _ncalculate the value of next clock cycle, and result of calculation is saved in to corresponding register; Register group, it comprises m register, each register is for the result of calculation of save register state computation logic module.

Preferably, the initial value in register is: the original position of establishing scrambler data is positioned at j position, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position needs with being the front k-j-1 position of opposite sequence to the register of j+1 position, and wherein, backward is classified formula D as _n-1=B*D _nthe sequence obtaining, wherein B meets by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.

Preferably, processing module for carrying out the processing of scrambler/descrambling code in the time receiving Scramble_begin signal.

According to a further aspect in the invention, provide a kind of parallel disturbance code/descrambling code processing method.

The method according to this invention comprises: according to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence; According to the k parallel-by-bit scrambler sequence generating, input data are carried out to the processing of scrambler/descrambling code.

Preferably, k/m group scrambler sequence produces circuit evolving k parallel-by-bit scrambler sequence, and every group generates m parallel-by-bit scrambler sequence, wherein, if the integral number power that the exponent number p of scrambler generator polynomial is 2, m=p; Otherwise, in the power that m value is 2, be greater than the minimum integer of p.

Preferably, according to formula D _n+k=A ^k* D _ncalculating generation k parallel-by-bit scrambler sequence further comprises: according to the value of each register in present clock period register group, utilize formula D _n+k=A ^k* D _ncalculate the value of next clock cycle, and result of calculation is saved in to corresponding register.

Preferably, the initial value in register is: the original position of establishing scrambler data is positioned at j position, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position needs with being the front k-j-1 position of opposite sequence to the register of j+1 position, and wherein, backward is classified formula D as _n-1=B*D _nthe sequence obtaining, wherein B meets by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.

Preferably, in the time receiving Scramble_begin signal, carry out the processing of scrambler/descrambling code.

Compared with prior art, according to technique scheme of the present invention, make d0 _n+32～d31 _n+32value pass through d0 _n～d31 _ndrive multiple XOR gate to calculate, reduced the fan leaves coefficient of low bit register.

Brief description of the drawings

Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 is according to the ITU-T of prior art multinomial x G.707 ⁷+ x ⁶+ 1 electrical block diagram;

Fig. 2 is according to the ITU-T of prior art multinomial x G.709 ¹⁶+ x ¹²+ x ³the electrical block diagram of+x+1;

Fig. 3 is according to the block diagram of parallel disturbance code/descrambling code processing unit of the embodiment of the present invention;

Fig. 4 is the scrambler sequence original position schematic diagram according to the embodiment of the present invention;

Fig. 5 is the k position frame synchronization parallel disturbance code device schematic diagram according to the embodiment of the present invention;

Fig. 6 is to be x according to the multinomial of the embodiment of the present invention ⁷+ x ⁶+ 1 32 parallel-by-bit scrambler sequence generation module electrical block diagrams;

Fig. 7 is to be x according to the multinomial of the embodiment of the present invention ⁷+ x ⁶the schematic diagram of 32 frame synchronization parallel disturbance code devices of+1;

Fig. 8 is to be x according to the multinomial of the embodiment of the present invention ¹⁶+ x ¹²+ x ³the schematic diagram of 32 frame synchronization parallel disturbance code devices of+x+1;

Fig. 9 is according to the flow chart of parallel disturbance code/descrambling code processing method of the embodiment of the present invention.

Embodiment

Parallel disturbance code sequence generation circuit is divided into some groups by the present invention, and the circuit structure of every group is identical, therefore can improve the reuse efficiency of circuit, greatly saves design time.Every group of circuit contains m register and corresponding computational logic, and the computational logic of every group of circuit is just the same, the value that all calculates next and clap each register with the register of the m in this group.Only need, by giving different initial values to the register of each group of circuit, just can generate whole scrambler sequence.

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.

Device embodiment

According to embodiments of the invention, a kind of parallel disturbance code/descrambling code processing unit is proposed.

Fig. 3 is that as shown in Figure 3, this device comprises according to the block diagram of parallel disturbance code/descrambling code processing unit of the embodiment of the present invention:

Generation module 10, for according to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence;

Processing module 20, is connected with generation module 10, for the k parallel-by-bit scrambler sequence generating according to generation module 10, input data is carried out to the processing of scrambler/descrambling code.

Describe the details of above-mentioned processing below in detail.

Generation module 10 comprises K/m scrambler sequence generation module.Scrambler sequence generator polynomial can be expressed as conventionally $p\left(x\right)=x^p+c_{p-1}{x}^{p-1}+...+c_{1}x+1=\underset{i=0}{\overset{p}{\mathrm{\Σ}}}{c}_i{x}^i,$ Wherein, c _iequal 0 or 1.The exponent number of note scrambler sequence generator polynomial is p.If start the parallel figure place of scrambler and be k (k=8,16,32,64 ...).Parallel disturbance code sequence generation circuit is divided into k/m group, and every group generates m parallel-by-bit scrambler sequence, and k/m group scrambler sequence produces circuit and altogether generates k parallel-by-bit scrambler sequence.

If some powers that the exponent number p of scrambler generator polynomial is 2, m value is m=p, such as the G.709 scrambler sequence generator polynomial x of agreement suggestion of ITU-T ¹⁶+ x ¹²+ x ³+ x+1 is 16 rank, m=p=16.

If the exponent number p of scrambler generator polynomial is not some powers of 2, m value is to be greater than a number minimum in the power of p and 2, as the G.707 scrambler sequence generator polynomial x of agreement suggestion of ITU-T ⁷+ x ⁶+ 1 exponent number is 7 rank, and m should be greater than 7, meets and on the basis of this condition, from 2 n power, gets a minimum number, i.e. m=8.

According to the derive logical relation of the currency of m register and the value of next bat in every group of circuit of multinomial:

By multinomial $p\left(x\right)=\underset{i=0}{\overset{p}{\mathrm{\Σ}}}{c}_i{x}^i,$ If c _iin have j number to equal 1, the logical relation that can obtain serial scrambler is:

d(m-1) _n+1＝d(m-2) _n

d(m-2) _n+1＝d(m-3) _n

d1 _n+1＝d0 _n

This logical relation can be expressed in matrix as:

D _n+1＝A*D _n

Wherein:

D _n+1＝[d(m-1) _n+1，d(m-2) _n+1，…，d1 _n+1，d0 _n+1] ^T，

D _n＝[d(m-1) _n，d(m-2) _n，…，d1 _n，d0 _n] ^T，

$A_{m\&times;m}=\left[\begin{array}{ccccc}{c}_1& c_2& ...& c_{p-1}& {\mathrm{<figure-callout\; id="1"\; label="c\; p"\; filenames="H2009101734181E00022.png"\; state="\{\{state\}\}">c</figure-callout>}}_p\\ 1& 0& ...& 0& 0\\ 0& 1& ...& 0& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ 0& 0& ...& 1& 0\end{array}\right]$ (in the time of m=p), or

$A_{m\&times;m}=\left[\begin{array}{ccccccccc}{c}_1& c_2& ...& c_{p-1}& {\mathrm{<figure-callout\; id="0"\; label="c\; p"\; filenames="H2009101734181E00022.png"\; state="\{\{state\}\}">c</figure-callout>}}_p& 0& ...& 0& 0\\ 1& 0& ...& 0& 0& 0& ...& 0& 0\\ 0& 1& ...& 0& 0& 0& ...& 0& 0\\ .& .& .& .& .& .& .& .& .\\ .& .& .& .& .& .& .& .& .\\ .& .& .& .& .& .& .& .& .\\ 0& 0& ...& 0& 0& 0& ...& 1& 0\end{array}\right]$ (in the time that m is greater than p)

Matrix A _{m × m}the 2nd row all meet to the capable element of m: a _{i, i-1}=1, all the other are 0.

By serial scrambler logical relation D _n+1=A*D _nthe logical relation that can obtain k parallel-by-bit scrambler is D _n+k=A ^k* D _n(because same number in XOR oneself is 0 with own phase XOR result, so should, to 2 deliverys, relate to being not always the case of matrix multiple, no longer in addition explanation herein below after two matrix multiples).

Determine register initial value: because the original position difference of the scrambler data that each agreement specifies, so in k parallel-by-bit scrambler, the original position of scrambler is also different.If the original position of scrambler data is positioned at j position, as shown in Figure 4, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position is the front k-j-1 position of opposite sequence to the register of j+1 position.If (by formula D _n+1=A*D _nthe sequence obtaining is called positive sequence, claims by formula D _n-1=B*D _nthe sequence obtaining is opposite sequence, and wherein B meets: by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.Scrambler sequence and opposite sequence are all the definite pseudo random sequences being determined by scrambler multinomial.)

The circuit structure of k position frame synchronization parallel disturbance code device as shown in Figure 5, is made up of the individual scrambler sequence generation module of n (n=k/m) and an add/scramble process module (being the processing module shown in Fig. 3).

Scrambler sequence generation module is used for generating k parallel-by-bit scrambler sequence, and each scrambler sequence generation module generates m position scrambler sequence, and the symbiosis of n scrambler sequence generation module becomes k parallel-by-bit scrambler sequence.The circuit structure of this n scrambler sequence generation module is identical.

In scrambler sequence generation module, comprise a register group and a buffer status computational logic module.

Register group is made up of m register.

The logic function that buffer status computational logic module realizes can be by formula D _n+k=A ^k* D _nobtain.

In the time that Scramble_begin signal is effective, represent to start scrambler, give respectively initial value 1～initial value n to each register group, as shown in Figure 5.After this each clock same period, buffer status computational logic module, according to the value of each register in present clock period register group, calculates the value of next each register of clock cycle, and result of calculation is saved in to corresponding register.

Add/scramble process module is responsible for the k bit data Data_in of input to carry out scrambled code or descrambling code processing.In a Frame, not every data are all wanted scrambler, are generally that a frame starts several bytes without scrambler, and byte thereafter is all wanted scrambler.The original position of a frame of signal fp_in instruction, in the time that fp_in signal arrives, need not carry out scrambler to the data Data_in of input, and Scrambled/Descrambled data out directly exports the data of Data_in input; In the time that arriving, Scramble_begin signal starts scrambler, k parallel-by-bit scrambler sequence and Data_in that add/scramble process module generates n scrambler sequence generation module carry out step-by-step XOR, and result is the data of Scrambled/Descrambled data out output.

Below respectively with ITU-T G.707, ITU-T G.709 the scrambler multinomial of agreement suggestion further illustrate as example as 32 taking the figure place that walks abreast.

The ITU-T G.707 scrambler multinomial of agreement suggestion is x ⁷+ x ⁶+ 1, scrambler multinomial exponent number is p=7, gets m=8, can obtain A by scrambler multinomial to be:

$A_{8\&times;8}=\left[\begin{array}{cccccccc}0& 0& 0& 0& 0& 1& 1& 0\\ 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 0& 0\\ 0& 0& 0& 0& 1& 0& 0& 0\\ 0& 0& 0& 0& 0& 1& 0& 0\\ 0& 0& 0& 0& 0& 0& 1& 0\end{array}\right]$

Can be by formula D _n+32=D _{8 × 8} ³²* D _nthe logic function that obtains buffer status computational logic module the inside is:

d0 _n+32＝d2 _n^d3 _n^d4 _n^d6 _n

d1 _n+32＝d0 _n^d3 _n^d4 _n^d5 _n^d6 _n

d2 _n+32＝d0 _n^d1 _n^d4 _n^d5 _n

d3 _n+32＝d1 _n^d2 _n^d5 _n^d6 _n

d4 _n+32＝d0 _n^d2 _n^d3 _n

d5 _n+32＝d1 _n^d3 _n^d4 _n

d6 _n+32＝d2 _n^d4 _n^d5 _n

d7 _n+32＝d3 _n^d5 _n^d6 _n

Multinomial is x ⁷+ x ⁶+ 1 32 parallel-by-bit scrambler sequence generation module circuit structures as shown in Figure 6, are made up of register group and buffer status computational logic module.In register group, have 8 registers, the logic function of buffer status computational logic module is foregoing logical relation.

ITU-T G.707 regulation STM-N frame since the second row scrambler, so scrambler sequence is just since the highest order (MSB) of 32 parallel-by-bit scramblers, therefore the initial value of 32 bit registers is scrambler sequence first 32: fe04_1851 (hexadecimal representation), is shown with binary form: 11111110_00000100_000110000_1010001.

Multinomial is x ⁷+ x ⁶32 frame synchronization parallel disturbance code device circuit structures of+1 as shown in Figure 7, are made up of 4 scrambler sequence generation modules and an add/scramble process module.Each scrambler sequence generation module generates 8 parallel-by-bit scrambler sequence, and the symbiosis of 4 scrambler sequence generation modules becomes the parallel disturbance code sequence of 32.

In the time that Scramble_begin signal is effective, represent to start scrambler, each register group is given respectively initial value 11111110,00000100,00011000,01010001 (as shown in Figure 7).After this each clock same period, buffer status computational logic, according to the value of each register in present clock period register group, calculates the value of next each register of clock cycle, and result of calculation is saved in to corresponding register.

Add/scramble process module is responsible for 32 bit data Data_in of input to carry out scrambled code or descrambling code processing.TIU-T G.707 agreement regulation STM-N frame carries out scrambler since the second row.The original position of a frame of signal fp_in instruction, in the time that fp_in signal arrives, need not carry out scrambler to the data Data_in of input.The position that Scramble_begin instruction scrambler starts, in the time that arriving, Scramble_begin signal starts scrambler, 32 parallel-by-bit scrambler sequence and Data_in that add/scramble process module generates 4 scrambler sequence generation modules carry out step-by-step XOR, and result is the data of Scrambled/Descrambled data out output.

The ITU-T G.709 scrambler multinomial of agreement suggestion is x ¹⁶+ x ¹²+ x ³+ x+1, scrambler multinomial exponent number is p=16, gets m=p=16, can obtain A by scrambler multinomial to be:

$A_{16\&times;16}=\left[\begin{array}{cccccccccccccccc}1& 0& 1& 0& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 1\\ 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0\\ .& .& .& .& .& .& .& .& .& .& .& .& .& .& .& .\\ .& .& .& .& .& .& .& .& .& .& .& .& .& .& .& .\\ .& .& .& .& .& .& .& .& .& .& .& .& .& .& .& .\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1& 0\end{array}\right]$

Can be by formula D _n+32=A _{16 × 16} ³²* D _nthe logic function that obtains buffer status computational logic module the inside is:

d0 _n+32＝d3 _n^d5 _n^d8 _n^d12 _n^d14 _n^d15

d1 _n+32＝d0 _n^d1 _n^d3 _n^d4 _n^d6 _n^d9 _n^d12 _n^d13 _n^d15

d2 _n+32＝d0 _n^d2 _n^d3 _n^d4 _n^d5 _n^d7 _n^d10 _n^d12 _n^d13 _n^d14

d3 _n+32＝d1 _n^d3 _n^d4 _n^d5 _n^d6 _n^d8 _n^d11 _n^d13 _n^d14 _n^d15

d4 _n+32＝d0 _n^d1 _n^d2 _n^d3 _n^d4 _n^d5 _n^d6 _n^d7 _n^d9 _n^d14 _n^d15

d5 _n+32＝d0 _n^d2 _n^d4 _n^d5 _n^d6 _n^d7 _n^d8 _n^d10 _n^d12 _n^d15

d6 _n+32＝d0 _n^d5 _n^d6 _n^d7 _n^d8 _n^d9 _n^d11 _n^d12 _n^d13

d7 _n+32＝d1 _n^d6 _n^d7 _n^d8 _n^d9 _n^d10 _n^d12 _n^d13 _n^d14

d8 _n+32＝d2 _n^d7 _n^d8 _n^d9 _n^d10 _n^d11 _n^d13 _n^d14 _n^d15

d9 _n+32＝d0 _n^d1 _n^d8 _n^d9 _n^d10 _n^d11 _n^d14 _n^d15

d10 _n+32＝d0 _n^d2 _n^d3 _n^d9 _n^d10 _n^d11 _n^d15

d11 _n+32＝d0 _n^d4 _n^d10 _n^d11

d12 _n+32＝d1 _n^d5 _n^d11 _n^d12

d13 _n+32＝d2 _n^d6 _n^d12 _n^d13

d14 _n+32＝d3 _n^d7 _n^d13 _n^d14

d15 _n+32＝d4 _n^d8 _n^d14 _n^d15

ITU-T G.709 agreement regulation OTU frame starts to carry out scrambler from MFAS byte (the 7th byte), in 32 parallel-by-bit scramblers, while starting scrambler, MFAS and subsequent a byte are just in low 16, high 16 need not be carried out scrambler, low 16 will be carried out scrambler, and all bytes all will be carried out scrambler afterwards.Therefore register initial value is: get first 16 of scrambler sequence for low 16, get first 16 of opposite sequence for high 16.The initial value that obtains thus register is: initial value 1=90f0, initial value 2=ffff, is shown with binary form: 10010000_11110000_11111111_11111111.

Multinomial is x ¹⁶+ x ¹²+ x ³the circuit structure of 32 frame synchronization parallel disturbance code devices of+x+1 as shown in Figure 8, adds descrambling code processing module by 2 scrambler sequence generation modules and one and forms.

Each scrambler sequence generation module comprises a register group and a buffer status computational logic module.Each register group includes 16 registers.The logic function that buffer status computational logic module realizes is foregoing logical relation.Each scrambler sequence generation module generates 16 parallel-by-bit scrambler sequence, and 2 scrambler sequence generation modules generate the parallel disturbance code sequence of 32 together.

In the time that Scramble_begin signal is effective, represent to start scrambler, each register group is given respectively initial value 1001000011110000,1111111111111111.After this each clock same period, buffer status computational logic, according to the value of each register in present clock period register group, calculates the value of next each register of clock cycle, and result of calculation is saved in to corresponding register.

Add/scramble process module is responsible for 32 bit data Data_in of input to carry out scrambled code or descrambling code processing.TIU-T G.709 agreement regulation OTU frame starts to carry out scrambler from MFAS byte (the 7th byte).The original position of a frame of signal fp_in instruction, in the time that fp_in signal arrives, need not carry out scrambler to the data Data_in of input.The position that Scramble_begin instruction scrambler starts, in the time that arriving, Scramble_begin signal starts scrambler, 32 parallel-by-bit scrambler sequence and Data_in that add/scramble process module generates 2 scrambler sequence generation modules carry out step-by-step XOR, and result is the data of Scrambled/Descrambled data out output.

Embodiment of the method

According to embodiments of the invention, a kind of parallel disturbance code/descrambling code processing method is also provided, the method can be realized by said apparatus embodiment.

Fig. 9 shows the flow chart of parallel disturbance code/descrambling code processing method of system according to the invention embodiment, and as shown in Figure 9, the method comprises:

S902, according to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence;

S904, carries out the processing of scrambler/descrambling code according to the k parallel-by-bit scrambler sequence generating to input data.

Wherein, k/m group scrambler sequence produces circuit evolving k parallel-by-bit scrambler sequence, and every group generates m parallel-by-bit scrambler sequence, wherein, if the integral number power that the exponent number p of scrambler generator polynomial is 2, m=p; Otherwise, in the power that m value is 2, be greater than the minimum integer of p.

S902 specifically comprises: according to the value of each register in present clock period register group, utilize formula D _n+k=A ^k* D _ncalculate the value of next clock cycle, and result of calculation is saved in to corresponding register.The regulation of register initial value comprises: the original position of establishing scrambler data is positioned at j position, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position needs with being the front k-j-1 position of opposite sequence to the register of j+1 position, and wherein, backward is classified formula D as _n-1=B*D _nthe sequence obtaining, wherein B meets by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.

In S904, while receiving Scramble_begin signal, carry out the processing of scrambler/descrambling code.

To sum up, the technique scheme according to the present invention, is divided into some groups by parallel disturbance code sequence generation circuit, and the circuit structure of every group is identical, has improved the reuse efficiency of circuit, greatly saves design time.Every group of circuit contains m register and corresponding computational logic, and the computational logic of every group of circuit is identical, the value that all calculates next and clap each register with the register of the m in this group.By giving different initial values to the register of each group of circuit, just can generate whole scrambler sequence, make d0 _n+32～d31 _n+32value pass through d0 _n～d31 _ndrive multiple XOR gate to calculate, reduced the fan leaves coefficient of low bit register.

The foregoing is only embodiments of the invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in claim scope of the present invention.

Claims (4)

1. parallel disturbance code/descrambling code processing unit, is characterized in that, comprising:

Generation module, for according to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence;

Processing module, carries out the processing of scrambler/descrambling code for the described k parallel-by-bit scrambler sequence generating according to described generation module to input data;

Wherein, k is the figure place of parallel disturbance code sequence, and A is scrambler polynomial matrix, D _nfor the capable column matrix of k being formed by present input data;

Wherein,

Described generation module comprises k/m scrambler sequence generation module, wherein, if the integral number power that the exponent number p of scrambler generator polynomial is 2, m=p; Otherwise, in the power that m value is 2, be greater than the minimum integer of p;

Each described scrambler sequence generation module further comprises: buffer status computational logic module, for according to the value of each register in present clock period register group, utilize formula D _n+k=A ^k* D _ncalculate the value of next clock cycle, and result of calculation is saved in to corresponding register;

Register group, it comprises m register, each described register is for preserving the result of calculation of described buffer status computational logic module;

Initial value in described register is: the original position of establishing scrambler data is positioned at j position, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position needs with being the front k-j-1 position of opposite sequence to the register of j+1 position, and wherein, described backward is classified formula D as _n-1=B*D _nthe sequence obtaining, wherein B meets by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.

2. device as claimed in claim 1, is characterized in that, described processing module is for carrying out the processing of scrambler/descrambling code receiving when scrambler starts Scramble_begin signal.

3. parallel disturbance code/descrambling code processing method, is characterized in that, comprising:

According to formula D _n+k=A ^k* D _ncalculate and generate k parallel-by-bit scrambler sequence;

According to the described k parallel-by-bit scrambler sequence generating, input data are carried out to the processing of scrambler/descrambling code;

Wherein,

K is the figure place of parallel disturbance code sequence, and A is scrambler polynomial matrix, D _nfor the capable column matrix of k being formed by present input data;

K/m group scrambler sequence produces circuit evolving k parallel-by-bit scrambler sequence, and every group generates m parallel-by-bit scrambler sequence, wherein, if the integral number power that the exponent number p of scrambler generator polynomial is 2, m=p; Otherwise, in the power that m value is 2, be greater than the minimum integer of p;

Described according to formula D _n+k=A ^k* D _ncalculating generation k parallel-by-bit scrambler sequence further comprises: according to the value of each register in present clock period register group, utilize formula D _n+k=A ^k* D _ncalculate the value of next clock cycle, and result of calculation is saved in to corresponding register;

Initial value in described register is: the original position of establishing scrambler data is positioned at j position, the front j position that the register initial value of 0 of j position to the is scrambler sequence; K-1 position needs with being the front k-j-1 position of opposite sequence to the register of j+1 position, and wherein, described backward is classified formula D as _n-1=B*D _nthe sequence obtaining, wherein B meets by D _n-1=B*D _nthe D trying to achieve _n-1make formula D _n=A*D _n-1set up.

4. method as claimed in claim 3, is characterized in that, carries out the processing of scrambler/descrambling code receiving when scrambler starts Scramble_begin signal.

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