CN111225301B - Device and method for mutual conversion between 8B/10B code and 64B/66B code - Google Patents

Abstract

The invention discloses a device and a method for mutual conversion between 8B/10B coding and 64B/66B coding, which comprises an 8-to-64 module and a 64-to-8 module, wherein for the 8-to-64 module: the 8 groups of 8-bit data obtained after the data received by the 8 channels are decoded are packaged into a group of 64-bit data, and the 64-bit data is subjected to 64B/66B coding and then is transmitted at high speed, so that the conversion from 8B/10B coding to 64B/66B coding is realized; for the 64-to-8 module: and decoding and restoring the data received from the transmitting end into 8-bit data of 8 groups of corresponding channels, and then transmitting the data after 8B/10B coding to realize the conversion from 64B/66B coding to 8B/10B coding. The invention greatly reduces the using amount of optical fibers and the laying cost of the optical fibers, and can improve the 1.25Gbps rate of PON port data transmission to 10Gbps rate through 64B/66B coding, thereby greatly improving the remote transmission speed.

Description

Device and method for mutual conversion between 8B/10B code and 64B/66B code

Technical Field

The invention relates to the technical field of networks, in particular to a device and a method for mutual conversion between 8B/10B codes and 64B/66B codes.

Background

Today, with the rapid development of network communication, the requirements for signal rate quality and the like are higher and higher. The network communication generally adopts a high-speed serial transmission mode, signals need to be coded so that the signals have sufficiently dense level conversion, and then the correct transmission of the signals can be ensured, wherein the gigabit rate adopts the most extensive 8B10B coding technology and is used for serial SCSI, serial ATA, optical fiber links, gigabit Ethernet, PCIExpress bus and the like. With the increasing demand for bandwidth, in order to reduce the coding overhead and reduce the complexity of hardware, the IEEE 802.3 working group has proposed a 64B/66B coding technique for 10G ethernet, which is mainly applied to Fiber Channel 10GFC and 16GFC, 10G ethernet, 100G ethernet, 10G EPON, InfiniBand, Thunderbolt and Xilinx Aurora protocols, etc.

The PON (passive Optical Network) is that (in an Optical Distribution Network) the PON does not contain any electronic device and electronic power supply, the ODN is composed of all passive devices such as an Optical Splitter (Splitter), and does not need expensive active electronic equipment, and the structure mainly includes an Optical Line Terminal (OLT) of a central office, an Optical Distribution Network (ODN) including the passive Optical device, and an Optical Network Unit/Optical Network Terminal (ONU/ONT Optical Network Unit/Optical Network Terminal) of a user side.

For an Optical Line Terminal (OLT), a single-fiber bidirectional Optical transmission network with a point-to-multipoint (P2MP) structure is adopted for a PON port of the OLT, a Wavelength Division Multiplexing (WDM) technology with a combination of downstream 1490 nm/upstream 1310nm wavelengths is adopted for a single Optical fiber, a Time Division Multiplexing (TDM) technology is used in a point-to-point mode for an upstream direction, a broadcast mode is used in a downstream direction, a sending rate is 1.25Gbps, encoded data of 8B/10B is adopted for transmission, each PON port can only be transmitted by an independent Optical fiber, that is, 8 independent Optical fibers are used for transmitting each PON data by the OLT of 8 PONs, which requires a large amount of Optical fiber materials and Optical fiber laying cost for PON long-distance transmission, and transmission distance and speed are not high. Therefore, when pon remote transmission is performed, if only one optical fiber is used for transmitting multi-channel pon data, the optical fiber and labor cost can be greatly saved, and the single optical fiber for transmitting multi-channel data becomes very important.

The invention processes the problem of data transmission delay by carrying out data detection on 8 channels of pon channel data, then combines the data into 64-bit data to carry out 10Gbit/s rate transmission, and splits the data at a receiving end to carry out data reception on corresponding 8 channels, thereby solving the problem of remotely transmitting the data of the multiple channels of pon by a single optical fiber and effectively improving the transmission rate.

Disclosure of Invention

The invention aims to solve the problems that: the data received from the 8-path independent PON port and transmitted at the 8B/10B coding rate and the 1.25Gpbs rate are transmitted at the 64B/66B coding rate and the 10Gbps rate through a single optical fiber, and the combined data is subjected to effective data judgment and is split into corresponding receiving channels.

In order to solve the technical problems, the invention adopts the following technical means:

an apparatus for interconversion between 8B/10B coding and 64B/66B coding, comprising an 8-to-64 module and a 64-to-8 module, wherein the 8-to-64 module comprises:

the channels 1 to 8 are used for transmitting 8 groups of 10bit data;

the buffers 1 to 8 are correspondingly connected with the channels 1 to 8 one by one and used for buffering 8 groups of 10-bit data;

8B/10B decoding units 1 to 8B/10B decoding units 8 which are correspondingly connected with the buffers 1 to 8 one by one and used for converting 8 groups of 10-bit data to be transmitted into 8 groups of 8-bit data;

an 8-to-64 unit connected with the 8B/10B decoding units 1-8B/10B decoding unit 8 and used for decoding 8 channels and then synthesizing 8 groups of 8-bit data output in parallel into a group of 64-bit data;

the data delay processing unit is connected with the channels 1 to 8, the buffers 1 to 8 and the 8-to-64 unit, and is used for detecting data of 8 channels, triggering the buffers of 8 channels and the 8-to-64 unit to transmit data to a lower stage after a certain time, so as to solve the problem of data transmission delay;

the 64B/66B coding unit is connected with the 8-to-64 unit and is used for converting 64-bit data to be transmitted into 66-bit data;

the 66B data transmission unit is connected with the 64B/66B coding unit and is used for transmitting 66bit data;

the 64-to-8 module includes:

a 64B/66B decoding unit which is connected with the 66B data transmission unit and is used for converting 66bit data to be transmitted into 64bit data;

a 64-to-8 unit connected with the 64B/66B decoding unit and used for splitting a group of received decoded 64-bit data into 8 groups of 8-bit data and outputting the 8 groups of 8-bit data to 8 corresponding channels for detection;

the control code detection unit 1 to the control code detection unit 8 are connected with the 64-to-8 unit and used for detecting a control start code and an end code, and from the detection of the start code to the detection of the end code at the back, the middle data is considered as valid data, otherwise, the channel is considered not to be subjected to data transmission, and the received data is invalid data and discarded so as to solve the problems that the data delay of a sending end is too large or the data transmission is not carried out;

8B/10B coding units 1 to 8B/10B coding units 8 which are correspondingly connected with the control code detection unit 1 to the control code detection unit 8 one by one and used for converting 8 groups of 8bit data to be transmitted into 8 groups of 10bit data;

the channel 1 transmission unit to the channel 8 transmission unit are correspondingly connected with the 8B/10B coding units 1 to 8B/10B coding units 8 one by one and are used for transmitting 8 groups of 10bit data.

Further, the data delay processing unit specifically includes the following steps:

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, a data delay processing unit carries out independent data detection on the 8 channels, the zone bit D is set to be 0 when the data is detected, for example, the 2 nd path and the 5 th path have data, the D [7:0] is changed into 11101101, and the triggered zone bit D cannot be repeatedly triggered before the D recovers the initial state, namely the 11111111 state;

step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period; when the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

Further, the 8-to-64 unit specifically comprises the following steps:

step TS 201: each channel buffer outputs 10bit data, and the existing 8B/10B decoding IP core is adopted to decode 8B/10B coded data and then output in parallel;

step TS 202: defining 8 parallel input and parallel output registers T [7:0] with 8 bits, totally 64 bits, and respectively mapping 8-bit parallel data of 8 channels;

step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

Further, the 64-to-8 unit specifically comprises the following steps:

step RS 101: the existing 64B/66B decoding IP core is adopted, and the data coded by 64B/66B is decoded and then output in parallel;

step RS 102: : the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

Further, the control code detection unit specifically includes: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'; in any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

A method for converting 8B/10B code and 64B/66B code is divided into 8 to 64 modules, namely 8B/10B code to 64B/66B code; a 64-to-8 module, i.e., 64B/66B coding to 8B/10B coding, wherein:

the 8-to-64 module comprises the following steps:

step TS 1: 8 channel data detection is carried out, and a synchronous signal SYN control buffer is output and 8-to-64 units output data to the lower stage;

step TS 2: the 8-to-64 unit decodes the 8-path data and then merges the 8-path data into a group of 64-bit data;

step TS 3: carrying out 64B/66B coding transmission on 64bit data;

the 64-to-8 module comprises the following steps:

step RS 1: the data transmitted from the 8-to-64 module is decoded and split into 8 groups of 8-bit data and distributed to corresponding 8 channels;

step RS 2: each channel detects the control code of the received 8bit data;

step RS 3: each channel performs 8B/10B encoded transmission of 8bit data.

Further, step TS1 specifically includes:

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, a data delay processing unit carries out independent data detection on the 8 channels, the zone bit D is set to be 0 when the data is detected, for example, the 2 nd path and the 5 th path have data, the D [7:0] is changed into 11101101, and the triggered zone bit D cannot be repeatedly triggered before the D recovers the initial state, namely the 11111111 state;

step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period; when the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

Further, the unit 8 to 64 in the step TS2 specifically includes:

step TS 201: each channel buffer outputs 10bit data, and the existing 8B/10B decoding IP core is adopted to decode 8B/10B coded data and then output in parallel;

step TS 202: defining 8 parallel input and parallel output registers T [7:0] with 8 bits, totally 64 bits, and respectively mapping 8-bit parallel data of 8 channels;

step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

Further, the unit of 64 to 8 in the step RS1 specifically includes:

step RS 101: the existing 64B/66B decoding IP core is adopted, and the data coded by 64B/66B is decoded and then output in parallel;

step RS 102: the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

Further, the step RS2 specifically includes: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'; in any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention uses single optical fiber to transmit multi-channel PON information, and increases the transmission rate to 10Gpbs, thus greatly saving the optical fiber cost and transmission rate of long-distance optical fiber transmission.

2. The invention accords with the 8B/10B coding and decoding and 64B/66B coding and decoding specifications, can utilize the existing coding and decoding IP core, and has high-efficiency and simple logic development. I is

3. The invention can effectively solve the problem of delay of each path of PON channel data or no effective data transmission through data detection.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of an 8-to-64 module of the present invention (due to the size relationship of the drawings, 2-7 channels are omitted and not shown, and the process is the same as that of the channel 1 and the channel 8);

FIG. 2 is a schematic diagram of a 64-to-8 module according to the present invention (due to the size relationship of the drawings, 2-7 channels are omitted and not shown, and the process is the same as that of the channels 1 and 8);

FIG. 3 is a diagram illustrating the operation steps of the data delay processing unit according to the present invention;

FIG. 4 is a schematic diagram of the 8-to-64 unit of the present invention;

fig. 5 is a schematic diagram of the 64-to-8 unit principle of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

8B/10B coding converts 8-bit data to be transmitted into 10-bit code-groups with the purpose of ensuring DC-balance and sufficiently dense level conversion. The 8bit raw data can be divided into two parts: the 8-bit data can be recorded as d.x.y if the lower 5-bit EDCBA (assuming its decimal value X) and the upper 3-bit HGF (assuming its decimal value Y). In addition, 12 control characters are also used in 8B/10B coding, which can be used as status identifiers of frame start, frame end, transmission idle, etc. in transmission, similar to the notation of data characters, the control characters are generally denoted as k.x.y. In 8B/10B coding, K28.1, K28.5 and K28.7 are used as control characters of a K code and are called as 'comma'. In any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma characters may be used to indicate the start and end flags of the frame, or to always correct the control character for alignment with the data stream.

The 64B/66B coding technique is proposed by the IEEE 802.3 working group for 10G Ethernet, in order to reduce coding overhead, reduce hardware complexity, and as an alternative to 8B/10B coding to support new programs and data. The 64B/66B coding encodes 64-bit data or control information into 66-bit blocks for transmission, and the first two bits of the 66-bit block represent the synchronization header, mainly due to data alignment at the receiving end and synchronization of the received data bit stream. The synchronous head has two kinds of '01' and '10', the '01' indicates that the following 64 bits are both data, the '10' indicates that the following 64 bits are the mixture of data and control information, and the 64-bit data can be transmitted after being scrambled. The scrambler used for 64B/66B encoding is X58+ X39+1.

FPGA (field Programmable Gate array) is a product of further development on the basis of Programmable devices such as PAL, GAL and the like. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), has the characteristics of rich wiring resources, high repeatable programming and integration level and low investment, overcomes the defects of custom circuits, overcomes the defect of limited gate circuits of the original programmable devices, and is widely applied in the field of digital circuit design.

Example 1

The invention provides a device for mutual conversion between 8B/10B coding and 64B/66B coding, which comprises an 8-to-64 module and a 64-to-8 module, wherein the 8-to-64 module comprises (referring to fig. 1):

the channels 1 to 8 are used for transmitting 8 groups of 10bit data;

the buffers 1 to 8 are correspondingly connected with the channels 1 to 8 one by one and used for buffering 8 groups of 10-bit data;

8B/10B decoding units 1 to 8B/10B decoding units 8 which are correspondingly connected with the buffers 1 to 8 one by one and used for converting 8 groups of 10-bit data to be transmitted into 8 groups of 8-bit data;

an 8-to-64 unit connected with the 8B/10B decoding units 1-8B/10B decoding unit 8 and used for decoding 8 channels and then synthesizing 8 groups of 8-bit data output in parallel into a group of 64-bit data;

the data delay processing unit is connected with the channels 1 to 8, the buffers 1 to 8 and the 8-to-64 unit, and is used for detecting data of 8 channels, triggering the buffers of 8 channels and the 8-to-64 unit to transmit data to a lower stage after a certain time, so as to solve the problem of data transmission delay;

the 64B/66B coding unit is connected with the 8-to-64 unit and is used for converting 64-bit data to be transmitted into 66-bit data;

the 66B data transmission unit is connected with the 64B/66B coding unit and is used for transmitting 66bit data;

the 64-to-8 module includes (with reference to fig. 2):

a 64B/66B decoding unit which is connected with the 66B data transmission unit and is used for converting 66bit data to be transmitted into 64bit data;

a 64-to-8 unit connected with the 64B/66B decoding unit and used for splitting a group of received decoded 64-bit data into 8 groups of 8-bit data and outputting the 8 groups of 8-bit data to 8 corresponding channels for detection;

the control code detection unit 1 to the control code detection unit 8 are connected with the 64-to-8 unit and used for detecting a control start code and an end code, and from the detection of the start code to the detection of the end code at the back, the middle data is considered as valid data, otherwise, the channel is considered not to be subjected to data transmission, and the received data is invalid data and discarded so as to solve the problems that the data delay of a sending end is too large or the data transmission is not carried out;

8B/10B coding units 1 to 8B/10B coding units 8 which are correspondingly connected with the control code detection unit 1 to the control code detection unit 8 one by one and used for converting 8 groups of 8bit data to be transmitted into 8 groups of 10bit data;

the channel 1 transmission unit to the channel 8 transmission unit are correspondingly connected with the 8B/10B coding units 1 to 8B/10B coding units 8 one by one and are used for transmitting 8 groups of 10bit data.

Specifically, the data delay processing unit specifically includes the following steps (refer to fig. 3):

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, a data delay processing unit carries out independent data detection on the 8 channels, the zone bit D is set to be 0 when the data is detected, for example, the 2 nd path and the 5 th path have data, the D [7:0] is changed into 11101101, and the triggered zone bit D cannot be repeatedly triggered before the D recovers the initial state, namely the 11111111 state;

step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period; when the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

Specifically, the 8-to-64 unit specifically includes the following steps (refer to fig. 4):

step TS 201: each channel buffer outputs 10bit data, and the existing 8B/10B decoding IP core is adopted to decode 8B/10B coded data and then output in parallel;

step TS 202: defining 8 parallel input and parallel output registers T [7:0] with 8 bits, totally 64 bits, and respectively mapping 8-bit parallel data of 8 channels;

step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

Specifically, the 64-to-8 unit specifically includes the following steps (see fig. 5):

step RS 101: the existing 64B/66B decoding IP core is adopted, and the data coded by 64B/66B is decoded and then output in parallel;

step RS 102: : the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

Specifically, the control code detection unit specifically includes: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'; in any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

The invention relates to a device for mutual conversion between 8B/10B coding and 64B/66B coding, which performs data detection and 8B/10B decoding on 8 channels to obtain 8 groups of 8-bit data, then combines the 8 groups of 8-bit data into a group of 64-bit data, performs 64B/66B coding and then transmits the data, and a 64-to-8 module splits the 64B/66B data into 8 groups of 8-bit data after decoding the data, performs control code detection and transmits the data after judging the data to be effective data.

Example 2

The invention also provides a method for converting 8B/10B codes into 64B/66B codes, which is divided into 8-to-64 modules, namely 8B/10B codes into 64B/66B codes; and a 64-to-8 module, namely 64B/66B coding to 8B/10B coding.

The 8-to-64 module comprises the following steps:

step TS 1: 8 channel data detection is carried out, and a synchronous signal SYN control buffer is output and 8-to-64 units output data to the lower stage;

step TS 2: the 8-to-64 unit decodes the 8-path data and then merges the 8-path data into a group of 64-bit data;

step TS 3: 64B/66B encoded transmission is performed on 64bit data.

The 64-to-8 module comprises the following steps:

step RS 1: the data transmitted from the 8-to-64 module is decoded and split into 8 groups of 8-bit data and distributed to corresponding 8 channels;

step RS 2: each channel detects the control code of the received 8bit data;

step RS 3: each channel carries out 8B/10B coding transmission on 8bit data;

in the above technical solution, step TS1 specifically includes, with reference to fig. 3:

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, carrying out independent data detection on the 8 channels by a data delay processing unit, corresponding to the zone bit D position 0 when detecting data, for example, when detecting that a 2 nd path and a 5 th path have data, changing the D [7:0] into 11101101, and before the D recovers the initial state, namely the 11111111111 state, triggering the triggered zone bit D repeatedly.

Step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period. When the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

In the above technical solution, the step TS 28 to 64 specifically includes, referring to fig. 4:

step TS 201: each channel buffer outputs 10bit data, the existing 8B/10B decoding IP core is adopted, and 8B/10B coded data are decoded and then output in parallel.

Step TS 202: 8-bit parallel input-parallel output registers T [7:0] are defined, for a total of 64 bits, mapping 8-bit parallel data of 8 channels, respectively.

Step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

In the above technical solution, step TS3 specifically includes: the existing 64B/66B coding IP core is adopted to code 64bit data and then serially output the data.

In the above technical solution, the unit for converting RS 164 to 8 specifically includes, referring to fig. 5:

step RS 101: and (3) decoding the IP core by adopting the existing 64B/66B, decoding the data coded by 64B/66B and then outputting the data in parallel.

Step RS 102: : the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

In the above technical solution, the step RS2 specifically includes: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'. In any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

In the above technical solution, the step RS3 specifically includes: and the existing 8B/10B coding unit IP core is adopted to code the 8bit data and then output the data.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. An apparatus for interconversion between 8B/10B coding and 64B/66B coding, comprising an 8-to-64 module and a 64-to-8 module, wherein the 8-to-64 module comprises:

the channels 1 to 8 are used for transmitting 8 groups of 10bit data;

the buffers 1 to 8 are correspondingly connected with the channels 1 to 8 one by one and used for buffering 8 groups of 10-bit data;

8B/10B decoding units 1 to 8B/10B decoding units 8 which are correspondingly connected with the buffers 1 to 8 one by one and used for converting 8 groups of 10-bit data to be transmitted into 8 groups of 8-bit data;

an 8-to-64 unit connected with the 8B/10B decoding units 1-8B/10B decoding unit 8 and used for decoding 8 channels and then synthesizing 8 groups of 8-bit data output in parallel into a group of 64-bit data;

the data delay processing unit is connected with the channels 1 to 8, the buffers 1 to 8 and the 8-to-64 unit, and is used for detecting data of 8 channels, triggering the buffers of 8 channels and the 8-to-64 unit to transmit data to a lower stage after a certain time, so as to solve the problem of data transmission delay;

the 64B/66B coding unit is connected with the 8-to-64 unit and is used for converting 64-bit data to be transmitted into 66-bit data;

the 66B data transmission unit is connected with the 64B/66B coding unit and is used for transmitting 66bit data;

the 64-to-8 module includes:

a 64B/66B decoding unit which is connected with the 66B data transmission unit and is used for converting 66bit data to be transmitted into 64bit data;

a 64-to-8 unit connected with the 64B/66B decoding unit and used for splitting a group of received decoded 64-bit data into 8 groups of 8-bit data and outputting the 8 groups of 8-bit data to 8 corresponding channels for detection;

the control code detection unit 1 to the control code detection unit 8 are connected with the 64-to-8 unit and used for detecting a control start code and an end code, and from the detection of the start code to the detection of the end code at the back, the middle data is considered as valid data, otherwise, the channel is considered not to be subjected to data transmission, and the received data is invalid data and discarded so as to solve the problems that the data delay of a sending end is too large or the data transmission is not carried out;

8B/10B coding units 1 to 8B/10B coding units 8 which are correspondingly connected with the control code detection unit 1 to the control code detection unit 8 one by one and used for converting 8 groups of 8bit data to be transmitted into 8 groups of 10bit data;

the channel 1 transmission unit to the channel 8 transmission unit are correspondingly connected with the 8B/10B coding units 1 to 8B/10B coding units 8 one by one and are used for transmitting 8 groups of 10bit data.

2. The apparatus according to claim 1, wherein the data delay processing unit comprises:

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, a data delay processing unit carries out independent data detection on the 8 channels, the zone bit D is set to be 0 when the data is detected, for example, the 2 nd path and the 5 th path have data, the D [7:0] is changed into 11101101, and the triggered zone bit D cannot be repeatedly triggered before the D recovers the initial state, namely the 11111111 state;

step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period; when the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

3. The apparatus of claim 1, wherein the 8B/10B coding to 64B coding conversion unit comprises the following steps:

step TS 201: each channel buffer outputs 10bit data, and the existing 8B/10B decoding IP core is adopted to decode 8B/10B coded data and then output in parallel;

step TS 202: defining 8 parallel input and parallel output registers T [7:0] with 8 bits, totally 64 bits, and respectively mapping 8-bit parallel data of 8 channels;

step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

4. The apparatus of claim 1, wherein the 64-to-8 unit comprises the following steps:

step RS 101: the existing 64B/66B decoding IP core is adopted, and the data coded by 64B/66B is decoded and then output in parallel;

step RS 102: the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

5. The apparatus of claim 1, wherein the control code detecting unit comprises: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'; in any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

6. A method for converting 8B/10B code and 64B/66B code is characterized in that the method is divided into an 8-to-64 module, namely 8B/10B code is converted into 64B/66B code; a 64-to-8 module, i.e., 64B/66B coding to 8B/10B coding, wherein:

the 8-to-64 module comprises the following steps:

step TS 1: 8 channel data detection is carried out, and a synchronous signal SYN control buffer is output and 8-to-64 units output data to the lower stage;

step TS 2: the 8-to-64 unit decodes the 8-path data and then merges the 8-path data into a group of 64-bit data;

step TS 3: carrying out 64B/66B coding transmission on 64bit data;

the 64-to-8 module comprises the following steps:

step RS 1: the data transmitted from the 8-to-64 module is decoded and split into 8 groups of 8-bit data and distributed to corresponding 8 channels;

step RS 2: each channel detects the control code of the received 8bit data;

step RS 3: each channel performs 8B/10B encoded transmission of 8bit data.

7. The method of claim 6, wherein the step TS1 specifically includes:

step TS 101: defining an 8-bit data detection zone bit D [7:0] which respectively corresponds to 8 channels, wherein the initial state is 11111111 and indicates no data, a data delay processing unit carries out independent data detection on the 8 channels, the zone bit D is set to be 0 when the data is detected, for example, the 2 nd path and the 5 th path have data, the D [7:0] is changed into 11101101, and the triggered zone bit D cannot be repeatedly triggered before the D recovers the initial state, namely the 11111111 state;

step TS 102: defining a synchronous signal SYN and a synchronous signal counter C, wherein the counting period is the length of an 8B/10B coded data clock period; when the RESET signal RESET comes, the flag bits D [7:0] restore to the initial state 11111111, C starts counting, the counting overflow (namely the clock cycle length of 8B/10B coded data) triggers a synchronous signal, and a synchronous clock pulse SYN is sent;

step TS 103: synchronous clock pulse SYN triggers 8 channel buffers and 8 to 64 units to transmit data to the next stage, the buffers output 10 bits of 8B/10B coded data in parallel, the 8 to 64 units output 64 bits of data in parallel, and SYN trigger C is cleared at the same time, and flag bits D [7:0] recover to an initial state 11111111111;

step TS 104: and for the zero clearing of the counter C, any bit flag bit D is 0, the zero clearing of the counter C is triggered, the channel is considered to have no data transmission when the data exceeds 7 8B/10B coding cycles at most, and the zero clearing of the clock pulse SYN and the RESET signal RESET is also triggered to ensure that the buffer and the 8-to-64 unit output data have no time delay.

8. The method of claim 6, wherein the unit 8 to 64 in the step TS2 specifically includes:

step TS 201: each channel buffer outputs 10bit data, and the existing 8B/10B decoding IP core is adopted to decode 8B/10B coded data and then output in parallel;

step TS 202: defining 8 parallel input and parallel output registers T [7:0] with 8 bits, totally 64 bits, and respectively mapping 8-bit parallel data of 8 channels;

step TS 203: SYN synchronous pulse acts on a register read-write enabling pin WE, when the pulse is low, namely 0, the value of the register is latched; when the pulse is high and remains high for a certain period, i.e. 1, the register outputs 64bit of data.

9. The method of claim 6, wherein the step RS1 of converting 64 cells to 8 specifically includes:

step RS 101: the existing 64B/66B decoding IP core is adopted, and the data coded by 64B/66B is decoded and then output in parallel;

step RS 102: the 64-to-8 unit defines 8-bit parallel input and parallel output registers R [7:0], totally 64 registers, 64-bit data decoded by 64B/66B can be stored in the registers R [7:0] in parallel, and the data are respectively output to corresponding channels in parallel.

10. The method of claim 6, wherein the step RS2 specifically includes: since K28.1, K28.5 and K28.7 are used as control characters of the K code in the 8B/10B coding, the code is called 'comma'; in any data combination, the comma only appears as a control character and does not appear in the data payload section, so the comma character is used to indicate the start and end flags of the frame, as shown in table 1:

TABLE 1

In the control code detection unit, a flag bit S is defined, the initial state is 1, when K28.1, K28.5 and K28.7, namely 00111100, 10111100 and 11111100, are detected, S is inverted, and when S is 1, the data received by a channel is regarded as invalid data and discarded; and when the S is 0, the data received by the channel is regarded as valid data and is transmitted.

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