CN2774018Y - 32-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system - Google Patents
32-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system Download PDFInfo
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- CN2774018Y CN2774018Y CN 200520039529 CN200520039529U CN2774018Y CN 2774018 Y CN2774018 Y CN 2774018Y CN 200520039529 CN200520039529 CN 200520039529 CN 200520039529 U CN200520039529 U CN 200520039529U CN 2774018 Y CN2774018 Y CN 2774018Y
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Abstract
The utility model relates to a 32-bit parallel frame synchronization scrambling coder/decoder in an optical synchronization digital transmission system. The utility model comprises 32 D triggers D0 to D31 and 32 exclusive-OR gates, wherein the 32 D triggers D0 to D31 and the 32 exclusive-OR gates are sequentially connected in series at intervals; besides, the output ends Q0 to Q31 of the 32 D triggers output a 32-bit scrambling code bit at one time in a clock phase, and simultaneously output signals to the input ends of the corresponding exclusive-OR gates. The 32-bit parallel frame synchronization scrambling coder/decoder has the advantages of simple logic representation, concise circuit actualization, compact derivation process, easy subsequent upgrade, low working frequency, strong system stability and convenient actualization of technology.
Description
Technical field
The utility model relates to a kind of adding/descrambler, and 32 parallel-by-bits that relate in particular in a kind of optical synchronization digital transmission system add/descrambler.
Background technology
Synchronous digital transmission system (being called for short SDH/SONET) generally is made up of transmission equipment and two kinds of basic equipments of network node, for synchronous optical transmission system, transmission equipment is exactly a cable system, network node is more complicated then, comprises termination equipment (TM), Cross Connect equipment (DXC), multiplexing equipment (ADM) etc.All be step-by-step (BIT) serial transfer signal in the synchronous digital transmission system, but do not transmit the clock signal of this node simultaneously that needed data of the receiving terminal of each node and clock all are to recover to come out from the data-signal that receives.Recover (CDR) principle according to data clock commonly used, clock recovery relies on the variation of data-signal along finishing, if there is long ' 1 ' or ' 0 ' sequence to occur in the data flow that receives, then the clock that recovers out by this principle is not really accurate, can cause losing of data message or mistake with such clock deal with data, therefore can to carry out Data Receiving and Clock Extraction exactly in order guaranteeing at receiving terminal, must to stop to have in the data flow transmitted appearance of long ' 1 ' or ' 0 ' sequence.International Telecommunication Association (CCITT) stipulates in the synchronous digital transmission system agreement for this reason: at transmitting terminal data are carried out scrambling, the data after the scrambling are transmitted by optical cable through electricity/light conversion back again; At receiving terminal the signal that transmits from optical cable is carried out light/electricity conversion, the data-signal after the conversion is carried out Clock Extraction, Data Receiving, descrambling and subsequent treatment again.CCITT agreement G.709 in also the regulation: (the most basic in the optical synchronization digital transmission system, most important module by signal is the STM-1 signal to STM-N, wire rate is 155.2Mbit/s, the STM-N signal is that wire rate is N*155.2Mbit/s with basic module signal STM-1 synchronous multiplexing, result after byte interleaves) 9xN byte of first row of section overhead do not carry out scrambler; Occur in case follow the highest order (MSB) of that byte of STM-N section overhead first last byte of row closely, scrambler should be set to " 1111111 " automatically; The generator polynomial of scrambler sequence is 1+X
6+ X
7, scrambler sequence length is 127.
In the book of " Optical synchronization digital transmission network " that the Wei Leping that the People's Press publishes writes (1998 December the 2nd edition) the 56th page provided a serial and added/function diagram of descrambler.See also Fig. 1,7 d type flip flops are used for displacement, d type flip flop R2, R3 ...., the input of R7 respectively with last d type flip flop R1, a R2 ...., the output of R6 links to each other, CLK is a STM-1 frame linearity clock signal, Reset is for deciding frame pulse, asserts signal; An XOR gate is in order to realize that mould 2 is carried out in the output of d type flip flop R7 and R6 adds (XOR), operation result feeds back to the input of d type flip flop R1, the output of d type flip flop R7 is scrambler sequence, and the linear speed data of it and STM-1 frame add/processing of descrambling.Can analyze from above-mentioned workflow and to draw: in the normal process stage, each scrambler all is to add operation result from the mould 2 before 7 timeticks, at each linear speed timeticks, R7 exports 1 scrambler, and R7 exports 32 scramblers successively in 32 linear speed timeticks.This scrambler circuit structure is simple, but owing to be operated under the wire rate, the operating frequency height causes complex manufacturing, the production cost height, even manufacturing has proposed high requirement even common process can't be realized to integrated circuit (IC) technology under 622M, 2.5G, 10G or higher frequency clock, as adopt special process then development cost can increase greatly, thereby this circuit must handle be replaced by parallelization in actual applications.
The utility model content
The purpose of this utility model is to provide 32 parallel-by-bit frame synchronization in a kind of optical synchronization digital transmission system that can be used under the high-frequency clock to add/descrambler.
The purpose of this utility model realizes by following technical method: 32 d type flip flop R0.。。R31 and 32 XOR gate interleave series connection according to the order of sequence, the output Q0 of 32 d type flip flops.。。Q31 once exports 32 scrambler position in a timeticks, output signal is to corresponding XOR gate input simultaneously.In 32 d type flip flops, 19 d type flip flop R1, R2, R3, R5, R7, R8, R9, R10, R13, R14, R15, R16, R17, R19, R20, R21, R22, R23, R24 for band reset terminal R, 13 is d type flip flop R0, R4, R6, R11, R12, R18, R25, R26, R27, R28, R29, R30, the R31 that has set end S in addition.
32 parallel-by-bit frame synchronization disclosed in the utility model add/descrambler, and its advantage shows: logical expressions are simple, and circuit is realized simple and clear, and derivation is simple and direct, and is easy to subsequent upgrade; Reduce operating frequency greatly, enhanced system stability is convenient to technology and is realized.
Description of drawings
Fig. 1 existingly is operated in that frame synchronization adds under the wire rate/circuit structure diagram of descrambler.
Fig. 2 be adopt the utility model 32 parallel-by-bits add/the SDH equipment of descrambler in the Data Stream Processing flow chart of receiving terminal.
Fig. 3 be adopt the utility model 32 parallel-by-bits add/the SDH equipment of descrambler in the Data Stream Processing flow chart of transmitting terminal.
Fig. 4 is that the utility model 32 parallel-by-bits add/circuit structure diagram of descrambler.
Embodiment
Scrambler sequence generator polynomial 1+X in conjunction with regulation in G.707
6+ X
7Be described in further detail.By the linear speed frame synchronization that Fig. 1 is provided add/analysis of decoder circuit structure can obtain: in the normal process stage, each scrambler all is to add computing from the mould 2 before 7 clocks; At scrambler of each linear speed clock output, in the clock cycle, export 8 scramblers successively at 8 linear speeds.Get any N clock, suppose that the Q end value of 7 d type flip flops among Fig. 1 is followed successively by d1
n, d2
n, d3
n, d4
n, d5
n, d6
n, d7
n, hold from N to N+8 clock cycle d type flip flop Q and the value of XOR it is as shown in the table successively with the value representation of N clock cycle:
Derivation is disturbed/is decoded in table 1. serial
| Week XOR Q1 Q2 Q3 Q4 Q5 Q6 Q7 phase N d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n N+1 d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n N+2 d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n N+3 d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n |
| N+4 d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n N+5 d1 n^d2 n d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n N+6 d6 n^d7 n^d1 n d1 n^d2 n d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n N+7 d5 n^d7 n d6 n^d7 n^d1 n d1 n^d2 n d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n N+8 d4 n^d6 n d5 n^d7 n d6 n^d7 n^d1 n d1 n^d2 n d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n |
If from last table XOR is regarded as d type flip flop R0, then the value of XOR is exactly d0 when N clock cycle
n, the value of XOR is exactly d0 when N+8 clock cycle
N+8, but when giving d type flip flop R0, R0 is made as d6 to the R7 initialize
n^d7
n, just realized the parallelization processing that scrambler sequence is generated so like this.In order to be illustrated more clearly in, suppose that scrambler sequence generation system clock frequency (clk_sys) is 1/8 of a linear speed clock (clk_line), and N the cycle of current P system clock cycle and N linear speed clock is synchronization, then N+8 the cycle of P+1 system clock cycle and linear speed clock is synchronization, and the value of 8 d type flip flops is as shown in the table:
Table 2.8 is disturbed/is decoded
| Q5 | d3 p^d4 p | d5 p |
| Q4 | d2 p^d3 p | d4 p |
| Q3 | d1 p^d2 n | d3 p |
| Q2 | d6 p^d7 p^d1 p | d2 p |
| Q1 | d5 p^d7 p | d1 p |
| Q0 | d4 p^d6 p | d0 p＝d6 p^d7 p |
The above-mentioned derivation method that the parallelization of serial scrambling code generator is realized is modal a kind of method, it is also not very complicated when the parallelization degree is relatively lower, but if realize 16,32,64,128 or just seem very complicated when higher, and the back of makeing mistakes is difficult for checking.
Great-jump-forward parallel disturbance code derivation method is a kind of easy derivation method.The value of 8 d type flip flops is followed successively by d0 when supposing any N clock cycle
n... d7
nThe value of 8 d type flip flops is followed successively by d0 during N+M clock cycle
N+m... d7
N+m(M be respectively 0,1,2,4,8,16.....).The value that this clock of every row place is represented constantly during N+M clock cycle in table 3 equates, the value representation of d type flip flop during only with different clock cycle, as: the value d0 of Q0 during N+4 clock cycle
N+4=d2
n^d3
n=d4
N+2^d5
N+2=d6
N+4^d7
N+4, use the value representation of N, N+2, a N+4 clock cycle trigger respectively.From following table 3 is that 1,2 o'clock method is identical with top method at M as can be seen, is that derivation when just omitting the 3rd, 5,6,7 clock cycle at 8 o'clock is with the simplification of implementation procedure at M.When N+4 clock cycle, be example with Q0, establish N '=N+2,
Then by d0
N+2=d4
n^d5
n
Get d0
N '+2=d4
N '^d5
N1=d4
N+2^d5
N+2,
Know by following table again: d4
N+2=d2
n
d5
n+2＝d3
n
And then obtain: d0
N+4=d4
N '^d5
N1=d4
N+2^d5
N+2=d2
n^d3
nIn like manner can obtain the value of other triggers.
Table 3. great-jump-forward parallel disturbance code derivation method
| Cycle Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 |
| N d0 n＝d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n |
| d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n d6 n |
| N+1 d0 n+1＝d6 n+1^d7 n+1 d1 n+1 d2 n+1 d3 n+1 d4 n+1 d5 n+1 d6 n+1 d7 n+1 |
| d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n d4 n d5 n |
| N+2 d5 n+1^d6 n+1 d6 n+1^d7 n+1 d1 n+1 d2 n+1 d3 n+1 d4 n+1 d5 n+1 d6 n+1 |
| d0 n+2＝d6 n+2^d7 n+2 d1 n+2 d2 n+2 d3 n+2 d4 n+2 d5 n+2 d6 n+2 d7 n+2 |
| N+4 d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n d6 n^d7 n d1 n d2 n d3 n |
| d4 n+2^d5 n+2 d5 n+2^d6 n+2 d6 n+2^d7 n+2 d1 n+2 d2 n+2 d3 n+2 d4 n+2 d5 n+2 |
| d0 n+4＝d6 n+4^d7 n+4 d1 n+4 d2 n+4 d3 n+4 d4 n+4 d5 n+4 d6 n+4 d7 n+4 |
| d4 n^d6 n d5 n^d7 n d6 n^d7 n^d1 n d1 n^d2 n d2 n^d3 n d3 n^d4 n d4 n^d5 n d5 n^d6 n |
| N+8 d2 n4^d3 n+4 d3 n+4^d4 n+4 d4 n+4^d5 n+4 d5 n+4^d6 n+4 d6 n+4^d7 n+4 d1 n+4 d2 n+4 d3 n+4 |
| d0 n+8＝d6 n+8^d7 n+8 d1 n+8 d2 n+8 d3 n+8 d4 n+8 d5 n+8 d6 n+8 d7 n+8 |
By top derivation principle, can derive 16 parallel-by-bits and disturb/decoder, the value of 16 triggers is followed successively by:
d0
n+16＝d2
n^d3
n^d4
n^d5
n
d1
n+16＝d3
n^d4
n^d5
n^d6
n
d2
n+16＝d4
n^d5
n^d6
n^d7
n
d3
n+16＝d1
n^d5
n^d6
n
d4
n+16＝d2
n^d6
n^d7
n
d5
n+16＝d1
n^d3
n
d6
n+16＝d2
n^d4
n
d7
n+16＝d3
n^d5
n
d8
n+16＝d4
n^d6
n
d9
n+16＝d5
n^d7
n
d10
n+16＝d1
n^d6
n^d7
n
d11
n+16＝d1
n^d2
n
d12
n+16＝d2
n^d3
n
d13
n+16＝d3
n^d4
n
d14
n+16＝d4
n^d5
n
d15
n+16＝d5
n^d6
n
According to top derivation principle, can disturb by 16 parallel-by-bits/decoder obtains 32 parallel-by-bit scramblers, and the input type of 32 d type flip flops is as follows:
d0
n+32＝d2
n^d3
n^d4
n^d6
n
d1
n+32＝d3
n^d4
n^d5
n^d7
n
d2
n+32＝d1
n^d4
n^d5
n^d6
n^d7
n
d3
n+32＝d1
n^d2
n^d5
n^d6
n
d4
n+32＝d2
n^d3
n^d6
n^d7
n
d5
n+32＝d1
n^d3
n^d4
n
d6
n+32＝d2
n^d4
n^d5
n
d7
n+32＝d3
n^d5
n^d6
n
d8
n+32＝d4
n^d6
n^d7
n
d9
n+32＝d1
n^d5
n
d10
n+32＝d2
n^d6
n
d11
n+32＝d3
n^d7
n
d12
n+32＝d1
n^d4
n^d7
n
d13
n+32＝d1
n^d2
n^d5
n^d7
n
d14
n+32＝d1
n^d2
n^d3
n^d6
n^d7
n
d15
n+32＝d1
n^d2
n^d3
n^d4
n
d16
n+32＝d2
n^d3
n^d4
n^d5
n
d17
n+32＝d3
n^d4
n^d5
n^d6
n
d18
n+32＝d4
n^d5
n^d6
n^d7
n
d19
n+32＝d1
n^d5
n^d6
n
d20
n+32＝d2
n^d6
n^d7
n
d21
n+32＝d1
n^d3
n
d22
n+32＝d2
n^d4
n
d23
n+32＝d3
n^d5
n
d24
n+32＝d4
n^d6
n
d25
n+32＝d5
n^d7
n
d26
n+32＝d1
n^d6
n^d7
n
d27
n+32＝d1
n^d2
n
d28
n+32＝d2
n^d3
n
d29
n+32＝d3
n^d4
n
d30
n+32＝d4
n^d5
n
d31
n+32＝d5
n^d6
n
Can obtain as shown in Figure 4 circuit structure from top 32 equatioies: 32 d type flip flop R0.。。R31 and 32 XOR gate interleave series connection according to the order of sequence, the output Q0 of 32 d type flip flops.。。Q31 once exports 32 scrambler position in a timeticks, an output signal is to corresponding XOR gate input simultaneously.32 output of d type flip flop in a clock cycle and the synchronous scrambler of linear speed are the same from the code stream of R7 output in 32 clock cycle.
32 parallel-by-bits shown in Figure 4 add/32 d type flip flops of the circuit structure of descrambler in, 19 d type flip flop R1, R2, R3, R5, R7, R8, R9, R10, R13, R14, R15, R16, R17, R19, R20, R21, R22, R23, R24 for band reset terminal R, 13 is d type flip flop R0, R4, R6, R11, R12, R18, R25, R26, R27, R28, R29, R30, the R31 that has set end S in addition.The output Q31...Q0 of 32 d type flip flops has constituted the scrambler sequence of 32 parallel-by-bits.The input signal of 32 d type flip flops is respectively:
1.D the input signal of trigger R0 is that the output signal of d type flip flop R2, R3, R4 and R6 is through the output signal after the XOR gate;
2.D the output signal of trigger R3, R4, R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R1;
3.D the output signal of trigger R1, R4, R5, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R2;
4.D the output signal of trigger R1, R2, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R3;
5.D the output signal of trigger R2, R3, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R4;
6.D the output signal of trigger R1, R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R5;
7.D the output signal of trigger R2, R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R6;
8.D the output signal of trigger R3, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R7;
9.D the output signal of trigger R4, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R8;
10.D the output signal of trigger R1 and R5 is through after the XOR gate, as the input signal of d type flip flop R9;
11.D the output signal of trigger R2 and R6 is through after the XOR gate, as the input signal of d type flip flop R10;
12.D the output signal of trigger R3 and R7 is through after the XOR gate, as the input signal of d type flip flop R11;
13.D the output signal of trigger R1, R4 and R7 is through after the XOR gate, as the input signal of d type flip flop R12;
14.D the output signal of trigger R1, R2, R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R13;
15.D the output signal of trigger R1, R2, R3, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R14;
16.D the output signal of trigger R1, R2, R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R15;
17.D the output signal of trigger R2, R3, R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R16;
18.D the output signal of trigger R3, R4, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R17;
19.D the output signal of trigger R4, R5, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R18;
20.D the output signal of trigger R1, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R19;
21.D the output signal of trigger R2, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R20;
22.D the output signal of trigger R1 and R3 is through after the XOR gate, as the input signal of d type flip flop R21;
23.D the output signal of trigger R2 and R4 is through after the XOR gate, as the input signal of d type flip flop R22;
24.D the output signal of trigger R3 and R5 is through after the XOR gate, as the input signal of d type flip flop R23;
25.D the output signal of trigger R4 and R6 is through after the XOR gate, as the input signal of d type flip flop R24;
26.D the output signal of trigger R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R25;
27.D the output signal of trigger R1, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R26;
28.D the output signal of trigger R1 and R2 is through after the XOR gate, as the input signal of d type flip flop R27;
29.D the output signal of trigger R2 and R3 is through after the XOR gate, as the input signal of d type flip flop R28;
30.D the output signal of trigger R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R29;
31.D the output signal of trigger R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R30;
32.D the output signal of trigger R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R31.
Fig. 2 and Fig. 3 adopt 32 parallel-by-bits to add/receive in the SDH equipment of descrambler and the Data Stream Processing flow chart of transmitting terminal.
In Fig. 2, linear speed data behind the light signal process clock data restorer (CDR) that receives form the system data of 32 bit formats again through serial/parallel conversion after searching the frame processing, producing frame head, adding with 32 parallel-by-bits under the effect of control signal subsequently/descrambler produces 32 parallel-by-bits under system clock scrambler sequence step-by-step once finishes 32 XOR (being descrambling code) computing, and the data behind descrambling are given the subsequent treatment module.Disturbing when beginning decoding adds/the d type flip flop R31 of descrambler synchronously to concurrent frame.。。R0 is provided with initial value and is " FE041851 ".Need first 32 of scrambler to carry out descrambling code computing by turn in this initial value " FE041851 " and the SDH/SONET frame, until last data of every frame.
In Fig. 3,32 system data adding with 32 parallel-by-bits under the effect of control signal/and descrambler produces 32 parallel-by-bits under system clock scrambler sequence step-by-step once finishes 32 XOR (being scrambled code) computing, data after the scrambling form bit stream after parallel/serial conversion, transmit on optical cable through electricity/light conversion back.
32 parallel-by-bits described in the utility model add/and descrambler can be implemented in system clock 78M (linear speed frequency 1/32) and generate scrambler sequence down and finish and add/descrambling operation in the 2.5G system data is handled; After FPGA (Field Programmable Gate Array, field-programmable gate array) realization, finish and satisfy protocol requirement, and logical expressions are simple, circuit is realized simple and clear, derivation is simple and direct, and is easy to subsequent upgrade; Because 32 parallel-by-bit processing reduce operating frequency greatly, enhanced system stability the more important thing is that being convenient to technology realizes, for cost is saved in the exploitation of chip.This mentality of designing can be used in the higher SDH/SONET frame data of linear speed are handled.
Claims (2)
1. 32 parallel-by-bit frame synchronization in the optical synchronization digital transmission system add/descrambler, it is characterized in that: comprise 32 d type flip flop R0.。。R31 and 32 XOR gate interleave series connection according to the order of sequence, and the output of these 32 d type flip flops has constituted the scrambler sequence of 32 parallel-by-bits; Wherein
1) input signal of d type flip flop R0 is that the output signal of d type flip flop R2, R3, R4 and R6 is through the output signal after the XOR gate;
2) output signal of d type flip flop R3, R4, R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R1;
3) output signal of d type flip flop R1, R4, R5, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R2;
4) output signal of d type flip flop R1, R2, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R3;
5) output signal of d type flip flop R2, R3, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R4;
6) output signal of d type flip flop R1, R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R5;
7) output signal of d type flip flop R2, R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R6;
8) output signal of d type flip flop R3, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R7;
9) output signal of d type flip flop R4, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R8;
10) output signal of d type flip flop R1 and R5 is through after the XOR gate, as the input signal of d type flip flop R9;
11) output signal of d type flip flop R2 and R6 is through after the XOR gate, as the input signal of d type flip flop R10;
12) output signal of d type flip flop R3 and R7 is through after the XOR gate, as the input signal of d type flip flop R11;
13) output signal of d type flip flop R1, R4 and R7 is through after the XOR gate, as the input signal of d type flip flop R12;
14) output signal of d type flip flop R1, R2, R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R13;
15) output signal of d type flip flop R1, R2, R3, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R14;
16) output signal of d type flip flop R1, R2, R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R15;
17) output signal of d type flip flop R2, R3, R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R16;
18) output signal of d type flip flop R3, R4, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R17;
19) output signal of d type flip flop R4, R5, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R18;
20) output signal of d type flip flop R1, R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R19;
21) output signal of d type flip flop R2, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R20;
22) output signal of d type flip flop R1 and R3 is through after the XOR gate, as the input signal of d type flip flop R21;
23) output signal of d type flip flop R2 and R4 is through after the XOR gate, as the input signal of d type flip flop R22;
24) output signal of d type flip flop R3 and R5 is through after the XOR gate, as the input signal of d type flip flop R23;
25) output signal of d type flip flop R4 and R6 is through after the XOR gate, as the input signal of d type flip flop R24;
26) output signal of d type flip flop R5 and R7 is through after the XOR gate, as the input signal of d type flip flop R25;
27) output signal of d type flip flop R1, R6 and R7 is through after the XOR gate, as the input signal of d type flip flop R26;
28) output signal of d type flip flop R1 and R2 is through after the XOR gate, as the input signal of d type flip flop R27;
29) output signal of d type flip flop R2 and R3 is through after the XOR gate, as the input signal of d type flip flop R28;
30) output signal of d type flip flop R3 and R4 is through after the XOR gate, as the input signal of d type flip flop R29;
31) output signal of d type flip flop R4 and R5 is through after the XOR gate, as the input signal of d type flip flop R30;
32) output signal of d type flip flop R5 and R6 is through after the XOR gate, as the input signal of d type flip flop R31.
2. 32 parallel-by-bit frame synchronization in the optical synchronization digital transmission system as claimed in claim 1 add/descrambler, it is characterized in that: in 32 d type flip flops, 19 d type flip flop R1, R2, R3, R5, R7, R8, R9, R10, R13, R14, R15, R16, R17, R19, R20, R21, R22, R23, R24 are with reset terminal R, and 13 d type flip flop R0, R4, R6, R11, R12, R18, R25, R26, R27, R28, R29, R30, R31 have set end S in addition.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108733617A (en) * | 2018-09-20 | 2018-11-02 | 电信科学技术第五研究所有限公司 | 64 parallel-by-bits of Fibre channel scramble the FPGA implementation method of descrambler |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108733617A (en) * | 2018-09-20 | 2018-11-02 | 电信科学技术第五研究所有限公司 | 64 parallel-by-bits of Fibre channel scramble the FPGA implementation method of descrambler |
| CN108733617B (en) * | 2018-09-20 | 2020-09-18 | 电信科学技术第五研究所有限公司 | FPGA implementation method of Fibre channel 64-bit parallel scrambling descrambler |
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