CN101610122A - Scrambling device that a kind of concurrent frame is synchronous and descrambling code device thereof - Google Patents
Scrambling device that a kind of concurrent frame is synchronous and descrambling code device thereof Download PDFInfo
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Abstract
The scrambling device that a kind of concurrent frame is synchronous, during this device comprised, control unit was used for that the pseudo random sequence of memory cell is carried out order and reads, and obtained in the pseudo random sequence and the corresponding content of parallel data; Memory cell is used to store the pseudo random sequence that sets in advance, and will import the XOR unit with the corresponding content of parallel data in the pseudo random sequence; The XOR unit is used for the parallel data with order input, successively with the pseudo random sequence of obtaining from memory cell make XOR and handle with the corresponding content of parallel data after, the data behind the output scrambler.The descrambling code device that a kind of concurrent frame is synchronous, in this device, the XOR unit is used for the data after will the scrambler of order input, successively with pseudo random sequence in scrambler after the corresponding content of data make XOR and handle after, the parallel data that obtains behind the output descrambling.Adopt scrambling device of the present invention and descrambling code device thereof, can realize scrambler and decoding respectively, reduced computation complexity.
Description
Technical field
The present invention relates to the frame synchronization scrambler technology in the communications protocol and the realization of descrambling code technology, relate in particular to synchronous scrambling device and the descrambling code device thereof of concurrent frame in a kind of synchronous digital transmission system (SDH)/synchronous optical network (SONET).
Background technology
In digital communication, receiving terminal utilizes 1/0 on the circuit to change, and the receive clock that carries out circuit by phase-locked loop recovers, and realizes bit synchronous, and transmits synchronizing information by flag of frame, thereby achieve frame is synchronous, and then byte of sync.Have only bit synchronous of having realized and frame synchronization, receiving terminal could correctly extract effective user data.The user profile that needs in the communication process to transmit is Protean, if user data contains long company 0 or connects 1 sequence, may make reception phase-locked loop losing lock and enter hold mode, clock quality descends, and can occur error code and even wrong problem when causing data to be recovered; If contain the information identical in the user data with flag of frame, may when initialization, make the received frame synchronous state machine enter error condition or vibration repeatedly, existence can't be carried out the problem of correct frame synchronization.
Scrambler is the normal technology of using in the digital communication, its objective is to make the data that transmit on digital circuit have the randomization characteristic, thereby can avoid the problems referred to above effectively.Randomized track data both can guarantee to have on the circuit 1/0 enough variation to come recovered clock, can avoid again comprising flag of frame in the user profile territory as far as possible.Scrambler realizes it all being that pseudo random sequence and the information that needs to transmit are carried out linear computing, and data behind the generation scrambler just utilize pseudo-random sequence generator to produce the randomized effect of outlet line data; Receiving terminal utilizes identical pseudo random sequence to carry out the phase inverse operation, just can recover legacy data, i.e. the process of descrambling.Scrambler can be realized with software or hardware.But because scrambler requires to carry out in real time, for the higher speed link, scrambler and descrambling generally adopt hardware circuit to realize.
Wherein, pseudo random sequence is made of pseudo noise code (M) sequence usually.So-called pseudo random sequence refers to: through a string number that arithmetical operation produced, this string number is a string number near random number sequence according to certain computing function.In scrambler/descrambling system, produce binary sequence by pseudo random sequence usually, carry out scrambler/descrambling and calculate.
The frame synchronization scrambler at transmitting terminal, will send data message and a M sequence XOR, transmission sequence 1 and 0 change at random behind the assurance scrambler.At receiving terminal, begin in same position, calculate on the contrary with same M sequence butt joint collection of letters breath code stream, recover the raw information code stream.The frame synchronization scrambler need transmit the state information of M sequence, and transmission field SDH system uses A1A2 as the frame synchronization pattern, is also referred to as and decides the frame byte, realizes the frame synchronization of receiving-transmitting sides.Simultaneously, this synchronizing signal also is used as the synchronizing information of motor synchronizing scrambler/descrambling circuit, at the frame head place, scrambler reconciliation circuit scrambler circuit all set is 1, return initial value and be complete 1 initial condition, and begin scrambler in identical position, and behind the 1st row section overhead scrambler, with guarantee transmitting terminal and receiving terminal both sides synchronously.
Because development of technology, message transmission rate is significantly improved, and adopt existing serial mode scrambler and scramble process need work on the linear velocity of transfer of data, the operating rate of the STM-64 of STM-16, the 10G of the 2.5G that generally adopts with present SDH transmission system even the STM-256 of 40G is an example, this just requires that the work in series speed of scrambler is the highest will to reach 40Gbp/s, and this is unusual difficulty on serial mode.Therefore, must utilize parallel disturbance code/descrambling circuit, reduce operating frequency, make scrambler and descrambling can realize with low-speed circuits with device by the expansion bit wide.Wherein, STM is the abbreviation of SynchronousTransport Module, is a kind of synchronous transfer mode, and STM-16, STM-64, STM-256 represent the synchronous transfer mode of different model respectively.
Adopt existing parallel disturbance code/descrambling circuit, at first be that the scrambler formula is showed with the serial circuit mode, then parallel bit stream is decomposed into the stack of each single-bit serial scrambler, utilizes matrix method or directly carry out the circuit structure that iterative computation obtains parallel disturbance code/descrambling.For different parallel input bit wides, need calculate the circuit structure that obtains corresponding parallel disturbance code/descrambling respectively.After parallel bit wide becomes greatly, as more than 256, need loaded down with trivial details iteration to derive and very long combinational logic link, this causes the delay of circuit very big, might not reach the processing frequency of the requirement of parallel signal, is not suitable for the above high speed circuit of 40G.
Wherein, parallel bit stream is a kind of parallel data, and parallel data is different from serial data, and so-called serial data refers to: according to the data of single-bit processing; So-called parallel data refers to: according to the data of many bit process.What transmit on the communication line all is serial data, but when chip is handled, all is that n continuous bit of intercepting handled in serial data, that is to say, serial data is become the parallel data of n position.Existing string also/also string conversion just is meant the implication here.
In sum, adopt the shortcoming that existing parallel disturbance code/descrambling circuit exists to be: on the one hand, for different parallel data input bit wides, need design the circuit structure of corresponding parallel disturbance code/descrambling respectively, pervasive scope is little, does not possess versatility, thereby is unfavorable for promoting the use of; On the other hand, the M sequence that does not pre-set need be done instant computing with parallel data, the input bit wide of parallel data is big more, it is just complicated more to make the iteration that instant computing adopts, the computation complexity of the instant computing of this iteration is very high, cause arithmetic speed slow, thereby cause the operating efficiency of parallel disturbance code/descrambling circuit and handle frequency low.
Summary of the invention
In view of this, main purpose of the present invention is to provide synchronous scrambling device of a kind of concurrent frame and descrambling code device thereof, can realize scrambler and decoding respectively, not only is adapted to the parallel data of various input bit wides, possesses versatility, utilizes and promotes; And reduced computation complexity, improve the operating efficiency of this scrambling device and descrambling code device thereof and handled frequency.
For achieving the above object, technical scheme of the present invention is achieved in that
The scrambling device that a kind of concurrent frame is synchronous, this device comprises: memory cell, control unit, XOR unit; Wherein,
Control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtains in the pseudo random sequence and the corresponding content of parallel data;
Memory cell is used to store the described pseudo random sequence that sets in advance, and will import the XOR unit with the corresponding content of parallel data in the described pseudo random sequence;
The XOR unit is used for the described parallel data with order input, successively with the described pseudo random sequence of obtaining from memory cell make XOR and handle with the corresponding content of parallel data after, the data behind the output scrambler.
Wherein, be under the state of Q in the bit wide of described parallel data, be specially with the corresponding content of parallel data in the described pseudo random sequence: in the pseudo random sequence with the corresponding Q of parallel data position content;
The length of described pseudo random sequence is T * Q, is made of the pseudo noise code M sequence of Q position; Wherein, T is the repetitive cycling cycle of described M sequence.
Wherein, described control unit is further used for circulating according to described T under the control of frame synchronizing signal, obtains in the described pseudo random sequence M sequence with the corresponding described Q of parallel data position successively.
Wherein, described XOR unit is further used for the described parallel data with the order input, does the XOR processing with the M sequence of the corresponding described Q of parallel data position successively with in the described pseudo random sequence, until the traversal of finishing the M sequence of T * Q position.
Wherein, described control unit is specially address generator; Described memory cell is specially the M sequencer.
The descrambling code device that a kind of concurrent frame is synchronous, this device comprises: memory cell, control unit, XOR unit; Wherein,
Control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtain in the pseudo random sequence with scrambler after the corresponding content of data;
Memory cell is used to store the described pseudo random sequence that sets in advance, with in the described pseudo random sequence with scrambler after the corresponding content of data input XOR unit;
The XOR unit is used for the data after will the described scrambler of order input, successively with the described pseudo random sequence of obtaining from memory cell with scrambler after the corresponding content of data make XOR and handle after, the parallel data that obtains behind the output descrambling.
Wherein, be under the state of Q in the bit wide of the data behind the described scrambler, in the described pseudo random sequence with scrambler after the corresponding content of data be specially: in the pseudo random sequence with scrambler after the corresponding Q of data position content;
The length of described pseudo random sequence is T * Q, is made of the M sequence of Q position; Wherein, T is the repetitive cycling cycle of described M sequence.
Wherein, described control unit is further used for circulating according to described T under the control of frame synchronizing signal, obtain successively in the described pseudo random sequence with scrambler after the M sequence of the corresponding described Q of data position.
Wherein, described XOR unit is further used for the data after will the described scrambler of order input, successively with described pseudo random sequence in scrambler after the M sequence of the corresponding described Q of data position make XOR and handle, until the traversal of finishing the M sequence of T * Q position.
Wherein, described control unit is specially address generator; Described memory cell is specially the M sequencer.
The present invention has realized scrambling device and the descrambling code device thereof that concurrent frame is synchronous, can realize scrambler and decoding respectively, with regard to scrambling device, control unit during this device comprises is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtains in the pseudo random sequence and the corresponding content of parallel data; Memory cell is used to store the pseudo random sequence that sets in advance, and will import the XOR unit with the corresponding content of parallel data in the pseudo random sequence; The XOR unit is used for the parallel data with order input, successively with the pseudo random sequence of obtaining from memory cell make XOR and handle with the corresponding content of parallel data after, the data behind the output scrambler.With regard to the descrambling code device corresponding with it, the control unit in the descrambling code device carries out order to the pseudo random sequence in the memory cell and reads, and obtain in the pseudo random sequence with scrambler after the corresponding content of data; The XOR unit is used for the data after will the scrambler of order input, successively with the pseudo random sequence of obtaining from memory cell with scrambler after the corresponding content of data make XOR and handle after, the parallel data that obtains behind the output descrambling.
Adopt the present invention, can realize scrambler and decoding that concurrent frame is synchronous respectively, realized the synchronous scrambler/descrambling of concurrent frame of any bit wide, not only be adapted to the parallel data of various bit wides, possess versatility, utilize and promote; And reduced computation complexity, improve the operating efficiency of this scrambling device and descrambling code device thereof and handled frequency.Compare with existing parallel disturbance code/descrambling circuit, its combinational logic is few, realizes that simply processing delay is few, is more suitable for big bit wide and parallel disturbance code and descrambling code at a high speed.
Description of drawings
Fig. 1 is the composition structural representation of the synchronous scrambling device/descrambling code device of concurrent frame of the present invention;
Fig. 2 is the composition structural representation of an embodiment of the synchronous scrambling device/descrambling code device of concurrent frame of the present invention;
Fig. 3 is the composition structural representation at an embodiment of the 256 parallel-by-bits scrambling device/descrambling code device of STM-256 signal.
Embodiment
Basic thought of the present invention is: when using as scrambling device, after the parallel data input scrambling device, read from memory cell in the pseudo random sequence and the corresponding content of parallel data by control unit; Phase XOR in the XOR unit then obtains the data behind the scrambler.And when using as descrambler, input be data behind the scrambler, control unit from memory cell, read out in the pseudo random sequence with scrambler after the corresponding content of data, in the XOR unit, do XOR with the data behind the scrambler and handle, obtain the parallel data code stream behind the descrambling.It is to be noted, from memory cell, read when using in the pseudo random sequence and the corresponding content of parallel data as scrambling device, from memory cell, read out when using in the pseudo random sequence as descrambler with scrambler after the corresponding content of data, this two parts content is identical.
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme.
When the present invention uses as scrambling device or descrambling code device, all form by XOR unit, control unit, these three functional units of memory cell.No matter be when using as scrambling device or descrambling code device, the pseudo random sequence that sets in advance of storing in memory cell all is the same; Under the control of control unit, the data that read from the memory cell order are identical, that is to say, when doing the XOR processing in the XOR unit, a part of content in the used pseudo random sequence is identical.Difference is, when using as scrambling device, input XOR unit be parallel data, through XOR handle that the back exports be scrambler after data; And when using as the descrambling code device, input XOR unit be parallel data, through XOR handle that the back exports be descrambling code after parallel data code stream.Like this, descrambling code device of the present invention could be made descrambling code to the data behind the scrambler of handling output through scrambling device and handle, thereby, after descrambling code is handled, recover the parallel data code stream of original input scrambling device.Because when the present invention uses as scrambling device or descrambling code device, all form by XOR unit, control unit, these three functional units of memory cell, therefore, easy in order to describe, all use the system architecture of Fig. 1 indication device, and set forth the specific implementation of each unit when using respectively as different device.
As shown in Figure 1, the scrambling device that a kind of concurrent frame is synchronous, this device comprises: memory cell, control unit, XOR unit.Wherein, control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtains in the pseudo random sequence and the corresponding content of parallel data.Memory cell is used to store the pseudo random sequence that sets in advance, and will import the XOR unit with the corresponding content of parallel data in the pseudo random sequence.The XOR unit is used for the parallel data with order input, successively with the pseudo random sequence of obtaining from memory cell make XOR and handle with the corresponding content of parallel data after, the data behind the output scrambler.
Here, be under the state of Q in the bit wide of parallel data, be specially with the corresponding content of parallel data in the pseudo random sequence: in the pseudo random sequence with the corresponding Q of parallel data position content.The length of pseudo random sequence is T * Q, is made of the M sequence of Q position; Wherein, T is the repetitive cycling cycle of M sequence.With regard to Q, the value of Q is relevant with the speed of serial data and chip processing speed, such as being 256 bits; With regard to T, the value of T is by the decision of the characteristic equation of M sequence, when the high-order of the characteristic equation of M sequence is r, and T=2
r-1.It is to be noted: below the value of the Q that relates to and T also be the implication here, below do not give unnecessary details.
As seen, because the present invention is kept in advance good pseudo random sequence in the memory cell in advance, directly take so that carry out when XOR is handled; And the pseudo random sequence of prior art is not calculated good in advance and storage, takes by instant computing.Therefore, adopt the present invention can reduce computation complexity, thereby it is simple that device of the present invention is handled, the treatment effeciency height goes for bigger bit wide of parallel data and device more at a high speed; And not limiting the bit wide of parallel data and the characteristic equation of M sequence, versatility is better, can be adapted to various communications protocols.
Above-mentioned control unit is further used for circulating according to T under the control of frame synchronizing signal, obtains in the pseudo random sequence M sequence with corresponding this Q position of parallel data successively.
Above-mentioned XOR unit is further used for the parallel data with the order input, does the XOR processing with the M sequence of corresponding this Q position of parallel data successively with in the pseudo random sequence, until the traversal of finishing the M sequence of T * Q position, and the data behind the output scrambler.
Here, control unit is specially address generator; Memory cell is specially the M sequencer.
The descrambling code device that a kind of concurrent frame is synchronous, this device comprises: memory cell, control unit, XOR unit.Wherein, control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtain in the pseudo random sequence with scrambler after the corresponding content of data.Memory cell is used to store the pseudo random sequence that sets in advance, with in the pseudo random sequence with scrambler after the corresponding content of data input XOR unit.The XOR unit is used for the data after will the scrambler of order input, successively with the pseudo random sequence of obtaining from memory cell with scrambler after the corresponding content of data make XOR and handle after, the parallel data that obtains behind the output descrambling.
Here it is to be noted, from memory cell, read when using in the pseudo random sequence and the corresponding content of parallel data as scrambling device, from memory cell, read out when using in the pseudo random sequence as descrambler with scrambler after the corresponding content of data, this two parts content is identical, like this, descrambling code device of the present invention, could make descrambling code to the data behind the scrambler of handling output through scrambling device handles, thereby, after descrambling code is handled, recover the parallel data code stream of original input scrambling device.
Here, be under the state of Q in the bit wide of the data behind the scrambler, in the pseudo random sequence with scrambler after the corresponding content of data be specially: in the pseudo random sequence with scrambler after the corresponding Q of data position content.The length of pseudo random sequence is T * Q, is made of the M sequence of Q position; Wherein, T is the repetitive cycling cycle of M sequence.
Here, control unit is further used for circulating according to T under the control of frame synchronizing signal, obtain successively in the pseudo random sequence with scrambler after the M sequence of corresponding this Q position of data.
Here, the XOR unit is further used for the data after will the scrambler of order input, successively with pseudo random sequence in scrambler after the M sequence of the corresponding described Q of data position make XOR and handle, until the traversal of finishing the M sequence of T * Q position, the parallel data that obtains behind the output descrambling.
Here, control unit is specially address generator; Memory cell is specially the M sequencer.
More than, address generator that the present invention relates to when using as scrambling device or descrambling code device and M sequencer are as shown in Figure 2.
In sum, the present invention includes following content:
The present invention adopts the principle of technical scheme to be: the M sequence is a kind of periodic sequence, and for the scrambler circuit on the highest r rank, the repetition period is 2
r-1, promptly this moment above-mentioned T=2
r-1.Scrambler/descrambling with the SDH/SONET system is an example, and the proper polynomial of scrambler is x
7+ x
6+ 1, just used 2
7-1 is the pseudo random sequence of 127 bit periods.Just according to the order of data bit transmission, each data bit and M sequencer output bit carry out XOR to the essence of frame synchronization scrambler, transmit on communication line then.Descrambling circuit also is according to corresponding order, the data bit behind the scrambler is exported bit with identical M sequencer carry out XOR, to obtain original data bit flow.When each frame synchronization point, M sequence linear shift register will be given initial value, generally all be to give complete 1 value.
If the bit wide of the parallel data D of input is Q, the repetition period of M sequence is T, and each complete M sequence is M[0, T-1].Then must exist a R sequence, its length is T * Q, and content is that Q M sequence merging forms, just:
R[0，TQ-1]＝{M[0，T-1]
0，M[0，T-1]
1，M[0，T-1]
2，M[0，T-1]
3.....M[0，T-1]
Q-1}
For the parallel disturbance code of Q bit wide, the Q bit data bit of order input successively with the R sequence in corresponding Q position content carry out XOR and handle, D just
0^R[0, Q-1], D
1^R[Q, 2Q-1], D
2^R[2Q, 3Q-1] ..., D
T-1^R[(T-1) Q, TQ-1], all the elements all travel through one time in the R sequence, have just finished a big scrambler cycle.It is exactly to repeat above process that ensuing scrambler is handled, until the scrambler work of finishing present frame.Descrambling process and scrambler process are just the same in processing mode.
The synchronous scrambling device of the concurrent frame/descrambling code device of the present invention's design is based on the realization of above-mentioned theory principle, as shown in Figure 1, by control unit, memory cell, three unit, XOR unit are formed, as shown in Figure 1.When needing the frame synchronization scrambler, after the parallel data input scrambling device, take out a part of content of corresponding M sequence by control unit from memory cell, phase XOR in the XOR unit then obtains the data behind the scrambler.And when using as the descrambling code device, input is the data behind the scrambler, and control unit takes out same a part of M sequence and the data behind the scrambler and does XOR handle in the XOR unit from memory cell, obtains the parallel data code stream behind the descrambling.The synchronous scrambling device of concurrent frame of the present invention/descrambling code device does not limit the bit wide of input parallel data and the characteristic equation of M sequence, for higher bit wide and longer scrambler sequence, just increases the capacity and the complexity of control unit and memory cell.Adopt the present invention, can be applicable to that SDH/SONET transmission system and other adopt the communication system of frame synchronization scrambler scheme than realizing scrambler and descrambling function under the low rate.
Control unit among Fig. 1 can be specially address generator, and memory cell can be specially the M sequencer, and as shown in Figure 2, establish parallel data bit wide q this moment, and the high-order of the characteristic equation of M is r.The effective address line of address generator output is the r root, and the address realm of control is 1-2
r-1.Under the guide of frame synchronizing signal, the address of control output is 1 address, and then according to the beat of input clock, cyclic address change in the time of each active data is until location 2 superlatively
7-1, get back to 1 address then again, successively circulation.After finishing the scrambler/descrambling of a frame, wait for the frame synchronizing signal of a new frame, again the address is pointed to initial address 1, begin the address accumulation process of a new frame.The M sequencer generally realizes that by RAM or ROM the valid data space is q * 2
r-1 bit.The M sequence begins to M2 from the M1 bit according to the bit-order that pseudo noise code produces
r-1 bit is filled successively, has filled q individual 2 altogether
rThe M sequence of-1 length.The scope of each address correspondence of controller output is the q bit, 2
rThe size of-1 address space correspondence just in time is 2
r-1 * q, corresponding complete q individual 2
rThe M sequence of-1 length.Address according to address generator output, the M sequencer takes out effective M sequence content from this index address, carry out XOR with the data after the parallel data/scrambling of input and handle, just obtained the parallel data that recovers behind the data/descrambling after the effective scrambling.
Embodiment:
Below in conjunction with Fig. 3, only disturbing device with the SDH STM-256 signal parallel frame synchronization of 256 bit bit wides is that design example is described, but all schemes all are applicable to the synchronous scrambling device of the concurrent frame of other bit wide.
System works realizes scrambling with 256 parallel-by-bit width under the 155.52MHz clock frequency.The M sequencer is made of ROM, because the proper polynomial of SDH scrambler is x
7+ x
6+ 1, used 2
7-1 is the pseudo random sequence of 127 bit periods, so its capacity is: (2
7-1 * 256) bit, 2
7-1 is the degree of depth of memory space; 256 is the width of memory space, and there is the content of 256 127 pseudo random sequences the inside.It is to be noted: M represents whole 127 pseudo random sequences among Fig. 3, and m1, m2... represent the content of the corresponding bit position of pseudo random sequence.
Among Fig. 3, deserializer is finished clock recovery, synchronization acquistion, serial/parallel conversion, and output word is wide to be 256 parallel data, synchronised clock (CLK).Deframer is decided the frame byte by the A1A2 in the detection signal, produces the frame synchronization index signal and the 256 later parallel-by-bit data of frame synchronization of first 256 word alignment in the STM-256 frame structure.Address generator calculates the rank addresses in the SDH frame structure, and draws the ROM table address of scrambler according to rank addresses.When frame synchronization indicates now, row address and column address are pointed to the initial position of frame structure, column address adds 1 one by one under the driving of indication synchronously, when column address 〉=270 * 256/8-1=8639, column address is pointed to the 1st row of frame structure, simultaneously row address adds 1, and when row address 〉=8 and column address 〉=8639, row address and column address are pointed to the original position of frame structure once more.On the other hand, frame synchronization indicates now, the ROM table address points to address 0, because 9 * N byte of the 1st row of STM-N section overhead is scrambler not, when row address is 0 and column address 〉=9 * 256/8-1=287, the ROM table address begins periodically to travel through from address AD DR0x00 to ADDR0x7E whole ROM, exporting M sequence content that appropriate address ROM deposits and 256 parallel-by-bit data simultaneously carries out XOR and obtains through the STM-256 Frame behind the scrambler, up to row address 〉=8 and column address 〉=8639, the look-up table address is pointed to address 0 again.So just finished the scrambler process of entire frame, descrambling code process and above-mentioned scrambler are similar.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (10)
1, the synchronous scrambling device of a kind of concurrent frame is characterized in that, this device comprises: memory cell, control unit, XOR unit; Wherein,
Control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtains in the pseudo random sequence and the corresponding content of parallel data;
Memory cell is used to store the described pseudo random sequence that sets in advance, and will import the XOR unit with the corresponding content of parallel data in the described pseudo random sequence;
The XOR unit is used for the described parallel data with order input, successively with the described pseudo random sequence of obtaining from memory cell make XOR and handle with the corresponding content of parallel data after, the data behind the output scrambler.
2, scrambling device according to claim 1 is characterized in that, is under the state of Q in the bit wide of described parallel data, is specially with the corresponding content of parallel data in the described pseudo random sequence: in the pseudo random sequence with the corresponding Q of parallel data position content;
The length of described pseudo random sequence is T * Q, is made of the pseudo noise code M sequence of Q position; Wherein, T is the repetitive cycling cycle of described M sequence.
3, scrambling device according to claim 2, it is characterized in that described control unit is further used under the control of frame synchronizing signal, circulate according to described T, obtain in the described pseudo random sequence M sequence successively with the corresponding described Q of parallel data position.
4, scrambling device according to claim 2, it is characterized in that, described XOR unit, be further used for described parallel data with the order input, do the XOR processing with the M sequence of the corresponding described Q of parallel data position successively with in the described pseudo random sequence, until the traversal of finishing the M sequence of T * Q position.
5, according to claim 3 or 4 described scrambling device, it is characterized in that described control unit is specially address generator; Described memory cell is specially the M sequencer.
6, the synchronous descrambling code device of a kind of concurrent frame is characterized in that this device comprises: memory cell, control unit, XOR unit; Wherein,
Control unit is used for that the pseudo random sequence of memory cell is carried out order and reads, and obtain in the pseudo random sequence with scrambler after the corresponding content of data;
Memory cell is used to store the described pseudo random sequence that sets in advance, with in the described pseudo random sequence with scrambler after the corresponding content of data input XOR unit;
The XOR unit is used for the data after will the described scrambler of order input, successively with the described pseudo random sequence of obtaining from memory cell with scrambler after the corresponding content of data make XOR and handle after, the parallel data that obtains behind the output descrambling.
7, descrambling code device according to claim 6, it is characterized in that, bit wide in the data behind the described scrambler is under the state of Q, in the described pseudo random sequence with scrambler after the corresponding content of data be specially: in the pseudo random sequence with scrambler after the corresponding Q of data position content;
The length of described pseudo random sequence is T * Q, is made of the M sequence of Q position; Wherein, T is the repetitive cycling cycle of described M sequence.
8, descrambling code device according to claim 7, it is characterized in that described control unit is further used under the control of frame synchronizing signal, circulate according to described T, obtain successively in the described pseudo random sequence with scrambler after the M sequence of the corresponding described Q of data position.
9, descrambling code device according to claim 7, it is characterized in that, described XOR unit, be further used for the data behind the described scrambler of order input, successively with described pseudo random sequence in scrambler after the M sequence of the corresponding described Q of data position make XOR and handle, until the traversal of finishing the M sequence of T * Q position.
10, according to Claim 8 or 9 described descrambling code devices, it is characterized in that described control unit is specially address generator; Described memory cell is specially the M sequencer.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910088502 CN101610122B (en) | 2009-07-03 | 2009-07-03 | Parallel frame synchronous scrambling device and descrambling device thereof |
| RU2012101263/07A RU2505932C2 (en) | 2009-07-03 | 2010-06-10 | Scrambling and descrambling device for parallel frame synchronisation |
| PCT/CN2010/073769 WO2011000257A1 (en) | 2009-07-03 | 2010-06-10 | Parallel frame synchronization scrambling apparatus and de-scrambling apparatus thereof |
| BR112012000016A BR112012000016A2 (en) | 2009-07-03 | 2010-06-10 | parallel frame synchronization scrambling apparatus and scrambling apparatus thereof. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910088502 CN101610122B (en) | 2009-07-03 | 2009-07-03 | Parallel frame synchronous scrambling device and descrambling device thereof |
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| Publication Number | Publication Date |
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| CN101610122A true CN101610122A (en) | 2009-12-23 |
| CN101610122B CN101610122B (en) | 2013-03-20 |
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| CN 200910088502 Active CN101610122B (en) | 2009-07-03 | 2009-07-03 | Parallel frame synchronous scrambling device and descrambling device thereof |
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| Country | Link |
|---|---|
| CN (1) | CN101610122B (en) |
| BR (1) | BR112012000016A2 (en) |
| RU (1) | RU2505932C2 (en) |
| WO (1) | WO2011000257A1 (en) |
Cited By (12)
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| WO2011000257A1 (en) * | 2009-07-03 | 2011-01-06 | 中兴通讯股份有限公司 | Parallel frame synchronization scrambling apparatus and de-scrambling apparatus thereof |
| CN102064912A (en) * | 2010-10-20 | 2011-05-18 | 武汉微创光电股份有限公司 | Line coding and decoding method for optical fibre transmission of high-speed digital signal |
| WO2015180545A1 (en) * | 2014-05-30 | 2015-12-03 | 华为技术有限公司 | Scrambling apparatus and scrambling configuration method |
| CN105183428A (en) * | 2015-08-12 | 2015-12-23 | 中国电子科技集团公司第四十一研究所 | Pseudo-random signal generation method |
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| SE9704497L (en) * | 1997-12-03 | 1999-06-04 | Telia Ab | Improvements to, or with respect to, data scramblers |
| US7106859B2 (en) * | 2001-10-16 | 2006-09-12 | Intel Corporation | Parallel data scrambler |
| KR100416478B1 (en) * | 2001-12-29 | 2004-01-31 | 디지피아(주) | Parallel scrambler for dvb-t |
| US7061966B2 (en) * | 2003-02-27 | 2006-06-13 | Motorola, Inc. | Frame synchronization and scrambling code indentification in wireless communications systems and methods therefor |
| CN101018097B (en) * | 2006-02-07 | 2011-09-21 | 华为技术有限公司 | Disturbance code generation device |
| CN101098299B (en) * | 2006-06-27 | 2010-08-18 | 中兴通讯股份有限公司 | Parallel method and apparatus for bit scrambling |
| CN101394246B (en) * | 2008-11-12 | 2011-05-04 | 烽火通信科技股份有限公司 | General configurable parallel disturbance code implementation device and method |
| CN101610122B (en) * | 2009-07-03 | 2013-03-20 | 中兴通讯股份有限公司 | Parallel frame synchronous scrambling device and descrambling device thereof |
-
2009
- 2009-07-03 CN CN 200910088502 patent/CN101610122B/en active Active
-
2010
- 2010-06-10 RU RU2012101263/07A patent/RU2505932C2/en active
- 2010-06-10 BR BR112012000016A patent/BR112012000016A2/en not_active Application Discontinuation
- 2010-06-10 WO PCT/CN2010/073769 patent/WO2011000257A1/en active Application Filing
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| CN115208722B (en) * | 2022-07-28 | 2024-03-01 | 电子科技大学 | Novel frame synchronous scrambling code descrambling method |
Also Published As
| Publication number | Publication date |
|---|---|
| RU2012101263A (en) | 2013-08-10 |
| CN101610122B (en) | 2013-03-20 |
| RU2505932C2 (en) | 2014-01-27 |
| WO2011000257A1 (en) | 2011-01-06 |
| BR112012000016A2 (en) | 2017-07-18 |
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