CN101098299B - Parallel method and apparatus for bit scrambling - Google Patents

Abstract

The invention discloses a parallel method of bit scrambling and a relative device, which comprises a bit scrambling sequence generator and a scrambling device, wherein the bit scrambling sequence generator outputs a plurality of scrambling code bit components synchronously, the scrambling device outputs a plurality of bit components with scrambled relative data block and the scrambling code bit components synchronously . The invention executes bit scrambling on 16 bits in one clock period, while the bit scrambling speed is improved 16 times and the bit scrambling process in whole HS-DSCH channel code is shortened.

Description

A kind of parallel method of bit scramble and device

Technical field

The present invention relates to a kind of broadband CDMA system (WCDMA) wireless communication system, specifically, what the present invention relates to is a kind of parallel method and device that is used for high-speed downlink packet access channel execution bit scramble.

Background technology

In mobile communication, can data fast, transmit at application expeditiously, becomes the key element of 3G industry development.HSDPA (high speed downlink packet inserts High Speed DownlinkPacket Access) is exactly the core technology of releasing for addressing this problem.The HSDPA technology reducing throughput and the peak-data rates that has increased transfer of data on the basis that postpones, for the multi-user provides the high-speed down data service, is particularly suitable for the business of a large amount of download messages such as mobile multimedia, Internet by AMC and H-ARQ technology.Studies show that the HSDPA technology can make the air interface downstream rate reach more than the 10Mbps, to adopting the HSDPA system of multiple-input, multiple-output (MIMO) technology, data rate can reach 20Mbps, is a very promising also very commercioganic new technology.

The principle of AMC technology is the pattern that changes modulation, coded system, code block size according to the variation of channel situation.When using the system of AMC technology, the user who sits pretty, for example can use high order modulation and high code check (for example 16QAM, bigger block size) near the user of base station, and be in the user of unfavorable position, for example away from its order of modulation of user of base station and code check then smaller (for example QPSK, less block size).The AMC technology mainly can improve the user's that sits pretty speed, thereby improves the average throughput of sub-district.

HARQ is a kind of link adaptation techniques, and ARQ is an automatic repeat request, and HARQ is with forward error correction coding (FEC) and the automatic technology that combines of repeat requests (ARQ).Forward error correction coding (FEC) has improved the reliability of transmission, but when channel situation is better, has reduced throughput.ARQ can not obtain desirable throughput under the error rate is not very high situation, but can introduce time delay, considers FEC and ARQ combined just to have formed hybrid ARQ.The check bit that in each packet that sends, contains error correction and error detection.If receive and to make mistakes bit number within error correcting capability in the bag, then wrongly corrected voluntarily, when mistake is serious, when having exceeded the error correcting capability of FEC, then allow transmitting terminal retransmit.

Be the cataloged procedure of the high speed descending sharing channel (HS-DSCH) of prior art as shown in Figure 1.As shown in Figure 1, cataloged procedure comprises that cyclic redundancy detects (CRC adder 001), bit scramble device 002, code block dispenser 003, Turbo encoder 004, HARQ process 005, physical channel segmentation 006, interleaver 007, planisphere reorganization 008.

With reference to figure 1, high level sends data block to CRC adder 001, affix CRC sign indicating number in CRC adder 001, and the data block that will add behind the CRC sign indicating number offers bit scramble device 002, and this bit scramble device 002 uses predetermined initial value to come the data block of having added CRC is carried out scrambling on the basis of each bit.Moving partnership (3GPP) with regard to the third generation below is described the bit scramble process.

From the bit definitions of CRC adder 001 output is b _{Im, 1}, b _{Im, 2}, b _{Im, 3}..., b _{Im, B}, B is the bit number that is input to bit scramble device 002, the output after bit scramble is complete is defined as d _{Im, 1}, d _{Im, 2}, d _{Im, 3}..., d _{Im, B}The procedural representation of bit scramble is as follows:

d _im，k＝(b _im，k+y _k)mod2 k＝1，2，...，B

3GPP stipulates y _kCan obtain by following process:

y′ _γ＝0 -15＜γ＜1

y′ _γ＝1 γ＝1

${y^{\&prime;}}_{\mathrm{\&gamma;}}=(\underset{x=1}{\overset{16}{\mathrm{\&Sigma;}}}{g}_x\&CenterDot;{y^{\&prime;}}_{\mathrm{\&gamma;}-x})\mathrm{<figure-callout\; id="2"\; label="mod"\; filenames="H06190451420060704E000012.png"\; state="\{\{state\}\}">mod</figure-callout>}2$ 1＜γ≤B，

Here g={g ₁, g ₂..., g ₁₆}={ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,1},

y _k＝y′ _k?k＝1，2，...，B

By the bit scramble process of above 3GPP definition as can be seen, the key of bit scramble is to obtain y ' _k, and y ' _kCan realize with a linear feedback shift register device.

Be illustrated in figure 2 as the bit scramble circuit arrangement that the bit scramble process according to 3GPP definition of prior art obtains, its course of work is as follows:

One group of predetermined initial value of the initial loading of shift register arrangement;

The predetermined bit of shift register arrangement is carried out the summation first time, and summation is exported to the highest significant position of shift register arrangement;

Output bit to predetermined bit sum and CRC adder 001 carries out the summation second time.

But the bit scramble device of 3GPP definition belongs to the serial scrambler, and each clock cycle can only be carried out the scrambling of a bit.When the HS-DSCH data quantity transmitted is big, its coding rate will be affected.May make data can not be fast, transmit at application expeditiously.

Therefore, there is defective in prior art, and awaits improving and development.

Summary of the invention

The parallel method and the device that the purpose of this invention is to provide a kind of bit scramble, being used for high-speed downlink packet access channel carries out, in order to improve the execution speed of bit scramble, adopt parallel device to realize the bit scramble process of 3GPP definition, this device can carry out scrambling to the data of 16 bits simultaneously to be handled.

Technical scheme of the present invention comprises:

A kind of parallel device of bit scramble, wherein, it comprises a bit scrambler sequence maker and a scrambler; Described bit scrambler sequence maker is used for exporting simultaneously 16 scrambler bit components in a clock cycle; Described scrambler is used for exporting simultaneously 16 bit components to after corresponding data piece and the scrambling of described scrambler bit component in a clock cycle.

Described device, wherein, the scrambler bit component of described bit scrambler sequence maker output is made as y _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16), i=0 wherein, 1 ..., N-1, N are the number that needs 16 Bit datas of scrambling; Computing formula is:

With the initial value is y ₀(1), y ₀(2) ..., y ₀(15), y ₀(16);

$\left\{\begin{array}{c}{y}_{i+1}\left(k\right)=y_i\left(k\right)+y_i(k+2)+y_i(k+3)+y_i(k+5);1\&le;k\&le;11\\ y_{i+1}\left(k\right)=y_i(k-11)+y_i(k-9)+y_i(k-8)+y_i(k-6)+y_i\left(k\right)+y_i(k+2)+y_i(k+3);12\&le;k\&le;13\\ y_{i+1}\left(k\right)=y_i(k-13)+y_i(k-10)+y_i(k-9)+y_i(k-6)+y_i(k-1)+y_i\left(k\right)+y_i(k+2);k=14\\ y_{i+1}\left(k\right)=y_i(k-14)+y_i(k-13)+y_i(k-12)+y_i(k-11)+y_i(k-10)+y_i(k-6)+y_i\left(k\right);15\&le;k\&le;16\end{array}\right.---\left(1\right).$

A kind of parallel method of bit scramble, it comprises the steps:

A, obtain 16 bit initial values y of bit scrambler sequence maker according to 3GPP agreement regulation ₀(1), y ₀(2) ..., y ₀(15), y ₀(16);

B, employing formula (1) generate 16 bit scrambler sequence y _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16), i=0 wherein, 1 ..., N-1, N are the number that needs 16 Bit datas of scrambling:

$\left\{\begin{array}{c}{y}_{i+1}\left(k\right)=y_i\left(k\right)+y_i(k+2)+y_i(k+3)+y_i(k+5);1\&le;k\&le;11\\ y_{i+1}\left(k\right)=y_i(k-11)+y_i(k-9)+y_i(k-8)+y_i(k-6)+y_i\left(k\right)+y_i(k+2)+y_i(k+3);12\&le;k\&le;13\\ y_{i+1}\left(k\right)=y_i(k-13)+y_i(k-10)+y_i(k-9)+y_i(k-6)+y_i(k-1)+y_i\left(k\right)+y_i(k+2);k=14\\ y_{i+1}\left(k\right)=y_i(k-14)+y_i(k-13)+y_i(k-12)+y_i(k-11)+y_i(k-10)+y_i(k-6)+y_i\left(k\right);15\&le;k\&le;16\end{array}\right.---\left(1\right)$

C, with 16 bit sequence y of bit scrambler sequence maker output _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16) carry out the scrambling operation with 16 bit input blocks of scrambler respectively, 16 bit components after the output scrambling;

D, repeating step B, C finishes up to all bit scrambles of same data block.

Described method wherein, also comprises:

Repeat above-mentioned steps A, B, C, D, to carry out the scrambling process of polylith data block.

The parallel method of a kind of bit scramble provided by the present invention and device, simultaneously the data of 16 bits have been carried out bit scramble a clock cycle, bit scramble speed has improved 16 times, has shortened the time of bit scramble link in whole HS-DSCH chnnel coding.

Description of drawings

Fig. 1 is the cataloged procedure of high speed descending sharing channel (HS-DSCH) of the 3GPP regulation of prior art;

The serial data scrambling circuit structure that Fig. 2 produces for the bit scramble process according to 3GPP regulation of prior art;

Fig. 3 is the structural representation of the inventive method and device;

Fig. 4 is the circuit structure of the inventive method and device;

Embodiment

Below in conjunction with accompanying drawing, will carry out comparatively detailed explanation to the specific embodiment of method of the present invention and device.

The parallel device of bit scramble of the present invention is used for high-speed downlink packet access channel and carries out, and as shown in Figure 3, this device comprises a bit scrambler sequence maker S001 and a scrambler S002; 16 scrambler bit components of described bit scrambler sequence maker S001 output are given described scrambler S002; 16 bit components after described scrambler S002 output block and the scrambling of bit scrambler sequence.

Concrete, the parallel device of bit scramble of the present invention is a device that generates 16 bit scrambler sequence simultaneously, shown in the upper part of Fig. 4 dotted line and the scrambling apparatus of 16 Bit datas of scrambling simultaneously, shown in the lower part of Fig. 4 dotted line.

The parallel method of bit scramble of the present invention, it comprises following process: the 16 bit initial values y that obtain bit scrambler sequence maker S001 according to 3GPP agreement regulation ₀(1), y ₀(2) ..., y ₀(15), y ₀(16); According to following formula (1), generate 16 bit scrambler sequence y _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16), i=0 wherein, 1 ..., N-1, N are the number that needs 16 Bit datas of scrambling;

$\left\{\begin{array}{c}{y}_{i+1}\left(k\right)=y_i\left(k\right)+y_i(k+2)+y_i(k+3)+y_i(k+5);1\&le;k\&le;11\\ y_{i+1}\left(k\right)=y_i(k-11)+y_i(k-9)+y_i(k-8)+y_i(k-6)+y_i\left(k\right)+y_i(k+2)+y_i(k+3);12\&le;k\&le;13\\ y_{i+1}\left(k\right)=y_i(k-13)+y_i(k-10)+y_i(k-9)+y_i(k-6)+y_i(k-1)+y_i\left(k\right)+y_i(k+2);k=14\\ y_{i+1}\left(k\right)=y_i(k-14)+y_i(k-13)+y_i(k-12)+y_i(k-11)+y_i(k-10)+y_i(k-6)+y_i\left(k\right);15\&le;k\&le;16\end{array}\right.---\left(1\right)$

Then, the 16 bit sequence y that bit scrambler sequence maker S001 is exported _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16) carry out the scrambling operation with the 16 bit input blocks of scrambler S002 respectively, 16 bit components after the output scrambling;

Repeat said process, finish up to all bit scrambles of a data block.

And then repeat above-mentioned each step process, carry out the scrambling process of polylith data block.

Concrete, the course of work of parallel bit scrambling apparatus of the present invention is:

The first step when detecting opening flag START FLAG, according to the regulation of 3GPP, is loaded the initial value y of bit scrambler sequence ₁=1, y ₂=y ₃=...=y ₁₆=0.

In second step, generate bit scrambler sequence y ₁, y ₂..., y ₁₆It may further comprise the steps:

A, to y ₁, y ₂..., y ₁₆In some specific bit sue for peace, comprise 15 2 input sum unit, i.e. 15 2 input XOR unit.Unit 01 is y ₁And y ₄XOR; Unit 02 is y ₂And y ₅XOR; ...; Unit 12 is y ₁₂And y ₁₅XOR; Unit 13 is y ₁₃And y ₁₆XOR; Unit 14 is y ₃And y ₉XOR; Unit 15 is y ₄And y ₁₀XOR.

B, generation bit scrambler sequence y ₁, y ₂..., y ₁₆, realize by 16 sum unit, comprise 11 two input sum unit and 54 input sum unit, i.e. 11 two input XOR unit and 54 input XOR unit.Unit 001 is the XOR of unit 01 and unit 03; Unit 002 is the XOR of unit 02 and unit 04; ...; Unit 010 is the XOR of unit 10 and unit 12; Unit 011 is the XOR of unit 11 and unit 13; Unit 012 is unit 01, unit 03, unit 12 and y ₁₄XOR; Unit 013 is unit 02, unit 04, unit 13 and y ₁₅XOR; Unit 014 is unit 01, unit 05, y ₁₄And y ₁₆XOR; Unit 015 is unit 01, unit 02, unit 14 and y ₁₅XOR; Unit 016 is unit 02, unit 03, unit 15 and y ₁₆XOR;

The result of unit 001 XOR is exported through register, be the bit scrambler sequence y that tries to achieve ₁

The result of unit 002 XOR is exported through register, be the bit scrambler sequence y that tries to achieve ₂

... and so on;

The result of unit 016 XOR is exported through register, be the bit scrambler sequence y that tries to achieve ₁₆

The 3rd step is with the bit scrambler sequence y of second step generation ₁, y ₂..., y ₁₆To 16 Bit data B001 of input, B002 ..., B016 carries out scrambling, output scrambled data D001, and D002 ..., D016.

D001 is B001 and y ₁The result of phase XOR;

D002 is B002 and y ₂The result of phase XOR;

... and so on;

D016 is B016 and y ₁₆The result of phase XOR.

The 4th step repeated for second step, the 3rd step, finished up to all bit scrambles of a data block.

The 5th step repeated above-mentioned four steps of the first step to the again, finished up to all data block scramblings.

The inventive method and device send for the high-speed data packets in the WCDMA wireless communication system, can carry out bit scramble to the data of 16 bits simultaneously a clock cycle, so just shorten the time of bit scramble link in whole HS-DSCH chnnel coding.

But should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims (3)

1. the parallel device of a bit scramble is characterized in that, it comprises a bit scrambler sequence maker and a scrambler; Described bit scrambler sequence maker is used for exporting simultaneously 16 scrambler bit components in a clock cycle; Described scrambler is used for exporting simultaneously 16 bit components to after a data block and the scrambling of described scrambler bit component in a clock cycle; Wherein, the scrambler bit component of described bit scrambler sequence maker output is made as y _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16), i=0 wherein, 1 ..., N-1, N are the number that needs 16 Bit datas of scrambling; Computing formula is:

With the initial value is y ₀(1), y ₀(2) ..., y ₀(15), y ₀(16);

$\left\{\begin{array}{c}{y}_{i+1}\left(k\right)=y_i\left(k\right)+y_i(k+2)+y_i(k+3)+y_i(k+5);1\&le;k\&le;11\\ y_{i+1}\left(k\right)=y_i(k-11)+y_i(k-9)+y_i(k-8)+y_i(k-6)+y_i\left(k\right)+y_i(k+2)+y_i(k+3);12\&le;k\&le;13\\ y_{i+1}\left(k\right)=y_i(k-13)+y_i(k-10)+y_i(k-9)+y_i(k-6)+y_i(k-1)+y_i\left(k\right)+y_i(k+2);k=14\\ y_{i+1}\left(k\right)=y_i(k-14)+y_i(k-13)+y_i(k-12)+y_i(k-11)+y_i(k-10)+y_i(k-6)+y_i\left(k\right);15\&le;k\&le;16\end{array}\right.---\left(1\right).$

2. the parallel method of a bit scramble, it comprises the steps:

A, obtain 16 bit initial values y of bit scrambler sequence maker according to 3GPP agreement regulation ₀(1), y ₀(2) ..., y ₀(15), y ₀(16);

B, adopt following formula (1) to generate 16 bit scrambler sequence y _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16), i=0 wherein, 1 ..., N-1, N are the number that needs 16 Bit datas of scrambling:

$\left\{\begin{array}{c}{y}_{i+1}\left(k\right)=y_i\left(k\right)+y_i(k+2)+y_i(k+3)+y_i(k+5);1\&le;k\&le;11\\ y_{i+1}\left(k\right)=y_i(k-11)+y_i(k-9)+y_i(k-8)+y_i(k-6)+y_i\left(k\right)+y_i(k+2)+y_i(k+3);12\&le;k\&le;13\\ y_{i+1}\left(k\right)=y_i(k-13)+y_i(k-10)+y_i(k-9)+y_i(k-6)+y_i(k-1)+y_i\left(k\right)+y_i(k+2);k=14\\ y_{i+1}\left(k\right)=y_i(k-14)+y_i(k-13)+y_i(k-12)+y_i(k-11)+y_i(k-10)+y_i(k-6)+y_i\left(k\right);15\&le;k\&le;16\end{array}\right.---\left(1\right)$

C, with 16 bit sequence y of bit scrambler sequence maker output _I+1(1), y _I+1(2) ..., y _I+1(15), y _I+1(16) carry out the scrambling operation with 16 bit input blocks of scrambler respectively, 16 bit components after the output scrambling;

D, repeating step B, C finishes up to all bit scrambles of same data block.

3. method according to claim 2 is characterized in that, also comprises:

Repeat above-mentioned steps A, B, C, D, to carry out the scrambling process of polylith data block.

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