KR100416478B1 - Parallel scrambler for dvb-t - Google Patents

Abstract

The invention provides a switching circuit for simplifying clock signal application and switching between byte units and bit units by enabling processing by a parallel method of byte units during scramble processing when one type of clock signal is applied when designing a scramble in a digital transmission system. The present invention relates to a parallel scrambler for DVB-T that is capable of eliminating the scrambler and maximizing efficiency.

Such a parallel scrambler for DVB-T is, in a scrambler in a digital transmission system, 15 flip-flops 110 initialized to a predetermined binary data value and the upper bits (R7-R15) of the 15 flip-flops 110 and A pseudo random binary bit string generation unit (100) configured of eight first exclusive logical sum gates (120) to output an exclusive logical sum operation with adjacent bits of the upper bits and output in parallel in units of bytes, and the pseudo random binary bit. A second exclusive logic gate 210 is provided to process / output the 1-byte scrambled data in parallel by performing an exclusive logical sum operation on the output bits output from the column generator 100 and the 1-byte MPEG2 input bit. It is achieved by being configured to include a scrambled output unit 200.

Description

Parallel scrambler for DV-T {PARALLEL SCRAMBLER FOR DVB-T}

The present invention relates to a parallel scrambler for DVB-T, and more particularly, to scrambling in units of bytes according to the application of a constant clock signal when designing a scramble in a modulation device of digital video broadcasting terrestrial (DVB-T). It relates to a parallel scrambler for DVB-T capable of performing scrambling.

As is well known, the transmission system for digital video broadcasting randomizes the transmission data sequence to prevent interference with other channels, and the distribution of '0' and '1' is not biased for synchronization acquisition or demodulation at the receiving side. In other words, the digital transmission system randomizes and encodes the MPEG data sequence synchronized with the transmission clock before transmitting the transmission data sequence, and modulates it through a modulator to transmit the transmission data to the transmission cable. will be.

The channel encoder of such a general digital transmission system is shown in FIG. As shown therein, the MPEG bitstream is input to the scrambler 20 through the parallel / serial converter 10 to be scrambled, and the Reed-solomon encoder 40 is passed through the serial / parallel converter 30. ), Code encoding is performed in order to correct an error on the communication path in the GRID-Solomon encoder 40, and then the data bit strings are reversed through the interleaver 50, and the channel in the modulator 60 It is designed to modulate the coded data and transmit it through the transmission cable.

However, in the above-described transmission process in the digital transmission system, an interface for transmitting an MPEG bit string when transmitting channel encoded data processes data in units of bytes, whereas a scrambler uses a bit. The Reed-Solomon encoder and the interleaver are configured to process data in byte units. Thus, in order to convert the data into bits and bytes in the data processing, MPEG data inputted in parallel to the scrambler input terminal is 1. A parallel / serial converter 10 for outputting bits in serial should be provided, and the structure of the scrambler output stage must be provided with a serial / parallel converter 30 for outputting the serially output bits in parallel in units of 1 byte. There was a problem with getting lost.

Since the scrambler, the Reed-Solomon encoder, and the interleaver each require a clock signal for 1-bit processing and a clock signal for 1-byte processing in order to process data, two types of clock signals are provided for one data processing. There was a problem that should occur.

Therefore, in order to solve the above problem, the present invention provides a parallel scrambler to process data in byte units according to the application of one clock signal in scramble design, so that only one type of constant clock signal can be provided and thus a clock signal. Since it is possible to pursue unification of the provision and to eliminate the circuit for switching between byte-by-bit and bit-by-bit, it provides a parallel scrambler for DVB-T that simplifies the structure for scramble configuration and maximizes efficiency. Has its purpose.

In order to achieve the above object, the parallel scrambler for DVB-T of the present invention is a scrambler in a digital transmission system, wherein 15 flip-flops are initialized to predetermined binary data values and the upper bits of the 15 flip-flops (R7). A pseudorandom binary bit string (PRBS) generation unit comprising eight first exclusive logical sum gates for parallel output in units of bytes by performing an exclusive logical sum operation on adjacent bits of the upper bits thereof; A scrambled output having a second exclusive logic gate for processing / outputting one byte of scrambled data in parallel by performing an exclusive logical OR operation on the output bits output from the bit string generator (PRBS) and the one-byte MPEG2 input bit. It is characterized in that the addition is configured.

The byte-coded output code outputted from the first exclusive logic gate is fed back to and stored in the first to eighth flip flops of the flip-flops, while the bit strings previously stored in the first to seventh flip flops are It is shifted and stored as an eighth to fifteenth flip-flop.

According to the scrambler having the above-described configuration, since the input terminal and the output terminal of the scrambler are processed in parallel in units of bytes, it can be seen that the circuit which has to be converted between serial processing and parallel processing can be eliminated and the circuit can be simplified.

1 is a block diagram showing a channel encoder of a general digital transmission system;

2 is a block diagram showing a parallel scrambler for DVB-T according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawing

100: pseudorandom binary bit string generation unit, 110: 1st to 15th flip flop,

120: first exclusive logic gate, 200: scrambled output unit,

210: second exclusive logic gate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a parallel scrambler for DVB-T according to a preferred embodiment of the present invention.

As shown in the figure, 15 flip-flops 110 initialized to '100101010000000' and 8 first exclusive logic gates 120 connected by combining the upper bits of the flip-flop are composed of 1-byte pseudo random binary. Pseudo-random binary sequence (PRBS) generation unit 100 for generating a pseudo-random binary sequence (PRBS), and output bits output from the pseudo-random binary bit sequence generation unit 100 and 1 byte And a scramble output unit 200 having a second exclusive logic gate 210 for processing / outputting one byte of scrambled data in parallel by performing an exclusive logical sum operation on the MPEG2 input bits.

In addition, the byte-coded output code output from the first exclusive logic gate 120 is fed back to and stored in the first to eightth flip flops among the flip flops, and is stored in the first to seventh flip flops. The stored bit string is configured to be shifted and stored in the eighth to fifteenth flip-flops.

In addition, the scrambler outputs one byte of scrambled data from the scrambled output unit 200 in parallel, and outputs the first synchronous byte every time the 1-byte MPEG2 input bit is input. When it does, the scrambler runs but does not perform scrambling on the sync byte.

The operation of the parallel scrambler for DVB-T of the present invention configured as described above will be described with reference to FIG.

First, as described above, 15 flip-flops 110 are provided to generate a pseudorandom binary bit string in a transmission system for digital video broadcasting, and the initial values of the flip-flops 110 are set to '100101010000000', respectively. The period of the data bus of the initial value is 8 packets (1 packet = 188 bytes). In other words, if a sync byte is input for every 8 MPEG2 packets, initialization occurs. At this time, the first byte (synchronization byte) of the first packet is provided for synchronization purposes so that the scrambling process is not performed. The scrambler does not operate while the sync byte of the first packet is input so as not to generate a pseudorandom binary bit string.

The input of the digital broadcasting (DVB-T) modulation has an MPEG2 transport stream, and the basic unit of the transport stream is a packet having 188 (204) bytes, and the Reed-Solomon after the scrambler is 188 to 204 bytes. It is desirable that one cycle of data processing has 204 System Clock ticks because it has a structure in bytes.

In such a state, when the first clock signal is synchronized and the sync byte of the first packet is input to the scrambler, the '0' value and the 1-byte MPEG2 input bit that are output by the scrambler non-operation are exclusively logically calculated. The input MPEG2 input bits are output as they are.

Subsequently, when the MPEG2 input bit is input according to the second clock signal, an exclusive logical sum operation is performed on the bits of the upper flip-flop (seventh through fifteenth flip-flop) and the adjacent bits of the upper flip-flop. The output bit string is computed by the MPEG2 input bit and the second exclusive logic gate 210 to output the result.

Subsequently, the MPEG2 input bit for the next clock signal needs to be scrambling. In order to do so, the bit value of the flip-flop for generating a pseudorandom binary bit string must be changed. The byte-coded output code is fed back to and stored as the first to eighth flip-flops among the flip-flops, while the bit sequences previously stored in the first to seventh flip-flops are transferred to the eighth to fifteen flip-flops. By being shifted and stored, the data value of the flip flop is changed.

By repeating the above operation up to 188 clock as described above, one packet data scrambling process is completed.

In other words, the PRBS generation unit 100 combines two bits of the flip-flop bit values of the scrambler and outputs a 1-byte pseudorandom binary bit string through the first double logic gate unit 120 to input 1-bit MPEG2 input. The bits are subjected to exclusive logic operation in the pseudorandom binary bit string and the second exclusive logic gate unit 210 to finally output scrambled data in parallel.

As described above, according to the DVB-T parallel scramble of the present invention, data processing on the scrambler input side and output side is separately processed in units of bits or bytes when transmitting channel coded MPEG data in digital broadcasting. To provide a scrambler that can process data in byte units according to the application of one clock signal in scramble design, it is possible to process the signal according to one type of clock and eliminate the switching circuit that switches between byte unit and bit unit. It is possible to simplify the structure of the scrambler while maximizing the efficiency.

Claims (2)

In scrambler in digital transmission system, 15 exclusive flip-flops 110 initialized to a predetermined binary data value, upper bits R7 to R15 of the 15 flip-flops, and adjacent logical bits of the upper bits to perform an exclusive logical sum operation to output in parallel in units of bytes. A pseudo-random binary bit string generation unit 100 composed of eight first exclusive logic gates 120, A second exclusive logical gate that processes / outputs 1 byte of scrambled data in parallel by performing an exclusive logical OR operation on the output bits output from the pseudorandom binary bit string generation unit 100 and the 1-byte MPEG2 input bit ( Parallel scrambler for DVB-T, characterized in that it comprises a scrambled output unit 200 is provided. The method of claim 1, The byte-coded output code output from the first exclusive logic gate 120 is fed back to and stored as the first to eighth flip-flops among the flip-flops, while the bit strings previously stored in the first to seventh flip-flops are Parallel scrambler for DVB-T, characterized in that shifted to the eighth to fifteenth flip-flop.