JPH05260041A - Feedback shifting scramble pattern generating circuit - Google Patents

Abstract

PURPOSE:To arbitrarily set the generating pattern of a scramble pattern and to deal with a serial/parallel pattern without providing any conversion circuit by feeding back and shifting any arbitrary pattern. CONSTITUTION:This circuit is composed of a shift register 7 with N-bit load composed of D flip-flops 1, 2 and 3 and selectors 4, 5 and 6 and by writing patterns 1-N set to terminals 8, 9 and 10 to the shift register 7 at the load timing of a terminal 14 and successively feeding back and shifting the patterns at arbitrary speed, the scramble patterns 1-N of the patterns 1-N to be successively shifted are outputted from terminals 11, 12 and 13. On the other hand, a serial data scramble circuit is composed of a shift register 15 with N-bit load and an exclusive OR circuit 16 and outputs scramble data from a terminal 18 by exclusively ORing the serial data of the terminal 17 and the output scramble pattern 1 of the shift register 15 with Nbit load.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble pattern generation circuit used for digital communication.

[0002]

2. Description of the Related Art A conventional circuit is disclosed in JP-A-2-172340.
As represented by the serial scramble signal generating means described in Japanese Patent Laid-Open Publication No.
The scramble pattern is generated by the exclusive OR of the outputs from the predetermined points of the type flip-flop.

[0003]

In the above prior art, it is difficult to arbitrarily set the generation pattern of the scramble pattern when generating an arbitrary scramble pattern,
Further, when the serial pattern is made to correspond to the parallel pattern of the same pattern, a conversion circuit for converting the serial pattern to the parallel pattern is necessary, which is difficult to cope with.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, to set a scramble pattern generation pattern arbitrarily, and to enable serial / parallel correspondence without a conversion circuit.

[0005]

To achieve the above object, a scramble pattern is generated by feedback-shifting an arbitrary pattern with a shift register at an arbitrary operation speed.

[0006]

Operation: An arbitrary pattern for one cycle is written in the shift register and sequentially shifted at an arbitrary speed. Further, by performing feedback shift, a scramble pattern of a constant cycle is repeatedly generated.

As a result, the generation pattern of the scramble pattern can be set arbitrarily, and since the scramble pattern for one cycle is always output from the shift register, the serial pattern is converted into a parallel pattern without a conversion circuit. / Parallel support is possible.

[0008]

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a configuration example of a feedback shift type scramble pattern generation circuit according to the present invention, FIG. 2 is a serial data scramble circuit according to the present invention, and FIG. 3 is an embodiment of a parallel data scramble circuit according to the present invention. Is.

The feedback shift type scramble ton generation circuit shown in FIG. 1 is composed of a shift register 7 with N-bit load consisting of D type flip-flops 1, 2 and 3 and selectors 4, 5 and 6, and a load timing of a terminal 14. And terminal 8,
By writing the patterns 1 to N set to 9 and 10 in the shift register and sequentially feedback-shifting the patterns at an arbitrary speed, scramble patterns 1 to N of patterns 1 to N sequentially shifted from the terminals 11, 12, and 13 are generated. Output.

The serial data scramble circuit shown in FIG. 2 is composed of an N-bit load-equipped shift register 15 and an exclusive OR circuit 16, and the serial data at the terminal 17 and the output scramble pattern 1 of the N-bit load-equipped shift register 15. By taking the exclusive OR, the terminal 18
More scrambled data is output.

The parallel data scramble circuit shown in FIG. 3 comprises an N-bit load-equipped shift register 19 and exclusive OR circuits 20, 21, 22 and terminals 23, 2
The scramble data 1 to N are output from the terminals 26, 27 and 28 by taking the exclusive OR of the parallel data 4 and 25 and the output scramble patterns 1 to N of the shift register 19 with N-bit load.

As described above, according to the present embodiment, the generation pattern of the scramble pattern can be arbitrarily set by changing the pattern settings of the patterns 1 to N set at the terminals 8, 9 and 10 in FIG. It is possible, and as shown in FIGS. 2 and 3, the correspondence of serial / parallel data can be configured without a conversion circuit for converting a serial pattern into a parallel pattern.

[0014]

Since the present invention is configured as described above, the scramble pattern generation pattern can be set arbitrarily. Further, the serial pattern can be made to correspond to the parallel pattern of the same pattern without the conversion circuit for converting the serial pattern into the parallel pattern.

[Brief description of drawings]

FIG. 1 is a feedback shift type scramble ton generation circuit diagram of the present invention.

FIG. 2 is a serial data scramble circuit diagram according to the present invention.

FIG. 3 is a parallel data scramble circuit diagram according to the present invention.

[Explanation of symbols]

1, 2, 3 ... D-type flip-flop, 4, 5, 6 ... Selector, 7, 15, 19 ... Shift register with N-bit load, 8, 9, 10 ... Pattern 1-N input terminals, 11, 12, 13 ... scramble pattern 1 to N output terminal, 14 ... load signal input terminal, 16, 20, 21, 22 ... exclusive OR circuit, 17 ... serial data input terminal, 18 ... serial scramble data output terminal, 23, 24, 25 ... Parallel data 1-N input terminals, 26, 27, 28 ... Parallel scramble data 1-N
Output terminal.

Claims (1)

[Claims] 1. A feedback shift type scramble pattern generation circuit for generating a scramble pattern by feedback-shifting an arbitrary pattern.