CN1964478A - A random processing method for scrambling/descrambling in digital video broadcast system - Google Patents
A random processing method for scrambling/descrambling in digital video broadcast system Download PDFInfo
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- CN1964478A CN1964478A CN 200610119288 CN200610119288A CN1964478A CN 1964478 A CN1964478 A CN 1964478A CN 200610119288 CN200610119288 CN 200610119288 CN 200610119288 A CN200610119288 A CN 200610119288A CN 1964478 A CN1964478 A CN 1964478A
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Abstract
The advanced processing method for scrambling/descrambling in digital multimedia TV broadcast system comprises: at the transmission end, before adding serial data into the demodulator, using a pseudo-random sequence binary generator to take random process to long sequence of ''1'' and ''0'' in multiplexed code flow, and employing paralleled multi-digit transmission; at receiving end, taking same random process. This invention increases system throughput, and prevents series problems led by serial-to-parallel conversion.
Description
Technical field
The invention belongs to channel coding technology field in the digital video broadcast system, relate to the scrambling/scramble process method in a kind of digital video broadcast system particularly.
Background technology
The digital communication theory all is " 0 " with " 1 when the design of communications system in the bit stream that transmitted of hypothesis " be that equiprobability occurs, and also practical communication system and relevant design performance index also are assumed to be prerequisite with this.But multiplexing code stream continuous " 0 " or continuous " 1 " may occur therein through after the encoding process.Destroyed the prerequisite of system design so on the one hand, the system that makes might not reach the performance index of design; On the other hand, it is synchronous to carry out the demodulation sign indicating number at first to extract bit clock before receiving terminal carries out channel-decoding, the extraction of bit clock is to utilize the waveform saltus step between " 0 " and " 1 " in the transmission code stream to realize, and continuous " 0 " or continuous " 1 " have brought difficulty for the extraction of bit clock, promptly can't provide enough timing informations.For " 0 " in the data code flow that guarantees under any circumstance to enter ground digital multimedia/television broadcasting system transmission system can both equate substantially that with the probability of " 1 " transmission system at first upsets processing with a pseudo random sequence to the TS code stream of input.
Summary of the invention
The objective of the invention is to propose a kind of random processing method that in digital video broadcast system, chnnel coding is carried out scrambling/descrambling, equal substantially with the probability of " 0 " in the data code flow of guaranteeing transmission system and " 1 ".
Method of randomization of in digital video broadcast system, chnnel coding being carried out scrambling/descrambling of the present invention, concrete steps are as follows:
At transmitting terminal, long sequence to " 1 " in the multiplexing code stream and " 0 " is carried out randomization: added a pseudo-random binary sequence generator before serial data enters modulator, carry out scrambling or with the data code flow randomization, and adopt parallel multidigit to send and transmission method.Transmit and added pseudo-random binary sequence (PRBS) maker in the multiplexing bag, if what will finish system requirements is that unit sends and transmits with the byte, need before randomization, to carry out parallel/serial conversion, after randomization, need to carry out serial/parallel conversion.And adopted parallel multidigit processing method, just can avoid problems such as the stream rate that brings because of these conversions and clock rate adjustment.
In the inventive method, also comprise the randomization step of receiving terminal:
1) in receiving terminal, will carry out randomization: added before serial data enters modulator that a pseudo random sequence binary generator carries out descrambling or with the data code flow randomization through the long sequence of " 1 " and " 0 " after the RS decoding;
2) add the pseudo-random binary sequence maker in the multiplexing bag of transmission, and adopted parallel multidigit to send and transmission method.
Among the present invention, produce pseudo-random binary sequence (Pseudo RandomBinary Sequences PRBS) for any N level linear feedback shift register, its proper polynomial is f (x)=1+X
m+ X
1, (m, 1＜n), as shown in Figure 1.The realization of the pseudo-random binary sequence of serial: the sequence buffer memory is numbered b respectively
1, b
2, b
3B
n, after first allowed the clock pulse of output, output is O as a result
1=b
m^b
1, become O after the buffer memory displacement
1, b
1, b
2B
nAfter second clock pulse that allows to export, output is O as a result
2=b
14^b
13, become O after the buffer memory displacement
2, O
1, b
1... b
nThe rest may be inferred, system clock synchronously down, the generation of random sequence and the displacement of register series, strictness is carried out sequentially successively, producing parallel pseudo-random binary sequence, send and transmission means at parallel multidigit, can realize parallel processing data scrambling/descrambling.
Among the present invention, at the China Digital TV ground transmission standard, use one 15 grades linear feedback shift register to produce pseudo-random binary sequence (Pseudo Random Binary Sequences PRBS), its proper polynomial is f (x)=1+X
14+ X
15, as shown in Figure 1.The realization of the pseudo-random binary sequence of serial: the sequence buffer memory is numbered b respectively
1, b
2, b
3B
15, after first allowed the clock pulse of output, output is O as a result
1=b
15^b
14, become O after the buffer memory displacement
1, b
1, b
2B
14After second clock pulse that allows to export, output is O as a result
2=b
14^b
13, become O after the buffer memory displacement
2, O
1, b
1... b
13The rest may be inferred, system clock synchronously down, the generation of random sequence and the displacement of register series, strictness is carried out sequentially successively, can produce parallel pseudo-random binary sequence, send and transmission means at parallel multidigit, realize parallel processing data scrambling/descrambling.
Pseudo random sequence is to be generated by the pseudo-random sequence generator of a standard, and wherein the probability that occurs of " 0 " and " 1 " is near 50%.Because the special nature of binary numeral computing, after with pseudo random sequence the TS code stream of input being upset, can make the probability of occurrence approximately equal of " 0 " and " 1 " in the data code flow after upsetting.Upset has changed original bit stream, therefore after receiving terminal is to the transmission code stream error correction decoding, also needs according to the transmitting terminal processing procedure it to be carried out scramble process, to recover original bit stream.
From the angle of power spectrum signal, the upset process is equivalent to the power spectrum of digital signal is expanded, and it is spread out, because of upset process only be otherwise known as " energy dispersion ".In ground digital multimedia/television broadcasting system system (DMBT), use one 15 grades linear feedback shift register to produce pseudo-random binary sequence (Pseudo Random BinarySequences PRBS), its proper polynomial is f (x)=1+X
14+ X
15, linear feedback logic a
15=a
0 a
1, when per 8 transmission package begin, sequence is initialized as carrying out by the agreement appointment.
The pseudo-random binary sequence system can use d type flip flop and XOR gate to realize.Pseudo-random binary sequence with the China Digital TV ground transmission standard is embodied as example, as Fig. 1.In this system, the sequence that is randomized is if the binary message of serial.Suppose to support that the hardware maximum speed of this system is 100M, the high transmission speed of using that this system can realize is exactly 100Mbps.When the input data are parallel sequence or back-end processing when requiring to be parallel data, also need to carry out parallel/serial or serial/parallel conversion.If it is higher that transmission speed requires, the performance of this part function may become the fatal bottleneck of system.If according to parallel data transfer mode, adopt and realize parallel pseudo random sequence, the data throughout of system will be doubled and redoubled.Hypothetical sequence can expand to N position (1＜N＜14), and then under the clock of 100M, the throughput of system can reach N * 100Mbps, is N times of tandem system performance, can also avoid parallel/serial, a series of problems that processes such as serial/parallel conversion are brought.
Description of drawings
Fig. 1 scrambling/descrambling schematic diagram.
The parallel pseudo-random binary sequence in N position (N=8) in Fig. 2 scrambling/descrambling realizes.
Embodiment
With N=8 is the detailed process that example illustrates the inventive method:
The realization of the pseudo-random binary sequence of serial, the sequence buffer memory is numbered b respectively
1, b
2, b
3B
15, after first allowed the clock pulse of output, output is O as a result
1=b
15^b
14, become O after the buffer memory displacement
1, b
1, b
2B
14After second clock pulse that allows to export, output is O as a result
2=b
14^b
13, become O after the buffer memory displacement
2, O
1, b
1... b
13The rest may be inferred, the generation of random sequence and the displacement of register series, and in descending synchronously of system clock, strictness is carried out sequentially successively, handles the relation of displacement and random sequence well, can use the mode of parallel processing to realize this system.And the pseudo-random binary sequence of line output realizes theory diagram as shown in Figure 2.
Send and transmission means at parallel multidigit, can realize the data scrambling/descrambling of parallel processing.
In the present invention, used 32 logical blocks,, on the performance of data processing, but improved 8 times, had higher handling property the use amount of logical block manyed 1 times than serial sequence.
In this example, N=8 has realized the efficient pseudo-random binary sequence processing of 8 parallel-by-bits.In like manner, in scrambling/scramble process, can select the bit wide of parallel processing according to the system transmissions rate requirement of reality, N can get 1,2,3 ... any one numerical value in 14; Its processing method and thought not only can act on scrambling/descrambling, can also be applicable to that all need the PN sequence, carry out the functional module that shift register is handled.
Claims (4)
1, a kind of chnnel coding is carried out the random processing method of scrambling/descrambling, it is characterized in that, may further comprise the steps:
1) in transmitting terminal, the long sequence of " 1 " in the multiplexing code stream and " 0 " is carried out randomization: added before serial data enters modulator that a pseudo random sequence binary generator carries out scrambling or with the data code flow randomization;
2) add the pseudo-random binary sequence maker in the multiplexing bag of transmission, and adopt parallel multidigit to send and transmission method.
2, processing method according to claim 1 is characterized in that, also comprises the randomization step of receiving terminal:
1) in receiving terminal, will carry out randomization: added before serial data enters modulator that a pseudo random sequence binary generator carries out descrambling or with the data code flow randomization through the long sequence of " 1 " and " 0 " after the RS decoding;
2) add the pseudo-random binary sequence maker in the multiplexing bag of transmission, and adopt parallel multidigit to send and transmission method.
3. processing method according to claim 2 is characterized in that: produce pseudo-random binary sequence for any N level linear feedback shift register, its proper polynomial is f (x)=1+X
m+ X
1, (m, 1＜n), the realization of the pseudo-random binary sequence of serial: the sequence buffer memory is numbered b respectively
1, b
2, b
3B
n, after first allowed the clock pulse of output, output is O as a result
1=b
m^b
1, become O after the buffer memory displacement
1, b
1, b
2B
nAfter second clock pulse that allows to export, output is O as a result
2=b
14^b
13, become O after the buffer memory displacement
2, O
1, b
1... b
nThe rest may be inferred, system clock synchronously down, the generation of random sequence and the displacement of register series, strictness is carried out sequentially successively, producing parallel pseudo-random binary sequence, send and transmission means at parallel multidigit, realize parallel processing data scrambling/descrambling.
4. processing method according to claim 3 is characterized in that: at the China Digital TV ground transmission standard, use one 15 grades linear feedback shift register to produce pseudo-random binary sequence, its proper polynomial is f (x)=1+X
14+ X
15, the realization of the pseudo-random binary sequence of serial: the sequence buffer memory is numbered b respectively
1, b
2, b
3B
15, after first allowed the clock pulse of output, output is O as a result
1=b
15^b
14, become O after the buffer memory displacement
1, b
1, b
2B
14After second clock pulse that allows to export, output is O as a result
2=b
14^b
13, become O after the buffer memory displacement
2, O
1, b
1... b
13The rest may be inferred, system clock synchronously down, the generation of random sequence and the displacement of register series, strictness is carried out sequentially successively, producing parallel pseudo-random binary sequence, send and transmission means at parallel multidigit, realize parallel processing data scrambling/descrambling.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011026262A1 (en) * | 2009-09-03 | 2011-03-10 | 卓胜微电子（上海）有限公司 | Method for capturing control logic channel used in china mobile multimedia broadcasting system |
| CN101599811B (en) * | 2008-06-02 | 2011-04-06 | 华为技术有限公司 | Data processing device, communication equipment and data processing method |
| CN101669365B (en) * | 2007-11-30 | 2011-06-22 | 哉英电子股份有限公司 | Video signal transmission device, video signal reception device, and video signal transmission system |
| CN102136885A (en) * | 2011-03-29 | 2011-07-27 | 中国科学院计算技术研究所 | Parallel physical uplink shared channel (PUSCH) interleaving and scrambling realization method and system for 3rd-generation partnership project long term evolution (3GPP LTE) |
| CN102208210A (en) * | 2010-03-31 | 2011-10-05 | 深圳市朗科科技股份有限公司 | Flash memory device and data storage method thereof |
| CN101335549B (en) * | 2008-08-06 | 2013-01-02 | 北京创毅视讯科技有限公司 | Multiplex apparatus and multiplex method |
-
2006
- 2006-12-07 CN CN 200610119288 patent/CN1964478A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101669365B (en) * | 2007-11-30 | 2011-06-22 | 哉英电子股份有限公司 | Video signal transmission device, video signal reception device, and video signal transmission system |
| CN101599811B (en) * | 2008-06-02 | 2011-04-06 | 华为技术有限公司 | Data processing device, communication equipment and data processing method |
| US8514833B2 (en) | 2008-06-02 | 2013-08-20 | Huawei Technologies Co., Ltd. | Data processing apparatus, communications device, and data processing method |
| US8665856B2 (en) | 2008-06-02 | 2014-03-04 | Huawei Technologies Co., Ltd. | Data processing apparatus, communication device, and data processing method |
| CN101335549B (en) * | 2008-08-06 | 2013-01-02 | 北京创毅视讯科技有限公司 | Multiplex apparatus and multiplex method |
| WO2011026262A1 (en) * | 2009-09-03 | 2011-03-10 | 卓胜微电子（上海）有限公司 | Method for capturing control logic channel used in china mobile multimedia broadcasting system |
| CN102006254B (en) * | 2009-09-03 | 2013-03-06 | 卓胜微电子（上海）有限公司 | Method for capturing and controlling logic channel for China mobile multimedia broadcasting system |
| CN102208210A (en) * | 2010-03-31 | 2011-10-05 | 深圳市朗科科技股份有限公司 | Flash memory device and data storage method thereof |
| CN102136885A (en) * | 2011-03-29 | 2011-07-27 | 中国科学院计算技术研究所 | Parallel physical uplink shared channel (PUSCH) interleaving and scrambling realization method and system for 3rd-generation partnership project long term evolution (3GPP LTE) |
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Open date: 20070516 |