CN101174914A - Code error correcting system and its transmission device, receiving device and code error correction method - Google Patents
Code error correcting system and its transmission device, receiving device and code error correction method Download PDFInfo
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- CN101174914A CN101174914A CNA200610063396XA CN200610063396A CN101174914A CN 101174914 A CN101174914 A CN 101174914A CN A200610063396X A CNA200610063396X A CN A200610063396XA CN 200610063396 A CN200610063396 A CN 200610063396A CN 101174914 A CN101174914 A CN 101174914A
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Abstract
The present invention relates to an emitter of the error code correcting system; the emitter comprises a scrambling code processing module which is used for implementing code scrambling process on the primary data to produce scrambling data; an interweaving coding module which is used for interweaving coding on the scrambling code to produce interweaving data and implementing correcting coding on the interweaving data; after an checking code is produced, checking data are produced after the code is implemented with interweaving coding process; a pilot code addition module which is used for adding pilot codes to the interweaving data and the checking data to produce interweaving data. The present invention also provides a corresponding receiver, an error code correcting system and an error code correcting method. The present invention implements correction coding on the data after the code scrambling process to overcome the error spread caused by the code scrambling process.
Description
Technical field
The present invention relates to the communications field, more particularly, relate to a kind of code error correcting system and dispensing device thereof, receiving system and code error correction method.
Background technology
In order to ensure the cost benefit of Ethernet operation, ten thousand megabit ethernet standards have been introduced new 64b/66b coding, make transmission rate near 10Gbps (bits per second, bits per second).For the 10Gbps transmission rate, have only 3.125% to be used for the consumption of non-transmission data in the 64B/66B coding, and can in the time that does not influence transmission, finish encoding process.This coding method is adopted by IEEE 802.3 10Gbps standards.
That 8 Bit datas are mapped as predefined 10 bits of encoded is different with 8b/10b coding, and the 64b/66b coding adopts the method for scrambler.The data of each 64 bit are carried out the scrambler processing in self-synchronous scrambler (the scrambler multinomial is x
58+ x
39+ 1); Then, dibit is led sign indicating number and add the code word of handling through scrambler to.If code word only comprises data byte, lead sign indicating number so and be " 01 "; If code word had both comprised data byte and also comprised control byte, lead sign indicating number so and be " 10 " (as shown in Figure 1).Lead sign indicating number " 00 " and " 11 " and be regarded as invalid code word, this packet is invalid.
Although the 64b/66b coding is a kind of high efficient coding mechanism, and has become the coding candidate of a kind of brute force of high speed interframe interconnection, chip interconnect and backplane interconnect.But the scrambling device of 64b/66b is brought a problem of can not ignore, and is exactly the error propagation problem.When certain bit error code took place link, this error code can influence the 39th and the 59th decoding of follow-up arrival, causes this dibit also will produce error code, i.e. error propagation (error propagation).
In addition, because the traffic rate of single link is more and more higher, in order to overcome the intersymbol interference problem that channel attenuation causes, many chips have adopted complicated signal processing apparatus, and decision feedback equalization device (DFE) is exactly one of them.The decision feedback equalization device is a kind of very effective intersymbol interference device that overcomes, and in the 10Gbps speed range, the decision feedback equalization device almost becomes a kind of essential device.The structure of decision feedback equalization device as shown in Figure 2.The processing formula of decision feedback equalization device is: the title that please unify same technical characterictic
V(T
0)＝V
in(T
0)-W
1*D(T
-1)-W
2*D(T
-2)-A-W
N*D(T
-N)。
Equally, its superior performance of decision feedback equalization device also exists a problem of can not ignore, i.e. error propagation problem behind.The output of decision feedback equalization device is relevant with preceding N bit information.Error code has taken place in certain bit in the current N bit information, will influence the decision feedback equalization result of current bit so, also just may produce the erroneous judgement of current bit, and error code takes place.And this error propagation characteristic produces continuous several error code possibly.
In order to reach the error rate requirement of ethernet interconnect under the existing 10Gbps speed, adopt traditional optimization link and signal processing technology can not finish such requirement, need be by error correction coding.Prior art has proposed employing CRC (Cycle Redundancy Check, the cyclic redundancy check (CRC)) method that 16 encoder for correcting carry out error correction to the 64b/66b error propagation, and wherein the multinomial of CRC16 is: x
16+ x
12+ x
5+ 1.CRC16 buffer form is: two 64 bit codewords are as the information source of CRC16 error correction coding, and error correction coding will produce the CRC16 check code of 16 bits, with the CRC check code combination of 8 64 bits together, form the checking data of one 64 bit.By at receiving terminal checking data is carried out CRC check and with the CRC check result non-vanishing time contrast error code form, this error code charting the various error code situations that occur when propagating of 64b/66b coding.CRC16 can correct any one bit error code in 128 bit codewords, and can detect any dibit error condition of 128 bits.For example when the data consistent of the capable j of the i in CRC check result and error code form row, just show the j bit generation error code of i code word.
Yet the error code characteristic when this scheme can only be propagated a part of 64b/66b coding adds the error code form.As previously mentioned and since the 64b/66b scrambling device just occur in preceding two 64 bit codewords error propagation in 64 bit codewords of postorder, thereby a code word of postorder has just produced the error code of dibit, CRC16 can't correct this mistake.And this error condition has no idea to solve by the error code form.For the error propagation problem that the decision feedback equalization device produces, this scheme can't solve equally.The error code of continuous several bits that the decision feedback equalization device produces, by the error propagation of 64b/66b, it is bigger, wideer that the error code scope will become again, and relying on the CRC16 error correcting technique merely is the error correction that may not finish this error code.
Summary of the invention
The technical problem to be solved in the present invention is, can't solve the error propagation in the high-speed transfer and adjudicate the balanced error propagation problem that produces at above-mentioned CRC16 verification, a kind of code error correcting system and dispensing device thereof, receiving system and code error correction method are provided.
The embodiment of the invention solves the technical scheme that its technical problem adopts: construct a kind of dispensing device of code error correcting system, include:
The scrambler processing module is used for that initial data is carried out scrambler and handles, and generates the scrambler data;
The interweaving encoding module is used for that described scrambler data are carried out interweaving encoding and generates interleaving data, and described interleaving data is carried out error correction coding, behind the generation check code, described check code is carried out interweaving encoding generate checking data;
Lead sign indicating number and add module, be used for described interleaving data and the interpolation of described checking data are led sign indicating number, generate coded data.
The present invention also provides a kind of receiving system of code error correcting system, comprising:
Lead a yard synchronization module, be used for that sign indicating number is led in the coded data use that receives and carry out synchronously, and described coded data is separated into interleaving data and checking data;
Correction module is used for described checking data is reverted to the check code of normal sequence, and uses described check code that described interleaving data is carried out error correction decoding;
The scramble process module is used for the interleaving data behind the described error correction decoding is done scramble process, reverts to initial data.
The present invention also provides a kind of code error correcting system, comprises dispensing device and receiving system;
Described dispensing device comprises:
The scrambler processing module is used for that initial data is carried out scrambler and handles, and generates the scrambler data;
The interweaving encoding module is used for that described scrambler data are carried out interweaving encoding and generates interleaving data, and described interleaving data is carried out error correction coding, behind the generation check code, described check code is carried out interweaving encoding generate checking data;
Lead sign indicating number and add module, be used for described interleaving data and the interpolation of described checking data are led sign indicating number, generate coded data;
Described receiver module comprises:
Lead a yard synchronization module, be used for that sign indicating number is led in the coded data use that receives and carry out synchronously, and described coded data is separated into interleaving data and checking data;
Correction module is used for described checking data is reverted to the check code of normal sequence, and uses described check code that described interleaving data is carried out error correction decoding;
The scramble process module is used for the data behind the described error correction decoding are done scramble process, reverts to initial data.
The present invention also provides a kind of code error correction method, may further comprise the steps:
(a) dispensing device receives initial data, and described initial data is carried out scrambler handle, and generates the scrambler data;
(b) described scrambler data are carried out interweaving encoding, generate interleaving data, and carry out error correction coding, generate checking data according to described interleaving data;
(c) be that sign indicating number is led in the interpolation of described interleaving data and described checking data, generate coded data, send described coded data.
Carry out after scrambler is handled because the embodiment of the invention is carried out error correction coding to data, changed in the past and before scrambler is handled, carried out error correction coding, handle the error propagation problem of bringing thereby overcome scrambler.In addition, the embodiment of the invention has also overcome the error propagation problem that the processing of decision feedback equalization device produces.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation of coded data in the prior art 64b/66b coding;
Fig. 2 is the structural representation of the decision-feedback device in the prior art high-speed link;
Fig. 3 is the logic diagram of the embodiment of code error correcting system in the high speed transmission system of the present invention;
Fig. 4 is the schematic diagram that system carries out interweaving encoding among Fig. 3;
Fig. 5 is the schematic diagram that system carries out interweaving encoding among Fig. 3 to check code;
Fig. 6 is the schematic diagram that system reverts to checking data the normal sequence check code among Fig. 3;
Fig. 7 is the flow chart of an embodiment of the code error correction method in the high speed transmission system of the present invention.
Embodiment
As shown in Figure 3, an embodiment of the code error correcting system in the high speed transmission system of the present invention comprises dispensing device 31 and receiving system 32;
Described dispensing device 31, be used for that initial data is carried out the scrambler processing and obtain the scrambler data, described scrambler data are carried out interweaving encoding generate interleaving data and checking data, and described interleaving data and checking data added lead the sign indicating number back and generate a coded data, send described coded data to described receiving system 32 by high-speed transfer link 33;
Described receiving system 32 is used for using and leads sign indicating number described coded data is carried out synchronously, after interleaving data and checking data are separated, described interleaving data is carried out error correction, and carries out scramble process and obtain initial data finishing interleaving data after the error correction.
Wherein high-speed transfer link 33 can be ethernet link, high speed interframe interconnection link, chip interconnect link and backplane interconnect link etc., and dispensing device 31 and receiving system 32 then can be the relevant devices in these links.
In the present embodiment, described dispensing device 31 specifically comprises first data processing module 311, scrambler processing module 312, interweaving encoding module 313, leads sign indicating number interpolation module 314 and sending module 315;
Described first data processing module 311 is used to receive and deal with data and the initial data to be sent that will handle are sent to scrambler processing module 312; In concrete the application, this first data processing unit 311 can be data sink, data deciphering device or processing unit etc., and the data processing of first data processing unit 311 can be Data Receiving operation, data decode or data transaction etc.;
Described scrambler processing module 312 is used for that the initial data of handling through first data processing module 311 to be sent is carried out scrambler and handles generation scrambler data, for example uses scrambler multinomial x
58+ x
39+ 1 carries out scrambler handles;
Described interweaving encoding module 313 is used for that described scrambler data are carried out interweaving encoding and generates interleaving data, and described interleaving data is carried out error correction coding, behind the generation check code, described check code is carried out interweaving encoding generate checking data.
The described sign indicating number of leading adds module 314, is used for described interleaving data and the interpolation of described checking data are led sign indicating number, generates coded data.
Described sending module 315 is used to send described coded data.
In the present embodiment, interweaving encoding module 313 can adopt CRC 16 error correction coding modes when generating check code.When specific implementation, interweaving encoding module 313 can comprise:
Check code generates submodule, is used for the interleaving data of two the 64 bits information source as CRC 16 error correction codings is produced CRC 16 check codes of 16 bits;
Checking data generates submodule, is used for CRC 16 check codes of 4 16 bits are formed the checking data of one 64 bit;
The submodule that interweaves is used for the synthetic code word of scrambler data set and uses the buffer memory (the corresponding interleaving data of the data of each buffer memory) of 4 128 bits that code word is carried out interweaving encoding, as shown in Figure 4.In the present embodiment, the data set of two 64 bits synthesizes a code word, and 4 buffer memorys can be stored 64 bytes altogether, and numbering is from (the b0～b63) that 0 is arranged into 63.The bit of each byte is arranged in the buffer memory according to the form of interlaced code, and the bit 0～bit 3 of b0 byte is successively placed in 0 bit of buffer memory 0～buffer memory 3, and the bit 4～bit 7 of b0 byte also is successively placed on 1 bit of buffer memory 0～buffer memory 3.By this order, placed all 64 bytes: the bit 0～bit 3 of b63 byte is successively placed in 126 bits of buffer memory 0～buffer memory 3, and the bit 4～bit 7 of b63 byte also is successively placed on 127 bits of buffer memory 0～buffer memory 3.The submodule that interweaves generates checking data according to the data in buffer memory 0, buffer memory 1, buffer memory 2 and the buffer memory 3 of 128 bits respectively.Certainly, use the buffer memory of 4 128 bits that code word is carried out interweaving encoding, just one of present embodiment preferred embodiment, in actual applications, the submodule that interweaves can use the buffer memory of N 128 bits that code word is carried out interweaving encoding, wherein N be 4 or 4 certificate doubly, and N is greater than 1, less than 128.
Correspondingly, the described sign indicating number of leading adds module 314 according to above-mentioned interleaving data information, increases lead yard (with reference to the figure 1) of corresponding 64b/66b coding, thereby generates coded data.When sending coded data by sending module 315, according to the normal sequence transmission of coded data, thereby the scrambler that does not influence data is handled.
When the data message to buffer memory 0, buffer memory 1, buffer memory 2 and the buffer memory 3 of 128 bits carries out error correction coding, produce 4 16 bit CRC 16 check codes, be respectively c0, c1, c2 and c3.When carrying out the interweaving encoding of check code, use the buffer memory of 4 16 bits, numbering from 0 ' to 3 '.The bit of each check code places buffer memory according to the form of interlaced code, and also is interweaved between the check code.Bit 0～the bit 3 of c0 check code is successively placed on 0 bit of buffer memory 0 '～buffer memory 3 '; Bit 0～the bit 3 of c1 check code is successively placed on 1 bit of buffer memory 0 '～buffer memory 3 '; Bit 0 ~ the bit 3 of c2 check code is successively placed on 2 bits of buffer memory 0 '～buffer memory 3 '; Bit 0 ~ the bit 3 of c3 check code is successively placed on 3 bits of buffer memory 0 '～buffer memory 3 '.According to top order, placed the check code of 4 16 bits successively; Finally, the bit 12～bit 15 of c0 check code is successively placed on 12 bits of buffer memory 0 '～buffer memory 3 '; Bit 12～the bit 15 of c1 check code is successively placed on 13 bits of buffer memory 0 '～buffer memory 3 '; Bit 12～the bit 15 of c2 check code is successively placed on 14 bits of buffer memory 0 '～buffer memory 3 '; Bit 12～the bit 15 of c3 check code is successively placed on 15 bits of buffer memory 0 '～buffer memory 3 '.
4 CRC 16 check codes are combined into the checking data of 64 bits, do not do any scrambler and handle, and interpolation is led sign indicating number and is " 01 ".The reason that CRC 16 checking datas that produce do not need to handle is, through x
58+ x
39The data that+1 scrambler is handled, the CRC 16 (x of generation
16+ x
12+ x
5+ 1) 16 zero or 1 (x can not appear in check code
58+ x
39+ 1 multinomial can not be by x
16+ x
12+ x
5+ 1 multinomial is divided exactly, and long 0 or long 1 situation therefore can not occur).4 CRC 16 checking datas are combined, and have more reduced the probability that this situation occurs.Thereby the error propagation problem of the error propagation of decision feedback equalization device and scrambler can not have influence on checking data yet.Lead after sign indicating number handles finishing, checking data sends form and also sends to receiving system 32 according to the form in the buffer memory by sending module.
In the present embodiment, check code generates submodule and use binary data t (x) * x to be sent when generating CRC 16 check codes
r, divided by generator polynomial g (x), with last remainder as the CRC check sign indicating number.Implementation step is as follows: (1) establishes the binary system multinomial t (x) that data block to be sent is the m position; (2) generator polynomial is the g (x) on r rank.Add r individual 0 at the end of data block; (3) length of data block is increased to the m+r position; (4) Dui Ying binary system multinomial is t (x) * x
r(5) remove with generator polynomial g (x); (6) trying to achieve remainder is that exponent number is the binary system multinomial y (x) of r-1.This binary system multinomial y (x) is exactly the CRC check sign indicating number of t (x) through generator polynomial g (x) coding.In this embodiment, in fact CRC 16 check codes are exactly r=17, m=128 position, g (x)=x
16+ x
12+ x
5+ 1.
In the present embodiment, receiving system 32 can specifically comprise:
Lead yard synchronization module 324, being used for that sign indicating number is led in the coded data use that described receiver module 325 receives carries out synchronously, promptly revert to the order of sending module when sending, and described coded data is separated into interleaving data and checking data according to leading coded data that sign indicating number will successively receive;
Second data processing module 321 is used for that scramble process module 322 is handled the initial data that the back obtains and does further processing, for example to initial data encode, conversion etc.In concrete the application, second data processing module 321 can be data sending device, data coding device, processing unit etc.
In the present embodiment, described correction module 323 can specifically comprise:
Order is adjusted submodule, is used for described checking data (for example CRC 16 checking datas) is reverted to the check code of normal sequence, to be used for the error code correction decoding.The form of check code in buffer memory of recovery order as shown in Figure 6.Buffer memory is made up of the buffer memory of 4 group of 16 bit, can store 4 16 bit check codes, and numbering is from 0 " to 3 ".The bit of each check code is arranged in the buffer memory according to normal form.Bit 0～the bit 15 of c0 check code is successively placed on buffer memory 0 "; Bit 0～the bit 15 of c1 check code is successively placed on buffer1 "; Bit 0～the bit 15 of c2 check code is successively placed on buffer memory 2 "; Bit 0～the bit 15 of c3 check code is successively placed on buffer memory 3 ".According to top order, placed the check code of all 16 bytes successively.
The error correction submodule is used to use the check code of above-mentioned recovery order to carry out error correction decoding: divided by generator polynomial g (x), the remainder that obtains is check results with the coded data that receives.If check results is 0, then showing does not have error code.If check results is not 0, show that then coded data has produced error code in transmission course.Check results and error code form compared carry out error correction.Be x for example when table 1 is depicted as multinomial
16+ x
12+ x
5+ 1 CRC 16 error correction error code forms, if the capable j columns of the i of check results and form illustrates i code word so according to consistent, the j bit has produced error code.By searching the error code form, can find out the error code that individual bit produces in the corresponding 128+16 Bit data fully, and revise.
| Bit | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 1 | ’0001’ | ’0002’ | ’0004’ | ’0008’ | ’0010’ | ’0020’ | ’0040’ | ’0080’ |
| 2 | ’0100’ | ’0200’ | ’0400’ | ’0800’ | ’1000’ | ’2000’ | ’4000’ | ’8000’ |
| 3 | ’1021’ | ’2042’ | ’4084’ | ’8108’ | ’1231’ | ’2462’ | ’48C4’ | ’9188’ |
| 4 | ’3331’ | ’6662’ | ’CCC4’ | ’89A9’ | ’0373’ | ’06E6’ | ’0DCC’ | ’1B98’ |
| 5 | ’3730’ | ’6E60’ | ’DCC0’ | ’A9A1’ | ’4363’ | ’86C6’ | ’1DAD’ | ’3B5A’ |
| 6 | ’76B4’ | ’ED68’ | ’CAF1’ | ’85C3’ | ’1BA7’ | ’374E’ | ’6E9C’ | ’DD38’ |
| 7 | ’AA51’ | ’4483’ | ’8906’ | ’022D’ | ’045A’ | ’08B4’ | ’1168’ | ’22D0’ |
| 8 | ’45A0’ | ’8B40’ | ’06A1’ | ’0D42’ | ’1A84’ | ’3508’ | ’6A10’ | ’D420’ |
| 9 | ’B861’ | ’60E3’ | ’C1C6’ | ’93AD’ | ’377B’ | ’6EF6’ | ’DDEC’ | ’ABF9’ |
| 10 | ’47D3’ | ’8FA6’ | ’0F6D’ | ’1EDA’ | ’3DB4’ | ’7B68’ | ’F6D0’ | ’FD81’ |
| 11 | ’EB23’ | ’C667’ | ’9CEF’ | ’29FF’ | ’53FE’ | ’A7FC’ | ’5FD9’ | ’BFB2’ |
| 12 | ’6F45’ | ’DE8A’ | ’AD35’ | ’4A4B’ | ’9496’ | ’390D’ | ’721A’ | ’E434’ |
| 13 | ’D849’ | ’A0B3’ | ’5147’ | ’A28E’ | ’553D’ | ’AA7A’ | ’44D5’ | ’89AA’ |
| 14 | ’0375’ | ’06EA’ | ’0DD4’ | ’1BA8’ | ’3750’ | ’6EA0’ | ’DD40’ | ’AAA1’ |
| 15 | ’4563’ | ’8AC6’ | ’05AD’ | ’0B5A’ | ’16B4’ | ’2D68’ | ’5AD0’ | ’B5A0’ |
| 16 | ’7B61’ | ’F6C2’ | ’FDA5’ | ’EB6B’ | ’C6F7’ | ’9DCF’ | ’2BBF’ | ’577E’ |
| 17 | ’AEFC’ | ’4DD9’ | ’9BB2’ | ’2745’ | ’4E8A’ | ’9D14’ | ’2A09’ | ’5412’ |
| 18 | ’A824’ | ’4069’ | ’80D2’ | ’1185’ | ’230A’ | ’4614’ | ’8C28’ | ’0871’ |
Table 1: (multinomial is x to the error code form
16+ x
12+ x
5+ 1 CRC 16 error correction error code forms)
Certainly, in the communication process of above-mentioned dispensing device 31 and receiving system 32, when the scrambler data are carried out interweaving encoding, also can use other deinterleaving method.For example code word the 0th～N bit is encoded to the 0th bit of the 0th～N interleaving data respectively, is the 1st bit of the 0th～N interleaving data the N+1～2N+1 bits of encoded of code word, up to the 127N+1～128N+1 bits of encoded with code word is the 127th bit of the 0th～N interleaving data, and wherein said N is greater than 1 and less than 128 integer.Correspondingly, interweaving encoding module 313 uses the buffer memory of N 128 bits to carry out interweaving encoding.
As shown in Figure 7, the flow chart for an embodiment of the code error correction method in the high speed transmission system of the present invention may further comprise the steps:
Step S71: dispensing device 31 is done scrambler with initial data and is handled generation scrambler data, for example uses scrambler multinomial x
58+ x
39+ 1.
Step S72: described scrambler data are carried out interweaving encoding and error correction coding, generate interleaving data and checking data.In this step, at first the scrambler data are carried out interweaving encoding, generate interleaving data; Generate check code according to interleaving data then, and check code is carried out interweaving encoding generation checking data.When the scrambler data are carried out interweaving encoding, be encoded to the 0th bit of the 0th～N interleaving data respectively, be the 1st bit of the 0th～N interleaving data with the synthetic code word of scrambler data set and with code word the 0th～N bit the N+1～2N+1 bits of encoded of code word, up to the 127N+1～128N+1 bits of encoded with code word is the 127th bit of the 0th～N interleaving data, and wherein said N is greater than 1 and less than 128 integer.Preferably, N is 4 or 4 integral multiple.
Step S73: lead sign indicating number and generate a coded data for interleaving data and checking data add, and described coded data is sent to receiving system.
In the present embodiment, among the above-mentioned step S72, use the buffer memory of 4 128 bits to carry out interweaving encoding, dispensing device 31 generates the check code of 4 16 bits according to the data in the buffer memory, and use the buffer memory of 4 16 bits that check code is carried out interweaving encoding, be combined into the checking data of 1 64 bit; And in step S73, interleaving data and checking data send to receiving system 32 after directly leading sign indicating number according to the interpolation of the order in the buffer memory.
Described method embodiment also comprises step:
Step S74: receiving system 32 uses to lead and after sign indicating number is finished the received code data synchronization described coded data is separated into interleaving data and checking data, and this synchronizing process has been removed leading sign indicating number and realizing the sequential organization of a plurality of coded datas in the coded data.
Step S75: checking data is reverted to the check code of normal sequence, and utilize described check code that described interleaving data is carried out error correction decoding.In this step, checking data is reverted to the same buffer memory that uses 4 16 bits of operation of normal sequence check code.And when error correction, at first the coded data that will handle through step S81 is divided by generator polynomial g (x), and the remainder that obtains is check results.If check results is 0, then showing does not have error code; If check results is not 0, show that then coded data has produced error code (check results and error code table can be compared and carry out error correction) in transmission course.
Step S76: the interleaving data behind the error correction decoding is done scramble process, revert to initial data.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (13)
1. the dispensing device of a code error correcting system is characterized in that, comprising:
The scrambler processing module is used for that initial data is carried out scrambler and handles, and generates the scrambler data;
The interweaving encoding module is used for that described scrambler data are carried out interweaving encoding and generates interleaving data, and described interleaving data is carried out error correction coding, behind the generation check code, described check code is carried out interweaving encoding generate checking data;
Lead sign indicating number and add module, be used for described interleaving data and the interpolation of described checking data are led sign indicating number, generate coded data.
2. dispensing device according to claim 1 is characterized in that, described interweaving encoding module comprises: the submodule that interweaves, and be used for the synthetic code word of scrambler data set, and use the buffer memory of N 128 bits that code word is carried out interweaving encoding, generate interleaving data.
3. dispensing device according to claim 2 is characterized in that, described interweaving encoding module also comprises: check code generates submodule, is used for interleaving data is generated the check code of 16 bits.
4. dispensing device according to claim 3 is characterized in that, described interweaving encoding module also comprises: checking data generates submodule, is used to use the buffer memory of 16 bits that each check code is carried out interweaving encoding, generates checking data.
5. according to each described dispensing device in the claim 2～4, it is characterized in that the number of described interleaving data is N, and N is 4 or 4 integral multiple, and greater than 1, less than 128.
6. the receiving system of a code error correcting system is characterized in that, comprising:
Lead a yard synchronization module, be used for that sign indicating number is led in the coded data use that receives and carry out synchronously, and described coded data is separated into interleaving data and checking data;
Correction module is used for described checking data is reverted to the check code of normal sequence, and uses described check code that described interleaving data is carried out error correction decoding;
The scramble process module is used for the interleaving data behind the described error correction decoding is done scramble process, reverts to initial data.
7. a code error correcting system is characterized in that, comprises dispensing device and receiving system;
Described dispensing device comprises:
The scrambler processing module is used for that initial data is carried out scrambler and handles, and generates the scrambler data;
The interweaving encoding module is used for that described scrambler data are carried out interweaving encoding and generates interleaving data, and described interleaving data is carried out error correction coding, behind the generation check code, described check code is carried out interweaving encoding generate checking data;
Lead sign indicating number and add module, be used for described interleaving data and the interpolation of described checking data are led sign indicating number, generate coded data;
Described receiver module comprises:
Lead a yard synchronization module, be used for that sign indicating number is led in the coded data use that receives and carry out synchronously, and described coded data is separated into interleaving data and checking data;
Correction module is used for described checking data is reverted to the check code of normal sequence, and uses described check code that described interleaving data is carried out error correction decoding;
The scramble process module is used for the data behind the described error correction decoding are done scramble process, reverts to initial data.
8. code error correcting system according to claim 7 is characterized in that, communicates by the 64b/66b coding between described dispensing device and receiving system.
9. a code error correction method is characterized in that, may further comprise the steps:
(a) dispensing device receives initial data, and described initial data is carried out scrambler handle, and generates the scrambler data;
(b) described scrambler data are carried out interweaving encoding, generate interleaving data, and carry out error correction coding, generate checking data according to described interleaving data;
(c) be that sign indicating number is led in the interpolation of described interleaving data and described checking data, generate coded data, send described coded data.
10. code error correction method according to claim 9 is characterized in that, and is further comprising the steps of:
(d) receiving system receives to use after the described coded data and leads sign indicating number described coded data is carried out synchronously, and described coded data is separated into interleaving data and checking data;
(e) checking data is reverted to the check code of normal sequence, and utilize described check code that described interleaving data is carried out error correction decoding;
(f) interleaving data behind the described error correction decoding is done scramble process, revert to initial data.
11. code error correction method according to claim 9 is characterized in that, described step (b) specifically comprises step:
(b1) described scrambler data are carried out interweaving encoding, generate interleaving data;
(b2) described interleaving data is carried out error correction coding, generate check code;
(b3) a plurality of check codes are carried out interweaving encoding, form a checking data.
12. code error correction method according to claim 11 is characterized in that, described step (b1) is specially:
Described interleaving data is N, with the synthetic code word of scrambler data set, and the buffer memory that uses 4 128 bits is encoded to code word the 0th～N bit respectively the 0th bit of the 0th～N interleaving data, is the 1st bit of the 0th～N interleaving data with the N+1～2N+1 bits of encoded of code word, up to the 127N+1～128N+1 bits of encoded with code word is the 127th bit of the 0th～N interleaving data, and wherein said N is greater than 1 and less than 128 integer.
13. code error correction method according to claim 12 is characterized in that, described N is 4 or 4 integral multiple, and greater than 1, less than 128.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101686104B (en) * | 2008-09-22 | 2013-11-06 | 华为技术有限公司 | Coding and decoding method for forward error correction, device and system thereof |
| CN109873777A (en) * | 2017-12-01 | 2019-06-11 | 华为技术有限公司 | A kind of error correction method and error correction device |
| CN110391875A (en) * | 2018-04-23 | 2019-10-29 | 华为技术有限公司 | A kind of error correction method and error correction device |
| CN112491506A (en) * | 2020-09-17 | 2021-03-12 | 天津瑞发科半导体技术有限公司 | PAM-M fault-tolerant transmission system and method |
| CN115037414A (en) * | 2022-05-31 | 2022-09-09 | 江苏屹信航天科技有限公司 | Error correction decoding method, device and terminal based on CRC |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101686104B (en) * | 2008-09-22 | 2013-11-06 | 华为技术有限公司 | Coding and decoding method for forward error correction, device and system thereof |
| CN109873777A (en) * | 2017-12-01 | 2019-06-11 | 华为技术有限公司 | A kind of error correction method and error correction device |
| CN109873777B (en) * | 2017-12-01 | 2021-12-17 | 华为技术有限公司 | Error correction method and error correction device |
| US11218246B2 (en) | 2017-12-01 | 2022-01-04 | Huawei Technologies Co., Ltd. | Error correction method and error correction apparatus |
| CN110391875A (en) * | 2018-04-23 | 2019-10-29 | 华为技术有限公司 | A kind of error correction method and error correction device |
| CN110391875B (en) * | 2018-04-23 | 2020-10-09 | 华为技术有限公司 | Error correction method and error correction device |
| US11316717B2 (en) | 2018-04-23 | 2022-04-26 | Huawei Technologies Co., Ltd. | Error correction method and apparatus |
| CN112491506A (en) * | 2020-09-17 | 2021-03-12 | 天津瑞发科半导体技术有限公司 | PAM-M fault-tolerant transmission system and method |
| CN112491506B (en) * | 2020-09-17 | 2022-11-08 | 天津瑞发科半导体技术有限公司 | PAM-M fault-tolerant transmission system and method |
| CN115037414A (en) * | 2022-05-31 | 2022-09-09 | 江苏屹信航天科技有限公司 | Error correction decoding method, device and terminal based on CRC |
| CN115037414B (en) * | 2022-05-31 | 2023-12-22 | 江苏屹信航天科技有限公司 | CRC-based error correction decoding method, device and terminal |
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