WO2011054273A1

WO2011054273A1 - Device and method for multi-cell time slot multiplexing

Info

Publication number: WO2011054273A1
Application number: PCT/CN2010/078258
Authority: WO
Inventors: 欧阳帆; 廖智勇; 孙明施; 曾敏
Original assignee: 中兴通讯股份有限公司
Priority date: 2009-11-06
Filing date: 2010-10-29
Publication date: 2011-05-12
Also published as: CN101741720B; CN101741720A

Abstract

The present invention provides a device and method for multi-cell time slot multiplexing. The device includes an input storage module for buffer-storing and outputting input cells, a gating network module for strobe-outputting the cells from the input storage module, an output storage module for buffer-storing the cells from the gating network module and outputting the cells in parallel, and a control logic module for sending a reading signal to the input storage module when it is determined that the cells are input into the input storage module, controlling the strobe output according to the signal with scheduled beat and controlling the output storage module to output the input data in parallel when determining completion of the strobe output. Through the scheme of the present invention, it is able to receive the cells input simultaneously or randomly and output the cells in parallel, and through utilizing multiple multiplexers and storage sub-modules to replace a single large multiplexer, the scale of the multiplexers and the design difficulty of the circuit are reduced.

Description

TECHNICAL FIELD The present invention relates to the field of communications, and in particular, to an apparatus and method for multiplexing multi-channel cell time slots. Background Art In modern communication networks, switching and processing based on cells (fixed-length packet data) has become more and more popular. The communication circuit using the cell as the basic data unit has the characteristics of high transmission efficiency and simple processing. The shared storage is a common structure of the switching chip, and multiple internal input and output ports share one storage space, which has the advantage of high memory utilization. The existing patent documents include: Chinese Patent Application No. 200520078701.3 "Synchronous Digital Signal Demultiplexing Circuit". In this patent, the time slot multiplexing of the multiplexed cells is performed by performing serial-to-parallel conversion and then strobing through the multiplexer. The method has the following disadvantages: 1. In the case that the input and output clocks are synchronized and the signals on the input link are continuous, the method requires that the cell arrival times on the input links are staggered from each other, and the letters on the links are Metas cannot be reached at the same time, limiting the flexibility of the input.

2. In the case of a large cell length, the circuit scale and delay of the multiplexer will become very large, increasing the complexity of the design. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide an apparatus and method for multi-channel cell time slot multiplexing, which can receive cells input simultaneously or randomly and output them in parallel, and use multiple multiplexers and The memory sub-module replaces a single large multiplexer, reducing the size of the multiplexer and the difficulty of circuit design. In order to solve the above technical problem, according to an aspect of the present invention, an apparatus for multiplexing multiple channel time slots is provided, including: an input storage module, configured to buffer and output an input cell; a strobe network module for strobing and outputting cells from the input storage module; an output storage module for buffering cells from the strobe network module and outputting cells in parallel; and a control logic module for Sending a readout signal to the input storage module when determining that a cell is input to the input storage module, and for controlling the gate output with a predetermined beat signal, and for controlling the output storage module to input data when determining that the gate output has been completed Parallel output. The input storage module includes a plurality of first-in first-out FIFO sub-modules for buffering the input multi-channel cells, wherein when there is a cell input, the FIFO sub-module generates a non-empty status signal. The control logic module includes: an internal control signal generating module configured to control the gate network module with a predetermined beat signal; and an output control signal generating module configured to generate a control output storage according to the non-empty state signal under the control of the predetermined beat signal The module will input control signals for parallel output of data. The strobe network module includes a plurality of multiplexers for strobing the input cells and outputting them to the output storage module under the control of a predetermined beat signal of the control logic module. The output storage module includes a plurality of random access memory RAMs for buffering the cells output by the strobe network module strobe, and outputting the cells in parallel under the control of the control signal of the control logic module. According to another aspect of the present invention, a method for multiplexing multi-channel cell slot multiplexing is provided, comprising the steps of: inputting a memory module to receive a cell and outputting a non-empty state signal; and the control logic module detects After the non-empty state signal, the input storage module outputs the cell; under the control of the control logic module, the multiplexer inside the strobe network module is sequentially turned on, so that the cells in the input storage module are separately strobed and output according to the cyclic manner. To each sub-module of the output storage module; and after determining that the strobe output of the cell has been completed, each sub-module outputs the cells in parallel under the control of the control logic module. The control logic module controls the input storage module output cell after detecting the non-empty state signal, and includes: outputting the cached cell in a stepwise manner. Wherein, the method further comprises the control logic module generating an output control signal, and determining whether the cells output in parallel are valid according to the output control signal. The input storage module includes a plurality of FIFO modules, and outputting the buffered cells in a stepwise manner includes: for the cells in the FIFO, in a cycle period, simultaneously FIFO#0 to FIFO#k The address numbers in the are n, nl, n-2 nk and the address number is The data in the address of the non-negative integer is sent to the strobe network, n>j+l, then cyclically changes from 0, where k is the number of the FIFO, j+1 is the depth of the FIFO, and n is a positive integer. Wherein, determining that the strobe output of the cell has been completed comprises: determining that the strobe output has been completed according to the length of the cell and the frequency of the control signal of the control logic module. The invention utilizes the input storage for buffering, the strobe network and the output storage to complete the time slot multiplexing of the multi-channel cells, and can process the time slot multiplexing of the multi-channel cells in any relative relationship in real time, thereby improving the processing flexibility. . At the same time, the use of multiple multiplexers and memory sub-modules instead of a single large multiplexer reduces the size of the multiplexer and the difficulty of circuit design. The present invention is suitable for cells of various lengths, and only changes the depth of the FIFO and the number of multiplexers and storage sub-modules on the circuit, improving design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a multi-channel cell slot multiplexing apparatus according to the present invention; FIG. 2 is a schematic diagram showing the structure of an input memory in accordance with the present invention; 4 is a schematic structural view of an internal structure of an output memory according to the present invention; FIG. 5 is a schematic structural view of the internal control logic of the present invention; FIG. 6 is a schematic diagram of a data transmission method according to the present invention; A flowchart of a data processing method of the present invention. DETAILED DESCRIPTION OF THE INVENTION In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. The multi-way time slot multiplexing device of the present invention comprises the following modules: Input storage, comprising a thousand first-in first-out sub-modules (FIFOs) for buffering input data on each link, and at a certain Under the timing control, the internal data is read out to the strobe network; the strobe network includes a thousand multiplexers (mux) for reading the data in the input storage and transmitting the data to the output storage module; Output storage, which includes thousands of storage sub-modules, can be composed of ram or registers. It is configured to receive data input by a corresponding multiplexer in the strobe network, and output the multiplexed data after a certain timing; control logic for providing control information of the input storage module, the strobe network, and the output storage module Wherein, the flow of data is: input port, input storage, strobe network, output storage, output port. The method for multiplexing multiple time slots according to the present invention: Step A: The input storage module receives cells from an input port. Step B: Input the FIFO in the storage module to buffer the data, and give a FIFO non-empty indication. In step C, the control logic polls the data in the FIFO of 0 to k. If the FIFO is non-empty, the internal data is read, and if it is empty, the data is not read. In step D, the multiplexers in the strobe network are sequentially opened in the order of 0 to j, and each multiplexer sends the data in the FIFOs 0 to k to the corresponding output storage submodules in a cyclic manner. Step E: The storage sub-module in the output storage module temporarily stores the data, and under the control of the control logic counter, cyclically outputs the data in the addresses 0 to j of all the storage sub-modules, and completes the information of the plurality of channel cells. Time slot multiplexing. The implementation of the technical solution is further described in detail below with reference to the accompanying drawings. As shown in FIG. 1, the device for multiplexing a cell of the present invention includes: The input storage 101 internally includes a plurality of FIFOs, buffers the input cells, and outputs the data in the FIFO to the strobe network under a certain timing control. The strobe network 102 internally includes thousands of multiplexers mux, and strobes the data read by the input memory 101 under a certain timing control. The output memory 103 internally includes a plurality of RAMs and registers, and buffers the input data. After the output time comes, the data in the time slot multiplexing in the RAM is output. The control logic 104 outputs a beat control signal; at the same time, the FIFO state in the input memory 101 is sampled to generate an output control signal. As shown in FIG. 2, the input memory 101 is internally composed of a plurality of FIFOs each having a depth of one cell, and the input terminal is connected to the input of the entire device. The FIFO sets the non-empty indication signal after receiving data for input. When the data is read out from the FIFO, the control logic sequentially inquires the non-empty indication signal of the FIFO in the order of 0 to k through the beat control signal, and supplies the non-empty indication signal to the control logic 104. As shown in FIG. 3, the strobe network 102 is internally composed of thousands of mux, and the number of inputs of each mux is the same as the number of FIFOs in the input memory 101, and the number of mux is the same as the FIFO depth in the input memory 101. When controlling the mux, the control logic sequentially starts the mux in the order of 0~j through the beat control signal. Each mux sequentially strobes the input signal in the order of 0 to K after startup. As shown in FIG. 4, the output memory 103 is composed of a plurality of RAMs and registers, and the input of each RAM is connected to the strobe network, and the outputs of all the RAMs are bound together to form a device for multiplexing cells. Output. The total number of RAMs is the same as the length of the cells, and the depth of the RAM is the same as the number of FIFOs in the input memory 101. After accepting the data of the strobe network, the 0#~j#RAM is outputted by the control logic together with the internal data after a certain time, and the time slot multiplexing is completed. As shown in FIG. 5, control logic 104 is comprised of an internal control signal generation 501 and an output control signal generation 502 module. The internal control signal generation module includes a counter and some control circuits for generating a beat control signal, which is output to the input storage 101, the strobe network 102, and the output storage 103, and controls the three modules. The output control signal generation module 502 performs gate output of the FIFO non-empty state in the input memory 101 under the control of the beat signal generated by the internal control signal generation 501 to generate an output control signal. The data transmission method of the multiplex cell time slot multiplexing device of the present invention is as shown in FIG. 6. After the start time slot 0 after the power-on reset, the data at the 0th address on the FIFO #0 is read out. Stored in address 0 on RAM #0; at time slot 1, ^! The first data on the first address on FIFO #0 and the zero address on FIFO #1 are read and stored in address No. 0 on RAM #1 and address No. 1 on RAM #0. After the time slot j, data will be read out in each FIFO every clock cycle, where the data in the nth address of FIFO#m will be stored in the mth address in RAM#n ( n < j ) in. As shown in FIG. 7, for the cell data entering the multiplex cell slot multiplexing apparatus of the present invention, the processing flow is as follows: Step 1, the FIFO in the input storage 101 receives the input cell data. In step 2, the FIFO in the input memory 101 buffers the cell and waits for the read signal. Step 3: The FIFO in the input memory 101 receives the read signal and outputs the data to the strobe network 102. Step 4: The multiplexer in the strobe network strobes the received signal under the control of the beat signal of the control logic 104, and sends it to the output storage 103. Step 5: The output storage 103 receives the data in the strobe network and performs caching. Step 6: Determine the output time, and if it has been reached, output the data in the storage 103 for output. In step 7, the cells after the time slot multiplexing is completed are output. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A device for multiplexing a plurality of cell time slots, comprising:

An input storage module, configured to cache and output the input cells;

a strobe network module, configured to perform strobing output of the cell from the input storage module;

An output storage module, configured to cache the cells from the gating network module and output the cells in parallel;

a control logic module, configured to send a readout signal to the input storage module when determining that a cell is input to the input storage module, and to control the gating output with a predetermined beat signal, and for determining the When the strobe output is completed, the output storage module is controlled to output the input data in parallel.

2. The apparatus according to claim 1, wherein the input storage module comprises a plurality of first-in first-out FIFO sub-modules for buffering input multi-channel cells.

Wherein, when there is a cell input, the FIFO sub-module generates a non-empty status signal.

3. The apparatus according to claim 2, wherein the control logic module comprises: an internal control signal generating module, configured to control the strobe network module with the predetermined beat signal;

And an output control signal generating module, configured to generate, according to the non-empty state signal, a control signal that controls the output storage module to output the input data in parallel under the control of the predetermined beat signal.

4. The apparatus according to claim 3, wherein the strobe network module comprises a plurality of multiplexers for inputting the input under control of the predetermined beat signal of the control logic module The cell strobes the output and sends it to the output storage module.

The device according to claim 1, wherein the output storage module comprises a plurality of random access memory RAMs for buffering the cells of the gating network module strobe output, and in the controlling The cells are output in parallel under the control of the control signal of the logic module.

6. A method for multiplexing multiplexed cell time slots, characterized in that it comprises the following steps:

The input storage module receives the cell and outputs a non-empty status signal;

The control logic module controls the input storage module to output the cell after detecting the non-empty status signal;

Under the control of the control logic module, the multiplexer inside the strobe network module is sequentially turned on to strobe and output the cells in the input storage module to the sub-modules of the output storage module in a round-robin manner; as well as

After determining that the strobe output of the cell has been completed, the sub-modules output the cell in parallel under the control of the control logic module.

The method according to claim 6, wherein the controlling the logic module to control the output storage module to output the cell after detecting the non-empty state signal comprises:

The buffered cells are output in a stepwise manner.

8. The method of claim 6 wherein the method further comprises the control logic module generating an output control signal and determining whether the cell output in parallel is valid based on the output control signal.

The method according to claim 7, wherein the input storage module comprises a plurality of FIFO modules, and outputting the cached cells in a stepwise manner comprises: In the ticks, the data in the addresses of the FIFO#0 to FIFO#k are respectively n, nl, n-2 nk and the address number is a non-negative integer, and the data is sent to the strobe network. n > j+1 , then cyclically changes from 0, where k is the number of the FIFO, j+1 is the depth of the FIFO, and n is a positive integer.

10. The method of claim 6, wherein the determining that the strobe output of the cell has been completed comprises:

The strobe output is determined to be complete based on the length of the cell and the frequency of the control signal of the control logic module.