CN117880437A - Frame synchronization platform based on FPGA airborne display system low-power consumption - Google Patents

Abstract

The application provides a frame synchronization platform based on low power consumption of an FPGA (field programmable gate array) airborne display system, belongs to the technical field of video image processing, and particularly relates to a hardware architecture taking an FPGA as a core, utilizes abundant logic resources and parallel data processing capacity of the FPGA, combines the characteristics of video synchronization signals, divides an off-chip single-chip frame memory into three areas, acquires the synchronization signals through a fast clock domain, realizes one-line writing and one-line reading of the off-chip frame memory in one-line time, realizes three-frame memory round-robin read-write operation of the single-chip frame memory, can be applied to an airborne display, and compared with a traditional three-memory frame synchronization mode, can fully utilize a frame memory with maximum efficiency of line-field synchronization characteristics and improve the read-write bandwidth of the frame memory, and is beneficial to development of the airborne video display hardware platform towards the low cost and low power consumption direction while meeting the video frame synchronization function of the airborne display system.

Description

Frame synchronization platform based on FPGA airborne display system low-power consumption

Technical Field

The application relates to the field of airborne display, in particular to a frame synchronization platform based on low power consumption of an FPGA (field programmable gate array) airborne display system.

Background

The current mainstream airborne display all needs to process external video, and the external video is generally required to be processed after being synchronized, and the current mainstream implementation mode of external video synchronization is processed in a three-frame polling mode, and the common hardware scheme is a scheme that an FPGA (field programmable gate array) is externally hung with three off-chip memories or video synchronization is realized by opening up three frame caches in a DDR (double data rate) memory. Under the hardware architecture of the traditional external three-piece physical frame memory, the single-chip independent frame memory is adopted, and each frame memory has only one group of address data buses and can only be read or written at the same time, so that the waste of read-write data bandwidth can be caused under the hardware architecture of the external three-piece physical frame memory. Under the condition of using the DDR memory to carry out frame synchronous cache, if the read-write operation of the DDR memory is required to be flexibly controlled, certain requirements are required on the design capability of the DDR controller.

Disclosure of Invention

In view of this, the application provides a frame synchronization platform based on FPGA airborne display system low-power consumption, has solved the problem in the prior art, improves the data throughput of off-chip frame memory, practices thrift off-chip frame memory resource, can reduce hardware cost and display system power consumption to a certain extent.

The frame synchronization platform based on the FPGA airborne display system and with low power consumption adopts the following technical scheme:

the frame synchronization platform based on the low power consumption of the FPGA on-board display system comprises an FPGA and an off-chip frame memory hung on the FPGA, wherein the address of the off-chip frame memory is divided into a plurality of sections, and each section of address space is respectively used as a piece of frame memory;

in the process of receiving the external video, the FPGA performs bit width conversion and clock domain conversion on the received external video data and outputs the external video data to an off-chip frame memory, and one-line writing and one-line reading of the off-chip frame memory are realized in one-line video time division; and the FPGA carries out synchronous signal reconstruction on the read frame video to generate actual output video time sequence screen-sending display.

Optionally, the FPGA is provided with a FIFO memory 1, a FIFO memory 2, a frame memory control module frame_ctrl and a timing reconstruction module rebuild_timing; wherein, english of FIFO is called First in First out, chinese represents first-in first-out.

The write data bit width of the FIFO memory 1 is n, the read data bit width of the FIFO memory 1 is a, the unit of the data bit width is bit, the external video data is directly written into the FIFO memory 1 according to the line energy input synchronously, the number of effective pixel points of one line of video of the external video is m, the FIFO memory 1 carries out bit width conversion and clock domain conversion on the input external video data and then outputs the external video data, and after conversion, one line of external video data input into the FIFO memory 1 is read by using b clock cycles, wherein a multiplied by b=n multiplied by m, a is larger than n, and m is larger than b;

the frame memory control module framer_ctrl is used for generating read enabling of the FIFO memory 1 and write enabling of the FIFO memory 2, the timing reconstruction module rebuild_timing generates a screen sending timing through a local clock domain, and synchronizes a line synchronizing signal of the screen sending timing by using a second clock, the pixel clock frequency of the screen sending timing is equal to the frequency of an external video pixel clock, and the frequency of the second clock is greater than the frequency of the external video pixel clock; when the falling edge of the write enabling of the FIFO memory 1 arrives, waiting for the rising edge of the line synchronization signal under the second clock domain to arrive, starting counting two sections of enabling signals, wherein the two sections of enabling signals are generated in the same line, the two sections of enabling signals are b clock cycles, the former section of enabling signal is used for reading one line of complete data from the FIFO memory 1 and writing one line of complete video data into one frame memory of the off-chip frame memory, and the latter section of enabling signal is used for reading one line of complete video data from the other frame memory of the off-chip frame memory and writing one line of complete video data into the FIFO memory 2;

the write data bit width of the FIFO memory 2 is a, the read data bit width of the FIFO memory 2 is n, the FIFO memory 2 performs bit width conversion and clock domain conversion on the input video data and outputs the video data, and one line of video data input into the FIFO memory 2 is converted and then is read by m clock cycles.

Optionally, the frame memory control module frame_ctrl generates a write enable signal of the FIFO memory 2, writes a frame of video into the FIFO memory 2 line by line under line synchronization of the second clock domain, and the local clock domain generates a screen-delivering time sequence to read video data in the FIFO memory 2, so as to realize clock domain conversion from the second clock domain to the screen-delivering time sequence.

Optionally, the read enable of the FIFO memory 2 is one line later than the write enable of the FIFO memory 2, and the line-field synchronizing signal of the screen sending timing sequence generated by the local clock domain is delayed according to the read enable signal and the valid data of the FIFO memory 2, and then the screen sending display is performed.

Optionally, the frequency of the pixel clock of the screen sending time sequence is 50MHz, and the frequency of the second clock is 80MHz.

Optionally, the addresses of the off-chip frame memory are divided into three sections, namely an F0 frame memory, an F1 frame memory and an F2 frame memory;

the former section of enabling is used for reading one line of complete data from the FIFO memory 1 and writing the complete data into the F0 frame memory, and the latter section of enabling is used for reading one line of complete video data from the F2 frame memory and writing the complete video data into the FIFO memory 2;

when the frame data of the F0 frame memory is written and the frame data of the F2 frame memory is also read, the next frame is written line by line from the F1 frame memory, and simultaneously, the line by line reading is started from the F0 frame memory, and when the frame data of the F1 frame memory is written and the frame data of the F0 frame memory is read, the line by line writing is started to the F2 frame memory, and simultaneously, the line by line reading is performed to the F1 frame memory, and three frame memories are continuously polled and read.

Optionally, the read data bit width a of FIFO memory 1 is identical to the maximum data bit width of the off-chip frame memory.

In summary, the present application includes the following beneficial technical effects:

according to the method and the device, the service efficiency and the read-write bandwidth of the off-chip frame memory are effectively improved, the off-chip single-chip frame memory is divided into three areas, and synchronous signals are acquired through a fast clock domain, so that data reading and data writing operation of one row of the frame memory is completed in one row of time, the three-frame memory round robin read-write operation of the single-chip frame memory is realized, the data throughput of the frame memory is improved, off-chip memory resources are saved, the number of the off-chip memory is saved, the hardware cost and the power consumption of a display system can be reduced to a certain extent, the data read-write efficiency of the single-chip frame memory is improved, the circuit scale and the power consumption are effectively reduced, the miniaturization and the low power consumption of an airborne display system can be effectively promoted, and convenience is provided for the flexibility of video processing of the display system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a frame synchronization platform with low power consumption based on an FPGA (field programmable gate array) airborne display system;

fig. 2 is a waveform diagram of a frame buffer line read-write operation simultaneously implemented in a line of video time in the present application.

Detailed Description

Embodiments of the present application are described in detail below with reference to the accompanying drawings.

Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The embodiment of the application provides a frame synchronization platform based on low power consumption of an FPGA (field programmable gate array) airborne display system.

As shown in fig. 1 and fig. 2, the frame synchronization platform based on the low power consumption of the FPGA airborne display system is characterized by comprising an FPGA and an off-chip frame memory externally hung on the FPGA, wherein the addresses of the off-chip frame memory are divided into a plurality of sections, and each section of address space is respectively stored as a piece of frame.

In the process of receiving the external video, the FPGA performs bit width conversion and clock domain conversion on the received external video data and outputs the external video data to an off-chip frame memory, and one-line writing and one-line reading of the off-chip frame memory are realized in one-line video time division; and the FPGA carries out synchronous signal reconstruction on the read frame video to generate actual output video time sequence screen-sending display.

The FPGA is provided with a FIFO memory 1, a FIFO memory 2, a frame memory control module framer_ctrl and a time sequence reconstruction module rebuild_timing;

the write data bit width of the FIFO memory 1 is n, the read data bit width of the FIFO memory 1 is a, the unit of the data bit width is bit, the external video data is directly written into the FIFO memory 1 according to the line energy input synchronously, the number of effective pixel points of one line of video of the external video is m, the FIFO memory 1 carries out bit width conversion and clock domain conversion on the input external video data and then outputs the external video data, and after conversion, one line of external video data input into the FIFO memory 1 is read by using b clock cycles, wherein a multiplied by b=n multiplied by m, a is larger than n, and m is larger than b; the application is illustrated with n equal to 18, a equal to 36, m equal to 1024, b equal to 512. The FIFO memory 1 converts 18bit data into 36bit data, and then writes the 18bit data into the FIFO memory 1 line by line according to the video effective data enabling, wherein the output data bit width of the FIFO memory 1 is set to 36bit, thereby realizing the function of converting 18bit into 36 bit. In other embodiments, the read data bit width of FIFO memory 1 may be adjusted depending on the off-chip memory actually used.

The frame memory control module framer_ctrl is used for generating read enabling of the FIFO memory 1 and write enabling of the FIFO memory 2, the timing reconstruction module rebuild_timing generates a screen sending timing through a local clock domain, and synchronizes a line synchronizing signal of the screen sending timing by using a second clock, the pixel clock frequency of the screen sending timing is equal to the frequency of an external video pixel clock, and the frequency of the second clock is greater than the frequency of the external video pixel clock; when the falling edge of the write enable (de signal of the external video) of the FIFO memory 1 arrives (indicating that a line of data has been written into the FIFO memory 1), and when the rising edge of the line synchronization signal under the second clock domain arrives, two segments of enable signals are counted, both of which are generated in the same line, both of which are 512 clock cycles (video resolution is 1024×768@50hz, and the video resolution and bit width conversion ratio are adjusted as required), the former segment of enable is used for reading a line of complete data from the FIFO memory 1 and writing one of the frame memories of the external frame memory, and the latter segment of enable is used for reading a line of complete video data from the other frame memory of the external frame memory and writing the same into the FIFO memory 2. The need to sample the line synchronization with a fast second clock domain in this application is to ensure that the fast clock domain can count the enable signals of two lines of valid data in a line time (one line of off-chip frame memory ).

The write data bit width of the FIFO memory 2 is 18 bits, the read data bit width of the FIFO memory 2 is 38 bits, the FIFO memory 2 performs bit width conversion and clock domain conversion on the input video data and outputs the video data, and one line of video data input into the FIFO memory 2 is converted and then is read by 1024 clock cycles.

The frame memory control module framer_ctrl generates a write enable signal of the FIFO memory 2, writes a frame of video into the FIFO memory 2 line by line under the line synchronization of the second clock domain, and the local clock domain generates the screen sending time sequence to read video data in the FIFO memory 2, so as to realize clock domain conversion from the second clock domain clk2 to the screen sending time sequence.

Because the data read from the off-chip frame memory are all generated under the synchronization of the local clock line, the interval period of the read enabling and the write enabling of the FIFO memory 2 is the same, the read enabling of the FIFO memory 2 is one line later than the write enabling signal of the FIFO memory 2, and the abnormal conditions of data overflow and read empty of the FIFO memory 2 in one frame of effective video can be avoided, so that the video data are ensured to be continuous and correct, and the line and field synchronizing signals of the screen sending time sequence generated by the local clock domain are delayed according to the read enabling signal and the effective data of the FIFO memory 2 and then displayed in a screen sending mode.

According to the method and the device, the service efficiency and the read-write bandwidth of the off-chip frame memory are effectively improved, the single-frame memory can be used in a partitioned mode through bit width conversion, and data reading and data writing operations on one row of the frame memory are completed in one row of time through conversion of data processing rate, so that the data throughput of the frame memory is improved, off-chip memory resources are saved, and hardware cost and display system power consumption can be reduced to a certain extent.

The frequency of the pixel clock local_clk of the screen feeding timing is 50MHz, and the frequency of the second clock clk2 is 80MHz.

The addresses of the off-chip frame memory are divided into three sections, namely an F0 frame memory, an F1 frame memory and an F2 frame memory;

the former section of enabling is used for reading one line of complete data from the FIFO memory 1 and writing the complete data into the F0 frame memory, and the latter section of enabling is used for reading one line of complete video data from the F2 frame memory and writing the complete video data into the FIFO memory 2;

when the frame data of the F0 frame memory is written and the frame data of the F2 frame memory is also read, the next frame is written line by line from the F1 frame memory, and simultaneously, the line by line reading is started from the F0 frame memory, and when the frame data of the F1 frame memory is written and the frame data of the F0 frame memory is read, the line by line writing is started to the F2 frame memory, and simultaneously, the line by line reading is performed to the F1 frame memory, and three frame memories are continuously polled and read.

The read data bit width a of FIFO memory 1 coincides with the maximum data bit width of the off-chip frame memory. Therefore, the storage space of the off-chip frame memory can be fully used, and the waste of storage resources of the off-chip frame memory is avoided.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (7)

1. The frame synchronization platform based on the low power consumption of the FPGA airborne display system is characterized by comprising an FPGA and an off-chip frame memory hung on the FPGA, wherein the address of the off-chip frame memory is divided into a plurality of sections, and each section of address space is respectively used as a piece of frame memory;

in the process of receiving the external video, the FPGA performs bit width conversion and clock domain conversion on the received external video data and outputs the external video data to an off-chip frame memory, and one-line writing and one-line reading of the off-chip frame memory are realized in one-line video time division; and the FPGA carries out synchronous signal reconstruction on the read frame video to generate actual output video time sequence screen-sending display.

2. The frame synchronization platform based on the low power consumption of the FPGA airborne display system according to claim 1, wherein the FPGA is provided with a FIFO memory 1, a FIFO memory 2, a frame control module frame_ctrl and a timing reconstruction module rebuild_timing;

the write data bit width of the FIFO memory 1 is n, the read data bit width of the FIFO memory 1 is a, the unit of the data bit width is bit, the external video data is directly written into the FIFO memory 1 according to the line energy input synchronously, the number of effective pixel points of one line of video of the external video is m, the FIFO memory 1 carries out bit width conversion and clock domain conversion on the input external video data and then outputs the external video data, and after conversion, one line of external video data input into the FIFO memory 1 is read by using b clock cycles, wherein a multiplied by b=n multiplied by m, a is larger than n, and m is larger than b;

the frame memory control module framer_ctrl is used for generating read enabling of the FIFO memory 1 and write enabling of the FIFO memory 2, the timing reconstruction module rebuild_timing generates a screen sending timing through a local clock domain, and synchronizes a line synchronizing signal of the screen sending timing by using a second clock, the pixel clock frequency of the screen sending timing is equal to the frequency of an external video pixel clock, and the frequency of the second clock is greater than the frequency of the external video pixel clock; when the falling edge of the write enabling of the FIFO memory 1 arrives, waiting for the rising edge of the line synchronization signal under the second clock domain to arrive, starting counting two sections of enabling signals, wherein the two sections of enabling signals are generated in the same line, the two sections of enabling signals are b clock cycles, the former section of enabling signal is used for reading one line of complete data from the FIFO memory 1 and writing one line of complete video data into one frame memory of the off-chip frame memory, and the latter section of enabling signal is used for reading one line of complete video data from the other frame memory of the off-chip frame memory and writing one line of complete video data into the FIFO memory 2;

the write data bit width of the FIFO memory 2 is a, the read data bit width of the FIFO memory 2 is n, the FIFO memory 2 performs bit width conversion and clock domain conversion on the input video data and outputs the video data, and one line of video data input into the FIFO memory 2 is converted and then is read by m clock cycles.

3. The frame synchronization platform based on low power consumption of the FPGA airborne display system according to claim 2, wherein the frame memory control module framer_ctrl generates a write enable signal of the FIFO memory 2, writes a frame of video into the FIFO memory 2 line by line under line synchronization of the second clock domain, and the local clock domain generates a screen-delivering time sequence to read video data in the FIFO memory 2, so as to implement clock domain conversion from the second clock domain to the screen-delivering time sequence.

4. The frame synchronization platform based on low power consumption of FPGA on-board display system according to claim 3, wherein the read enable of FIFO memory 2 is one line later than the write enable of FIFO memory 2, and the line-field synchronization signal of the screen-delivering timing sequence generated by the local clock domain is delayed according to the read enable signal and the valid data of FIFO memory 2, and then displayed on screen.

5. The frame synchronization platform based on low power consumption of FPGA on-board display system of claim 3, wherein the frequency of the pixel clock of the screen timing is 50MHz and the frequency of the second clock is 80MHz.

6. The frame synchronization platform based on the low power consumption of the FPGA on-board display system according to claim 2, wherein the address of the off-chip frame memory is divided into three sections, namely an F0 frame memory, an F1 frame memory and an F2 frame memory;

the former section of enabling is used for reading one line of complete data from the FIFO memory 1 and writing the complete data into the F0 frame memory, and the latter section of enabling is used for reading one line of complete video data from the F2 frame memory and writing the complete video data into the FIFO memory 2;

when the frame data of the F0 frame memory is written and the frame data of the F2 frame memory is also read, the next frame is written line by line from the F1 frame memory, and simultaneously, the line by line reading is started from the F0 frame memory, and when the frame data of the F1 frame memory is written and the frame data of the F0 frame memory is read, the line by line writing is started to the F2 frame memory, and simultaneously, the line by line reading is performed to the F1 frame memory, and three frame memories are continuously polled and read.

7. The frame synchronization platform based on low power consumption of an FPGA on-board display system according to claim 2, wherein the read data bit width a of the FIFO memory 1 is identical to the maximum data bit width of the off-chip frame memory.