CN103731224A - Device and method for supporting multi-length-variable-cell time slot multiplexing - Google Patents
Device and method for supporting multi-length-variable-cell time slot multiplexing Download PDFInfo
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- CN103731224A CN103731224A CN201210384420.5A CN201210384420A CN103731224A CN 103731224 A CN103731224 A CN 103731224A CN 201210384420 A CN201210384420 A CN 201210384420A CN 103731224 A CN103731224 A CN 103731224A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing
Abstract
The invention discloses a device and method for supporting multi-length-variable-cell time slot multiplexing. The method includes the steps that input multiple length-variable cells are respectively cached through an input storage module, the cached length-variable cell data are output to a gating network module according to a first sequential control command sent by a control logic module, the gating network module comprising a plurality of parallel multiplexers carries out gating output on the length-variable cell data read out from the input storage module according to a second sequential control command sent by the control logic module, the length-variable cell data coming from the gating network module are cached through an output storage module, and the length-variable cell data after time-slot multiplexing are output according to a third sequential control command sent by the control logic module. According to the device and method, time slot multiplexing of the multiple length-variable cells under any relative relation can be processed in real time, use of the bandwidth of each input port is guaranteed, and the processing flexibility is improved.
Description
Technical field
The present invention relates to communication technical field, in particular to a kind of apparatus and method of supporting the elongated cell time slot multiplexing of multichannel, particularly, it can be applicable to the input interface section of router or switch.
Background technology
In modern communication network, exchange and processing mode based on cell (fixed length grouped data) become more and more general, this be due to the communicating circuit that adopts cell as primitive have efficiency of transmission high, process simple feature, wherein, based on sharing storage, it is a kind of structure that exchange chip is conventional, a plurality of input/output ports of its inside share a slice memory space, have the advantage that memory utilance is high.
Number of patent application is that 200520078701.3 Chinese patent application discloses a kind of synchronous digital signal multiplexing-decomposition circuit, in this patent scheme, what the timeslot multiplex of multichannel cell adopted is first go here and there and change, by multiplexer, carry out the method for gating, the method has following shortcoming again:
1, the in the situation that on input and output clock synchronous and input link, signal being continuous, the method requires the cell on each input link to reach the time to stagger each other, and the cell on each link can not arrive simultaneously, has limited the flexibility of input.
2, in the situation that cell length is larger, the circuit scale of multiplexer and time delay meeting become very large, have increased the complexity of design.
In addition, the Chinese patent application that number of patent application is 200910209696.8 discloses a kind of apparatus and method of multichannel cell time slot multiplexing, and described device comprises input memory module, for the cell of input being carried out to buffer memory output; Gating network module, for carrying out gating output by the cell from input memory module; Output memory module, carries out buffer memory parallel output cell for the cell to from gating network module; And control logic module, for inputing to input and send read output signal to input memory module during memory module defining cell, and for exporting with predetermined tempo signal controlling gating, and will input data parallel output for control output memory module when definite gating output has completed, in this patent scheme, although it can receive simultaneously or the cell of random input by its parallel output, and adopt a plurality of multiplexers and memory submodule to substitute single large multiplexer, reduced scale and the circuit design difficulty of multiplexer.
But in the method, it still only supports the processing of fixed length cell, for elongated cell, cannot process.The mode that adopts fixed length cell waste bandwidth greatly when some transfer of data, affects efficiency, so, how to provide a kind of method of supporting elongated cell time slot multiplexing just to become one of key technology point that current industry need to solve.
Summary of the invention
The problem that can not process elongated cell input in order to overcome prior art, the invention provides a kind of device and method of supporting the elongated cell time slot multiplexing of multichannel.
The present invention is by the following technical solutions:
A device of supporting the elongated cell time slot multiplexing of multichannel, comprising:
Input memory module, for the elongated cell of multichannel of input is given respectively to buffer memory, and the first sequencing control order sending according to control logic module is exported to gating network module by the elongated cell data of buffer memory;
Gating network module, it comprises a plurality of parallel multiplexers, for the second sequencing control order sending according to control logic module, the elongated cell data of reading from input memory module is carried out to gating output;
Output memory module, carries out buffer memory for the elongated cell data to from gating network module, and the 3rd sequencing control order sending according to control logic module, and the elongated cell data that timeslot multiplex is completed is exported;
Control logic module, exports to gating network module for control inputs memory module by the elongated cell data of buffer memory; Be further used for controlling gating network module the elongated cell data of reading from input memory module is carried out to gating output; And be further used for controlling the elongated cell data that output memory module completes timeslot multiplex and export.
Preferably, described input memory module comprises a plurality of sub module stored, for the elongated cell of multichannel of buffer memory input; Wherein,
When having cell input, described sub module stored is by the set of non-NULL index signal.
Preferably, described output memory module comprises a plurality of parallel memory RAM immediately (Random Access Memory, random asccess memory) or register, elongated cell data for buffer memory from gating network module, and the 3rd sequencing control order sending according to control logic module, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
Preferably, described control logic module comprises:
Internal control signal generation module, for generation of rhythm control signal, and is sent to respectively input memory module, gating network module and output memory module by it;
Output control signal generation module, under the rhythm control signal generating at internal control signal generation module, carries out gating output by the non-dummy status in input memory module.
Preferably, under the control of the rhythm control signal that the multiplexer in gating network module sends in control logic module, the elongated cell data receiving is carried out to gating output and is sent to output memory module.
A method of supporting the elongated cell time slot multiplexing of multichannel, comprising:
Input memory module gives respectively buffer memory to the elongated cell of multichannel of input, and the first sequencing control order sending according to control logic module is exported to gating network module by the elongated cell data of buffer memory;
The second sequencing control order that the gating network module that comprises a plurality of parallel multiplexers sends according to control logic module, carries out gating output by the elongated cell data of reading from input memory module;
Output memory module is carried out buffer memory to the elongated cell data from gating network module, and the 3rd sequencing control order sending according to control logic module, and the elongated cell data that timeslot multiplex is completed is exported.
Preferably, described input memory module comprises a plurality of sub module stored, for the elongated cell of multichannel of buffer memory input; Wherein, before execution input memory module gives respectively the step of buffer memory to the elongated cell of multichannel of input, described method also comprises:
When having cell input, described sub module stored is by the set of non-NULL index signal.
Preferably, described output memory module comprises a plurality of parallel memory RAM immediately or registers, elongated cell data for buffer memory from gating network module, and the 3rd sequencing control order sending according to control logic module, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
Preferably, described control logic module comprises:
Internal control signal generation module, for generation of rhythm control signal, and is sent to respectively input memory module, gating network module and output memory module by it;
Output control signal generation module, under the rhythm control signal generating at internal control signal generation module, carries out gating output by the non-dummy status in input memory module.
Preferably, described in comprise a plurality of parallel multiplexers the second sequencing control order that sends according to control logic module of gating network module, the elongated cell data of reading from input memory module is carried out the step of gating output:
Under the control of the rhythm control signal that the multiplexer in gating network module sends in control logic module, the elongated cell data receiving is carried out to gating output and is sent to output memory module.
Technical scheme by the invention described above can be found out, the present invention utilizes input memory module to carry out the elongated cell buffer memory of multichannel, adopts gating network module and output memory module jointly to complete the timeslot multiplex of the elongated cell of multichannel, can process in real time the timeslot multiplex of the elongated cell of multichannel under Arbitrary Relative relation, guarantee the bandwidth usage of each input port, improved processing flexibility.
In addition, the present invention is applicable to the elongated cell of all lengths, only needs the degree of depth to storage on circuit, and the timeslot multiplex number of times of each port cell and the quantity of multiplexer and sub module stored are changed design, thereby has improved the flexibility of design.
Accompanying drawing explanation
Fig. 1 is the apparatus structure schematic diagram of the elongated cell time slot multiplexing of support multichannel in the embodiment of the present invention;
Fig. 2 is the input storage internal structure schematic diagram in the embodiment of the present invention;
Fig. 3 is the gating network internal structure schematic diagram in the embodiment of the present invention;
Fig. 4 is the output storage internal structure schematic diagram in the embodiment of the present invention;
Fig. 5 is the control logic internal structure schematic diagram in the embodiment of the present invention;
Fig. 6 is the data transmission method schematic diagram in the embodiment of the present invention;
Fig. 7 is the data processing method flow chart in the embodiment of the present invention.
The realization of the object of the invention, functional characteristics and excellent effect, be described further below in conjunction with specific embodiment and accompanying drawing.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described in further detail, so that those skilled in the art can better understand the present invention also, can be implemented, but illustrated embodiment is not as a limitation of the invention.
As shown in Figure 1, a kind of device of supporting the elongated cell time slot multiplexing of multichannel that the embodiment of the present invention provides, comprising:
During concrete enforcement, it comprises several first-in first-out submodules, data storage of each port.In order to the input data on each link, carry out buffer memory, and under certain port polling, by inner data reading to gating network module 102.
Under preferred implementation, described input memory module 101 comprises a plurality of sub module stored (being for example first-in first-out FIFO submodule), for the elongated cell of multichannel of buffer memory input; Wherein, when having cell input, described sub module stored is by the set of non-NULL index signal.
Gating network module 102, it comprises a plurality of parallel multiplexers, for the second sequencing control order sending according to control logic module 104, the elongated cell data of reading from input memory module 101 is carried out to gating output.
During concrete enforcement, it comprises several multiplexers, in order to by the data in the input storage of reading, is transferred to corresponding output memory module 103 spatial caches.
Under preferred implementation, under the control of the rhythm control signal that the multiplexer in gating network module 102 sends in control logic module 104, the elongated cell data receiving is carried out to gating output and be sent to output memory module 103.
During concrete enforcement, it comprises several sub module stored, can consist of RAM or register.In order to receive the data of corresponding multiplexer input in gating network module 102, and after certain sequential, the multiplexing data that complete are exported.
Under preferred implementation, described output memory module 103 comprises a plurality of parallel memory RAM immediately or registers, elongated cell data for buffer memory from gating network module 102, and the 3rd sequencing control order sending according to control logic module 104, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
During concrete enforcement, in order to the control information of input memory module 101, gating network module 102, output memory module 103 to be provided.
Under preferred implementation, described control logic module 104 comprises:
Internal control signal generation module 501, for generation of rhythm control signal, and is sent to respectively input memory module 101, gating network module 102 and output memory module 103 by it;
Output control signal generation module 502, under the rhythm control signal generating at internal control signal generation module 501, carries out gating output by the non-dummy status in input memory module 101.
As shown in Figure 2, input memory module 101 inside consist of several sub module stored, and the degree of depth of each sub module stored is the length of 1 maximum cell, and input is connected with the input of whole device.Sub module stored is after having received data and having inputted, by the set of non-NULL index signal.When sub module stored is carried out to data reading, control logic module 104 is inquired about the non-NULL index signal of sub module stored according to the order of 0 ~ m successively by rhythm control signal, and non-NULL index signal is offered to control logic module 104.
As shown in Figure 3, gating network module 102 inside are by several mux(Multiplexer, multiplexer) form, the input number of each mux is identical with the sub module stored quantity in input memory module 101, and the quantity n of mux is identical with parallel output bus k bit or sub module stored output bus j bit.When mux is controlled, control logic module 104 starts mux by rhythm control signal successively according to the order of 0 ~ n.Each mux carries out gating output to input signal successively by the order of 0 ~ m after starting.
As shown in Figure 4, output memory module 103 is comprised of several RAM or register, in the present embodiment, the input of each RAM is connected with gating network module 102, and the output of all RAM binds together, and has formed the output of the multiplexing device of cell.The number of output memory module 103RAM is identical with output bus kbit/64bit, and the degree of depth is identical with the input port number of input storage.After receiving the data of gating network module 102,0# ~ (n-1) #RAM is exported its inner data after the regular hour together by control logic module 104, completes timeslot multiplex.Wherein, read the valid data write time that the control of time can need to export according to this and determine, also can be as exporting kbit data output time delay output, specific design can be applied in a flexible way.
As shown in Figure 5, control logic module 104 is comprised of internal control signal generation module 501 and output control signal generation module 502.Internal control signal generation module 501 comprises counter and some control circuits, for generation of rhythm control signal, outputs to input memory module 101, gating network module 102 and output memory module 103, thereby realize, these 3 modules is controlled.
The cadence signal that output control signal generation module 502 produces at internal control signal generation module 501 carries out gating output by the non-dummy status of Input Control Element in input memory module 101 under controlling, and generates output control signal.
Adopt the device of the elongated cell time slot multiplexing of above-mentioned support multichannel to carry out the concrete implementation step of elongated cell time slot multiplexing as follows:
Steps A, input memory module 101 receives the elongated cell of multichannel from input port.
Step B, the buffer memory in input memory module 101 carries out buffer memory to elongated cell data, and provides the indication of buffer memory non-NULL.
Step C, 104 couples of input memory module 1010 ~ m(of control logic module wherein, m is the way of input memory module 101 parallel buffers) elongated cell data in number buffer memory carries out poll, if this buffer memory is non-NULL, just read interior data, the number of slices of sense data is determined according to the length information of elongated cell, if length information surpasses parallel output bus number k bit, only read k bit data, provide the indication information of first count simultaneously, remaining data reads at next polling cycle, reads at most k bit data, and poll reads successively; If it is empty, do not carry out data reading.
Step D, the multiplexer of gating network module 102 inside according to 0 ~ n(wherein, n is the quantity of the multiplexer of gating network module 102 inside) number order open successively, each multiplexer with circulation mode the data in 0 ~ m buffer memory are mail to respectively to corresponding output sub module stored.
Step e, output sub module stored in output memory module 103 is kept in elongated cell data, under the control of control logic module 104 counters, cyclically by the data output in 0 ~ n address in all output sub module stored, complete the timeslot multiplex of a plurality of passage cells.
Adaptably, the embodiment of the present invention also provides a kind of method of supporting the elongated cell time slot multiplexing of multichannel, comprising:
The elongated cell of multichannel of S101,101 pairs of inputs of input memory module gives respectively buffer memory, and the first sequencing control order sending according to control logic module 104 is exported to gating network module 102 by the elongated cell data of buffer memory;
The second sequencing control order that S102, the gating network module 102 that comprises a plurality of parallel multiplexers send according to control logic module 104, carries out gating output by the elongated cell data of reading from input memory module 101;
S103, the elongated cell data of 103 pairs of memory modules of output from gating network module 102 carry out buffer memory, and the 3rd sequencing control order sending according to control logic module 104, and the elongated cell data that timeslot multiplex is completed is exported.
During concrete enforcement, described input memory module 101 comprises a plurality of sub module stored, for the elongated cell of multichannel of buffer memory input; Wherein, before the elongated cell of multichannel of carrying out 101 pairs of inputs of input memory module gives respectively the step of buffer memory, described method also comprises:
S100, when there being cell when input, described sub module stored is by the set of non-NULL index signal.
During concrete enforcement, the second sequencing control order that the described gating network module 102 that comprises a plurality of parallel multiplexers sends according to control logic module 104, the elongated cell data of reading from input memory module 101 is carried out the step of gating output: under the control of the rhythm control signal that the multiplexer in gating network module 102 sends in control logic module 104, the elongated cell data receiving is carried out to gating output and be sent to output memory module 103.
Described output memory module 103 comprises a plurality of parallel memory RAM immediately or registers, elongated cell data for buffer memory from gating network module 102, and the 3rd sequencing control order sending according to control logic module 104, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
For the device of the support multichannel elongated cell time slot multiplexing corresponding with described method, the control logic module 104 that it comprises comprises:
Internal control signal generation module 501, for generation of rhythm control signal, and is sent to respectively input memory module 101, gating network module 102 and output memory module 103 by it;
Output control signal generation module 502, under the rhythm control signal generating at internal control signal generation module 501, carries out gating output by the non-dummy status in input memory module 101.
The data transmission method of the elongated cell time slot multiplexing device of multichannel that the embodiment of the present invention provides as shown in Figure 6, initial time slot_0 after electrification reset constantly, by after the data reading on No. 0 address on input memory module 101#0, store in No. 0 address on ram# 0; At time slot_1 constantly, No. 1 address on will input memory module 101#0 and two data readings on the 0th address on input memory module 101#1, store in No. 0 address and No. 1 address on ram# 0 on ram# 1; Each sense data of each input memory module 101 is no more than kbit; After time slot_m, in each clock cycle in each input memory module 101 by sense data, wherein input the data in h address in memory module 101#m and will store ram#h(h≤n-1 into) in m address.
As shown in Figure 7, for the elongated cell data that enters the device of the elongated cell time slot multiplexing of support multichannel that the embodiment of the present invention provides, as follows for its handling process:
Step 2, the input memory cell of input memory module 101 is carried out buffer memory to elongated cell, and waits for read output signal.
Step 3, the input memory cell of input memory module 101 receives read output signal, and data are exported to gating network module 102, wherein, the data that at every turn read are no more than kbit, and the kbit data that at every turn read are carried out to 0,1,2 ... mark, is recombinated by subsequent module.
Step 4, the multiplexer in gating network module 102, under the control of the cadence signal of control logic module 104, carries out gating output by the signal receiving, and is sent to output memory module 103.
Step 5, the data that output memory module 103 receives in gating network module 102, the row cache of going forward side by side.
Step 6, judges output time, if reach, the data in output memory module 103 is exported.
Step 7, the elongated cell after timeslot multiplex is completed is exported.
The foregoing is only the preferred embodiments of the present invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes specification of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a device of supporting the elongated cell time slot multiplexing of multichannel, is characterized in that, comprising:
Input memory module, for the elongated cell of multichannel of input is given respectively to buffer memory, and the first sequencing control order sending according to control logic module is exported to gating network module by the elongated cell data of buffer memory;
Gating network module, it comprises a plurality of parallel multiplexers, for the second sequencing control order sending according to control logic module, the elongated cell data of reading from input memory module is carried out to gating output;
Output memory module, carries out buffer memory for the elongated cell data to from gating network module, and the 3rd sequencing control order sending according to control logic module, and the elongated cell data that timeslot multiplex is completed is exported;
Control logic module, exports to gating network module for control inputs memory module by the elongated cell data of buffer memory; Be further used for controlling gating network module the elongated cell data of reading from input memory module is carried out to gating output; And be further used for controlling the elongated cell data that output memory module completes timeslot multiplex and export.
2. the device of the elongated cell time slot multiplexing of support multichannel as claimed in claim 1, is characterized in that, described input memory module comprises a plurality of sub module stored, for the elongated cell of multichannel of buffer memory input; Wherein,
When having cell input, described sub module stored is by the set of non-NULL index signal.
3. the device of the elongated cell time slot multiplexing of support multichannel as claimed in claim 1, it is characterized in that, described output memory module comprises a plurality of parallel memory RAM immediately or registers, elongated cell data for buffer memory from gating network module, and the 3rd sequencing control order sending according to control logic module, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
4. the device of the elongated cell time slot multiplexing of support multichannel as claimed in claim 2, is characterized in that, described control logic module comprises:
Internal control signal generation module, for generation of rhythm control signal, and is sent to respectively input memory module, gating network module and output memory module by it;
Output control signal generation module, under the rhythm control signal generating at internal control signal generation module, carries out gating output by the non-dummy status in input memory module.
5. the device of the elongated cell time slot multiplexing of support multichannel as claimed in claim 1, it is characterized in that, under the control of the rhythm control signal that the multiplexer in gating network module sends in control logic module, the elongated cell data receiving is carried out to gating output and is sent to output memory module.
6. a method of supporting the elongated cell time slot multiplexing of multichannel, is characterized in that, comprising:
Input memory module gives respectively buffer memory to the elongated cell of multichannel of input, and the first sequencing control order sending according to control logic module is exported to gating network module by the elongated cell data of buffer memory;
The second sequencing control order that the gating network module that comprises a plurality of parallel multiplexers sends according to control logic module, carries out gating output by the elongated cell data of reading from input memory module;
Output memory module is carried out buffer memory to the elongated cell data from gating network module, and the 3rd sequencing control order sending according to control logic module, and the elongated cell data that timeslot multiplex is completed is exported.
7. the method for the elongated cell time slot multiplexing of support multichannel as claimed in claim 6, is characterized in that, described input memory module comprises a plurality of sub module stored, for the elongated cell of multichannel of buffer memory input; Wherein, before execution input memory module gives respectively the step of buffer memory to the elongated cell of multichannel of input, described method also comprises:
When having cell input, described sub module stored is by the set of non-NULL index signal.
8. the method for the elongated cell time slot multiplexing of support multichannel as claimed in claim 6, it is characterized in that, described output memory module comprises a plurality of parallel memory RAM immediately or registers, elongated cell data for buffer memory from gating network module, and the 3rd sequencing control order sending according to control logic module, the elongated cell data that completes timeslot multiplex in RAM or register is exported.
9. the method for the elongated cell time slot multiplexing of support multichannel as claimed in claim 7, is characterized in that, described control logic module comprises:
Internal control signal generation module, for generation of rhythm control signal, and is sent to respectively input memory module, gating network module and output memory module by it;
Output control signal generation module, under the rhythm control signal generating at internal control signal generation module, carries out gating output by the non-dummy status in input memory module.
10. the method for the elongated cell time slot multiplexing of support multichannel as claimed in claim 6, it is characterized in that, the second sequencing control order that the described gating network module that comprises a plurality of parallel multiplexers sends according to control logic module, the elongated cell data of reading from input memory module is carried out the step of gating output:
Under the control of the rhythm control signal that the multiplexer in gating network module sends in control logic module, the elongated cell data receiving is carried out to gating output and is sent to output memory module.
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| CN201210384420.5A CN103731224B (en) | 2012-10-11 | 2012-10-11 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
| PCT/CN2013/082493 WO2014056362A1 (en) | 2012-10-11 | 2013-08-28 | Device and method for supporting time-slot multiplexing of multichannel variable-length cells |
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| CN114640728A (en) * | 2022-02-25 | 2022-06-17 | 烽火通信科技股份有限公司 | Protocol frame timing frame sending control method, device, equipment and storage medium |
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| CN1422508A (en) * | 2000-03-23 | 2003-06-04 | 西门子移动通讯公司 | Telecommunication process and system handling data organized in cells of variable length |
| US7162034B1 (en) * | 2000-12-29 | 2007-01-09 | Cisco Technology, Inc. | Method and apparatus for multi-session time-slot multiplexing |
| CN101741720A (en) * | 2009-11-06 | 2010-06-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
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| CN1819523A (en) * | 2006-02-20 | 2006-08-16 | 中国人民解放军国防科学技术大学 | Parallel interchanging switching designing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1422508A (en) * | 2000-03-23 | 2003-06-04 | 西门子移动通讯公司 | Telecommunication process and system handling data organized in cells of variable length |
| US7162034B1 (en) * | 2000-12-29 | 2007-01-09 | Cisco Technology, Inc. | Method and apparatus for multi-session time-slot multiplexing |
| CN101741720A (en) * | 2009-11-06 | 2010-06-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114640728A (en) * | 2022-02-25 | 2022-06-17 | 烽火通信科技股份有限公司 | Protocol frame timing frame sending control method, device, equipment and storage medium |
| CN114640728B (en) * | 2022-02-25 | 2023-05-16 | 烽火通信科技股份有限公司 | Protocol frame timing frame sending control method, device, equipment and storage medium |
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