CN101730398A - 印刷电路板及其制作方法 - Google Patents

印刷电路板及其制作方法 Download PDF

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CN101730398A
CN101730398A CN200810305114.1A CN200810305114A CN101730398A CN 101730398 A CN101730398 A CN 101730398A CN 200810305114 A CN200810305114 A CN 200810305114A CN 101730398 A CN101730398 A CN 101730398A
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test point
circuit board
printed circuit
pcb
connecting line
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周厚原
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN200810305114.1A priority Critical patent/CN101730398A/zh
Priority to US12/277,250 priority patent/US8143528B2/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0268Marks, test patterns or identification means for electrical inspection or testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2818Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/093Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/09309Core having two or more power planes; Capacitive laminate of two power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663Divided layout, i.e. conductors divided in two or more parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/162Testing a finished product, e.g. heat cycle testing of solder joints
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

一种印刷电路板,包括层叠设置的一信号层、一绝缘层及一参考层,所述信号层上设有一传输线,所述传输线上设有一测试点,所述参考层上对应于所述测试点的位置处设有一开槽,所述开槽于对应所述测试点的位置处设有一连接开槽两侧参考层的连接线。上述印刷电路板利用所述开槽及连接线来降低信号在传输过程中由所述测试点引起的电容效应。

Description

印刷电路板及其制作方法
技术领域
本发明涉及一种印刷电路板及其制作方法。
背景技术
在印刷电路板上,常常可见到一些圆形的测试点,其可供探棒去量测信号。基本上这些测试点是设置在印刷电路板的传输线上的,其相当于在传输线上增加一个很小的电容。因此,在传输高频信号时,这些测试点对信号的品质就会产生一定的影响,即电容效应。
发明内容
鉴于以上内容,有必要提供一种能降低测试点电容效应的印刷电路板,以减小测试点对信号品质的影响。
还有必要提供一种制作上述印刷电路板的制作方法。
一种印刷电路板,包括层叠设置的一信号层、一绝缘层及一参考层,所述信号层上设有一传输线,所述传输线上设有一测试点,所述参考层上对应于所述测试点的位置处设有一开槽,所述开槽于对应所述测试点的位置处设有一连接开槽两侧参考层的连接线。
一种印刷电路板的制作方法,包括以下步骤:
在信号层的传输线上设置一测试点;
在参考层上对应于所述测试点的位置处设置一具有一连接线的开槽。
上述印刷电路板在所述测试点所在的信号层邻近的参考层上位于所述测试点的正对位置处设置一开槽及一连接线,并利用所述连接线产生的电感效应来补偿所述测试点引起的电容效应,以降低在传输过程中所述测试点对信号品质的影响。
附图说明
下面结合附图及较佳实施方式对本发明作进一步详细描述:
图1为本发明印刷电路板的较佳实施方式的结构图。
图2为图1中第一信号层的正视图。
图3为图1中测试点、开槽及连接线的分布示意图。
图4为本发明印刷电路板未设开槽及连接线时测试点半径取不同值的信号损耗曲线图。
图5为本发明印刷电路板设有开槽及连接线时测试点半径取不同值的信号损耗曲线图。
图6为本发明印刷电路板的连接线宽度取不同值时信号频率为10Ghz的损耗曲线图。
具体实施方式
请共同参考图1及图2,本发明印刷电路板的较佳实施方式包括一第一信号层100、一电源层200、一接地层300以及一第二信号层400。所述第一信号层100设置于一第一半固化片(Prepreg)PP1的上方,所述电源层200设置于所述第一半固化片PP1的下方;所述接地层300设置于一第二半固化片PP2的上方,所述第二信号层400设置于所述第二半固化片PP2的下方。所述电源层200与所述接地层300通过一核心板CORE进行粘合。
所述第一半固化片PP1及第二半固化片PP2是通过将一些绝缘性载体材料浸在液态的树脂中,使其吸饱后再缓缓从液态的树脂中拖出并刮走多余的树脂,再经过热风与红外线加热,促使绝缘性载体材料进行部份之聚合反应而成的。所述核心板CORE为多层板之间的一内层薄基板,其具有粘合与绝缘的作用。所述第一半固化片PP1、第二半固化片PP2以及核心板CORE均可称为绝缘层,其对第一信号层100、电源层200、接地层300以及第二信号层400进行隔离,以防止信号和电流的相互干扰。所述第一信号层100上设有一传输线102,在所述传输线102上设有一测试点104,所述测试点104可供一探棒(图未示)去量测信号。所述第一信号层100及第二信号层400附有防焊膜(图未示)。所述防焊膜,是指在印刷电路板表面将不需焊接的部份导体,以永久性的树脂皮膜加以遮盖,其除了具防焊功用外,也能对所覆盖的线路起到保护与绝缘的作用。所述传输线102上也覆盖有防焊膜,所述测试点104上则无防焊膜。
请继续参照图3,所述电源层200上设有一开槽202,所述开槽202位于所述测试点104的正下方,其宽度等于所述测试点104的直径值。所述开槽202内设有一连接线206,所述连接线206位于所述测试点104的正下方,且与所述传输线102平行,其长度等于所述测试点104的直径值。所述开槽202用于切断所述电源层200上的回流路径,所述连接线206用于连接所述电源层200上被所述开槽202分开的部分,以形成新的回流路径。所述开槽202及连接线206是通过将所述电源层200上的铜箔蚀刻掉而形成的。
当一高频信号经所述传输线102传输到所述测试点104时,由于所述测试点104的直径比所述传输线102的宽度大,电流流经所述测试点104时会发散开,从而引起的电容效应,进而影响到所述高频信号的品质。又因高频信号的回流路径一般位于信号传输线的正下方,且频率越高,信号越集中,其回流路径就越窄。在所述电源层200上,所述高频信号原有的回流路径已被所述开槽202切断,分开的部分仅靠所述连接线206相连,故所述高频信号新的回流路径必须经过所述连接线206,于是,只需调整所述连接线206的宽度,便可利用所述高频信号流经所述连接线206时产生的电感效应对所述测试点104引起的电容效应进行补偿,进而降低所述测试点104引起的电容效应对所述高频信号品质的影响。
请共同参考图4及图5,在图4及图5中,横坐标均为信号传输频率;纵坐标均为信号传输的插入损耗(Insertion Loss)IL,例如,当纵坐标插入损耗IL=-0.1db时,则表示信号的插入损耗IL为0.1db;且曲线1均为所述印刷电路板上未设所述测试点104、所述开槽202及所述连接线206时的信号损耗曲线。两图的区别在于:图4中的曲线2-7分别为所述印刷电路板上未设所述开槽202及所述连接线206但设有所述测试点104,且所述测试点104的半径r1分别为5mil、10mil、15mil、20mil、25mil及30mil时的信号损耗曲线;图5中曲线2-7则分别为所述印刷电路板上设有所述开槽202、所述连接线206及所述测试点104,且所述测试点104的半径r1分别为5mil、10mil、15mil、20mil、25mil及30mil时的信号损耗曲线。通过对比图4及图5可发现,在传输高频信号时,当所述电源层200上设有所述开槽202及连接线206时,所述测试点104所引起的损耗明显小于未设所述开槽202及连接线206时的损耗。
在本较佳实施例中,所述印刷电路板的相关参数为:所述第一信号层100及第二信号层400的厚度T1=1.6mil;所述电源层200及接地层300的厚度T2=1.2mil;所述第一信号层100及第二信号层400上防焊膜厚度T3=0.7mil,传输线102上的防焊膜厚度T4=0.5mil;所述第一半固化片PP1及所述第二半固化片的厚度T5=2.6mil,其介电常数(Dielectric Constant)Dk1=3.7,损耗因素(Dissipation Factor)Df1=0.02;所述核心板CORE的厚度T6=47mil;所述测试点104的半径r1=15mil,其介电常数Dk2=4,其损耗因素Df2=0.02;所述槽线202的宽度W1=30mil;所述连接线206的长度L1=30mil;所述传输线102的厚度T6=1.6mil,其长度L2=400mil。根据这些参数在一仿真系统进行模拟仿真,以获取所述连接线206的宽度W2的最佳值。
图6为本发明印刷电路板的连接线206宽度取不同值时信号传输频率为10Ghz的损耗曲线图。图6中横坐标为所述连接线206的宽度W2取值,纵坐标为所述连接线206的宽度W2取不同值时信号的插入损耗情况。由图6可明显看出,当所述连接线206的宽度W2=4.5mil时,信号传输过程中损耗最少,即所述测试点104所引起的电容效应最小。
在其它实施例中,所述开槽202与所述传输线102只要成一定角度,且能起到切断所述电源层200上的回流路径的作用即可,此时,所述开槽202的宽度及所述连接线206的长度需相应调整。当所述传输线102及测试点104设置于所述第二信号层400时,则可在所述接地层300上设置所述开槽202及连接线206,此时所述开槽202及连接线206位于所述测试点104的正上方,同样也可达到解决所述测试点104所引起的电容效应的问题。
本发明印刷电路板也可为二层板或其他多层板,而不局限于本较佳实施例中的四层板,当所述印刷电路板为二层板时,所述电源层200、接地层300可设置于同一层,称为电源接地层。所述电源层200、接地层300以及电源接地层是作为信号层100、400的参考层。在所述印刷电路板上只要将所述开槽202及连接线206设置于所述测试点104的正上方或者正下方,均可达到降低所述测试点104所引起的电容效应。
上述印刷电路板在距离所述测试点104所在的第一信号层100或第二信号层400最近的电源层200或接地层300上位于所述测试点104的正对位置处设置一开槽202及一连接线206,以利用所述连接线206产生的电感效应来补偿所述测试点104引起的电容效应,从而降低在传输过程中所述测试点104对信号品质的影响。

Claims (10)

1.一种印刷电路板,包括层叠设置的一信号层、一绝缘层及一参考层,所述信号层上设有一传输线,所述传输线上设有一测试点,其特征在于:所述参考层上对应于所述测试点的位置处设有一开槽,所述开槽于对应所述测试点的位置处设有一连接开槽两侧参考层的连接线。
2.如权利要求1所述的印刷电路板,其特征在于:所述连接线平行于所述传输线。
3.如权利要求1所述的印刷电路板,其特征在于:所述开槽的宽度等于所述测试点的直径值。
4.如权利要求3所述的印刷电路板,其特征在于:所述测试点的半径为15mil,所述连接线的宽度为4.5mil。
5.如权利要求1所述的印刷电路板,其特征在于:所述参考层为一电源层或一接地层或一电源接地层。
6.一种印刷电路板的制作方法,包括以下步骤:
在信号层的传输线上设置一测试点;
在参考层上对应于所述测试点的位置处设置一具有一连接线的开槽。
7.如权利要求6所述的印刷电路板的制作方法,其特征在于:所述连接线位于所述开槽内对应于所述测试点的位置处,且平行于所述传输线。
8.如权利要求7所述的印刷电路板的制作方法,其特征在于:所述开槽的宽度等于所述测试点的直径值。
9.如权利要求8所述的印刷电路板的制作方法,其特征在于:所述测试点的半径为15mil,所述连接线的宽度为4.5mil。
10.如权利要求6所述的印刷电路板的制作方法,其特征在于:所述开槽及连接线是将所述参考层上的铜箔蚀刻掉而形成。
CN200810305114.1A 2008-10-23 2008-10-23 印刷电路板及其制作方法 Pending CN101730398A (zh)

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US12/277,250 US8143528B2 (en) 2008-10-23 2008-11-24 Printed circuit board and method of manufacturing the same

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