CN101714404A - 包括氧化物薄膜晶体管的多层存储设备 - Google Patents

包括氧化物薄膜晶体管的多层存储设备 Download PDF

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CN101714404A
CN101714404A CN200910204905A CN200910204905A CN101714404A CN 101714404 A CN101714404 A CN 101714404A CN 200910204905 A CN200910204905 A CN 200910204905A CN 200910204905 A CN200910204905 A CN 200910204905A CN 101714404 A CN101714404 A CN 101714404A
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memory apparatus
layered memory
layered
circuit unit
transistor
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宋利宪
朴宰彻
权奇元
金善日
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种包括氧化物薄膜晶体管的多层存储设备。所述多层存储设备包括有源电路单元和有源电路单元上形成的存储部件。行线和列线形成在存储层上。选择晶体管形成在行线和列线的侧端。

Description

包括氧化物薄膜晶体管的多层存储设备
技术领域
一个或多个示例性实施例涉及一种多层存储设备，更具体地讲，涉及一种包括形成在存储部件的各存储层中的选择晶体管的多层存储设备。
背景技术
随着工业和多媒体的发展，对大型信息存储装置(例如，在计算机或通信装置中使用的那些存储装置)的需求逐渐增加。由于这种需求，已对具有高信息存储密度和操作速度的信息装置进行了研究。
传统的存储装置通常包括有源电路单元和存储部件。有源电路单元包括寻址解码器、读/写控制逻辑、感测放大器、输出缓冲器和复用器。通常，将这些元件统称为系统开销，并占用物理存储器的预定区域。系统开销的大小越小，存储区域的大小越大。
为了增加存储装置的存储密度，已开始对开发多层存储设备进行了研究。多层存储设备包括有源电路单元和多个存储单元阵列，所述有源电路单元包括有源电路。有源电路支持对多层存储设备执行的操作，例如，读操作和写操作。此外，在硅基底上形成有源电路。在有源电路上堆叠多个存储单元阵列。在有源电路单元中形成用于选择存储单元阵列的选择晶体管。随着存储层被进一步堆叠，有源电路单元的大小由于选择晶体管的数量而急剧增加。
发明内容
一个或多个示例性实施例包括一种高度集成的多层存储设备，所述高度集成的多层存储设备包括在各多层存储部件中形成的选择晶体管。
其他方面将在下面的描述中被部分地阐述，部分地，根据描述是清楚的，或者可通过实施示例性实施例而获知。
示例性实施例公开了一种包括有源电路单元和多个存储层的多层存储设备。所述多个存储层形成在有源电路单元上。所述多个存储层中的每一层包括：多条行线和多条列线，连接到有源电路单元；选择晶体管，形成在行线和列线中每一条的至少一个侧端上。
至少一个其他示例性实施例提供一种包括有源电路单元和有源电路单元上的存储部件的多层存储设备。所述存储部件包括连接到行选择单元的行线和连接到列选择单元的列线。所述行选择单元和列选择单元在存储部件上。
另一示例性实施例指示一种包括有源电路单元和存储部件的多层存储设备，所述存储部件包括以交叉点阵列布置的多个堆叠的存储单元。所述多个堆叠的存储单元中的每一个包括：下电极，连接到第一选择晶体管；上电极，连接到第二选择晶体管；存储节点，在下电极和上电极之间。
一个或多个示例性实施例可包括一种多层存储设备，所述多层存储设备包括有源电路单元和在有源电路单元上形成的多个存储层。所述多个存储层中的每一层包括连接到有源电路单元的多条行线和多条列线，其中，每个存储层可包括在行线和列线中每一条的至少一侧端上形成的选择晶体管。
每个选择晶体管可以是氧化物薄膜晶体管(TFT)。
每一存储层可包括交叉点型存储阵列结构。
每一存储层可包括在行线和列线之间的每个交叉点处的开关结构和存储区域。
氧化物TFT可包括在下结构上形成的栅极、在下结构和栅极上形成的栅极绝缘层。在栅极绝缘层的对应于栅极的一部分上形成沟道，并且沟道包括Zn氧化物。在栅极绝缘层上沟道的两个侧端上形成源极和漏极。
选择晶体管可交替地形成在行线或列线的两个侧端上。
有源电路单元可包括：电平解码器，用于从多个存储阵列中选择存储层；和预解码器，用于对选择的存储层的存储单元进行选择。
有源电路单元可形成在硅基底上。
预解码器可经公共电极连接到选择晶体管。
电平解码器可连接到选择晶体管的栅极。
即使堆叠的存储层的数量增加，也可将有源电路单元的大小最小化。
附图说明
从下面结合附图对示例性实施例的描述，示例性实施例的这些和/或其他方面将变得清楚并更容易理解，其中：
图1示出示例性实施例的多层存储设备；
图2A是沿图1的线1-1’截取的多层存储设备的横截面图；
图2B是沿图1的线m-m’截取的多层存储设备的横截面图；
图3是图1的多层存储设备的电路图；
图4示出根据示例性实施例的图1的多层存储设备的存储部件的透视图；
图5A示出根据示例性实施例的多层存储设备；
图5B示出根据另一示例性所述的多层存储设备和列线；
图6是根据示例性实施例的可在图1的多层存储设备中使用的薄膜晶体管(TFT)的透视图。
具体实施方式
根据结合附图进行的详细描述，将更清晰地理解示例性实施例。
现在将参照附图更全面地描述各种示例性实施例，在附图中示出了一些示例性实施例。在附图中，为了清晰起见，层和区域的厚度可能被放大。
这里公开了详细的示出目的的示例性实施例。然而，这里公开的特定结构和功能细节仅仅是代表性的为了描述示例性实施例的目的。然而，其他实施例可以以许多可替换形式来实施，并且不应该理解为仅限于这里阐述的示例性实施例。
因此，尽管示例性实施例能够进行各种修改和可替换形式，但在附图中举例来表示示例性实施例，并在这里对这些示例性实施例进行详细描述。然而，应该理解，不是意在将示例性实施例限制为公开的特定形式，相反，示例性实施例将覆盖落入所述示例性实施例的范围内的所有修改、等同物和替换。贯穿附图的描述，相同的标号始终表示相同的元件。
应该理解的是，尽管在这里可使用术语第一、第二等来描述各元件，但这些元件并不受这些术语的限制。这些术语仅是用来将一个与另一个元件区分开来。例如，在不脱离示例性实施例的范围的情况下，可将第一元件命名为第二元件，类似地，可将第二元件命名为第一元件。如在这里使用的，术语“和/或”包括一个或多个相关所列项的任意组合和所有组合。
应该理解的是，当元件被称作“连接到”或“结合”到另一元件时，可将该元件直接连接或结合到另一元件，或者可存在中间元件。相反，当元件被称作“直接连接到”或“直接结合到”另一元件时，不存在中间元件。应该在同样形式(例如，“在...之间”与“直接在...之间”、“相邻”与“直接相邻”等)中解释用于描述元件之间的关系的其他词。
这里所使用的术语仅为了描述特定示例性实施例的目的，而不是意在限制示例性实施例。如在这里使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其组合。
另外，使用词语“化合物”表示单个化合物或多个化合物。使用这些词语来表示一个或多个化合物，但也可仅仅表示单个化合物。
现在，为了更具体地描述示例性实施例，将参照附图详细描述各种示例性实施例。在附图中，如果层形成在另一层或基底上，则表示层直接形成在另一层或基底上，或者在其间插入了第三层。在附图中，相同的标号表示相同的元件。
根据至少一个示例性实施例，多层存储设备可包括具有在有源电路单元上形成的多个存储阵列的存储部件，氧化物薄膜晶体管(TFT)可形成为每个存储阵列的选择晶体管。
图1、图2A和图2B示出根据示例性实施例的包括氧化物TFT的多层存储设备。图1是多层存储设备的平面图。图2A是沿图1的线1-1’截取的多层存储设备的横截面图。图2B是沿图1的线m-m’截取的多层存储设备的横截面图。
参照图1、图2A和图2B，在有源电路单元10上形成存储部件11。存储部件11包括在有源电路单元10上形成的多个存储层11a。可以以阵列形状来形成多个存储层11a中的每一层，并且多个存储层11a中的每一层可包括多个存储阵列。
存储层11a可包括在第一方向上形成的多条行线12和在第二方向(例如，垂直于第一方向)上形成的多条列线14。可在多条行线12和多条列线14之间形成存储节点(未示出)。多个选择晶体管13形成在行线12的第一端和第二端以及列线14的第一端和第二端，并可通过公共电极v连接到有源电路单元10。有源电路单元10还可包括用于支持存储器操作(例如，对存储部件11执行的读操作和写操作)的解码器、读/写控制逻辑和感测放大器。可通过使用普通的制造工艺在硅基底上形成有源电路单元10。
在多层存储设备的有源电路单元10的至少一侧端上形成用于选择存储部件11的存储层11a的电平解码器10a(第一解码器)。另外，形成用于对选择的存储层的单元进行选择的预解码器10b(图3中示出的第二解码器)，预解码器10b经公共电极v连接到选择晶体管13。
图3是图1的多层存储设备的电路图。
参照图3，在有源电路单元10中形成电平解码器10a和预解码器10b。电平解码器10a连接到选择晶体管13的栅极，所述选择晶体管13连接到存储部件11的每个存储层的行线12。预解码器10b连接到选择晶体管13的源极或漏极，所述选择晶体管13连接到每个存储层的行线12或列线14。如图3所示，电平解码器10a和预解码器10b连接到选择晶体管13，所述选择晶体管13连接到行线12。
将详细描述对多层存储设备执行的操作。首先，当有源电路单元10选择存储层11a时，通过电平解码器10a向存储部件11的选择的存储层11a的选择晶体管13施加信号。为了对选择的存储层11a的存储单元进行选择，将来自预解码器10b的信号施加到选择晶体管13，所述选择晶体管13连接到选择的存储层11a的行线12或列线14。如图3所示，选择晶体管13连接到行线12，但选择晶体管13可连接到列线14。
如图1至图3所示，将行解码器划分成预解码器10b和选择晶体管13，以用作行选择单元。预解码器10b设置在有源电路单元10上。每个选择晶体管13形成在存储层11a中的一层上。如果预解码器10b和选择晶体管13都在有源电路单元10上，则多层存储设备在空间上效率低。然而，当选择晶体管13形成在存储部件11上，以被连接到行线12或列线14时，可防止有源电路单元10的大小增加。
图4是根据示例性实施例的图1的多层存储设备的存储部件的透视图。
参照图4，存储部件11包括以阵列布置的多个存储单元MC。每个存储单元MC包括在第一方向上形成的下电极21、在下电极21上形成的开关结构22、存储区域23和在第二方向上在存储区域23上形成的上电极24。下电极21、开关结构22、存储区域23和上电极24依次堆叠。
开关结构22可形成为二极管。可用信息存储材料(例如，具有可变电阻的过渡金属氧化物)形成存储区域23。存储单元MC还在开关结构22和存储区域23之间包括中间电极25。开关结构22、存储区域23和中间电极25可形成存储节点。图4的存储阵列结构是交叉点型存储器。在上电极24上形成另外的电极线、开关结构和存储区域，以形成另外的存储单元和存储节点。
下电极21和上电极24可分别对应于行线12和列线14。选择晶体管13形成在下电极21和上电极24的侧端。
作为行选择单元和列选择单元的选择晶体管13可形成在行线12和列线14中每一条的任一侧端。形成有选择晶体管13的区域可选择性地被确定，并可在多层存储设备的设计期间被改变。例如，如图5A所示，选择晶体管13可只形成在行线12和列线14中每一条的一侧。可选择地，如图5B所示，选择晶体管13可形成在行线12和列线14的交替的侧端中的至少一个侧端上。
图6是根据示例性实施例的用作图1的多层存储设备的选择晶体管的TFT的透视图。在图6中，TFT是底栅型TFT。
参照图6，TFT 30包括栅极33，栅极33形成在下结构31和氧化层32上。应该明白，栅极33可直接形成在下结构31上，从而省略氧化层32。栅极绝缘层34形成在下结构31和栅极33上。沟道35形成在栅极绝缘层34的与栅极33重叠的一部分上。源极36a和漏极36b形成在栅极绝缘层34上在沟道35的侧端。
下结构31可由通常在半导体装置中使用的基底材料来形成，或者，可利用在基底材料上形成的氧化物和氮化物来形成。栅极绝缘层34可用普通绝缘材料制成，或用SiO2或介电常数比SiO2的高的高K材料形成。
可用Zn类的氧化物或者包括Zn类氧化物和金属(例如，Ga、In、Sn或Al)的化合物来形成沟道35。沟道35可形成为薄膜。沟道35可具有大约20nm至200nm范围的厚度。例如，可用化合物Ga2O3、In2O3和ZnO来形成沟道35。可使用沉积工艺来制成沟道35，在所述沉积工艺中，Zn和金属(例如，Ga、In、Sn或Al)的化合物作为单个靶进行溅射，或者ZnO以及Ga、In、Sn或Al进行共溅射。例如，当使用单个靶时，可使用包括比例为2∶2∶1的Ga2O3、In2O3和ZnO的化合物靶。然后，可在气体气氛(例如，N2)中在大约为250℃的温度执行退火。
可通过使用Si工艺形成有源电路单元10。然而，关于选择晶体管，由于选择晶体管不是形成在有源单元10上，所以难以使用Si类的外延生长工艺。另外，可在比大约900℃高的温度作为再结晶温度来执行高温工艺。因此，根据示例性实施例的多层存储设备可使用氧化物TFT作为选择晶体管。
如上所述，根据以上示例性实施例的一个或多个，本领域的技术人员已经明白，可通过使用氧化物TFT来制造包括多层存储设备的各种电子装置或设备。
应该明白，这里描述的示例性实施例应该被认为仅为描述目的，而不是为了限制目的。每个实施例内对特征或方面的描述应该按通常理解为可用于其他实施例中的相似特征或方面。

Claims (15)

1.一种多层存储设备，包括：
有源电路单元；
多个存储层，形成在有源电路单元上，所述多个存储层中的每一层包括多条行线、多条列线和选择晶体管，所述多条行线和所述多条列线连接到有源电路单元，所述选择晶体管形成在行线和列线中每一条的至少一个侧端上。
2.如权利要求1所述的多层存储设备，其中，每个选择晶体管是氧化物薄膜晶体管。
3.如权利要求2所述的多层存储设备，其中，存储层中的每一层被布置为交叉点型存储阵列，行线和列线交叉。
4.如权利要求3所述的多层存储设备，其中，所述多个存储层中的每一层包括开关结构以及行线和列线之间的每个交叉点处的存储区域。
5.如权利要求4所述的多层存储设备，其中，中间电极在每个开关结构和存储区域之间。
6.如权利要求2所述的多层存储设备，其中，氧化物薄膜晶体管包括：
栅极，形成在下结构上；
栅极绝缘层，形成在下结构和栅极上；
沟道，形成在栅极绝缘层的一部分上，所述沟道包括Zn氧化物；
源极和漏极，形成在沟道的端部上。
7.如权利要求1所述的多层存储设备，其中，选择晶体管交替地形成在所述多条行线中的每条行线的一个端部处，并交替地形成在所述多条列线中的每条列线的一个端部处。
8.如权利要求1所述的多层存储设备，其中，有源电路单元包括：
第一解码器，被构造为选择所述多个存储层中的第一存储层；
第二解码器，被构造为选择第一存储层的存储单元。
9.如权利要求8所述的多层存储设备，其中，第一解码器连接到选择晶体管的栅极。
10.一种多层存储设备，包括：
有源电路单元；
存储部件，在有源电路单元上的，所述存储部件包括行线和列线，行选择单元在存储部件上，行线连接到行选择单元。
11.如权利要求10所述的多层存储设备，其中，所述存储部件包括多个存储层。
12.如权利要求11所述的多层存储设备，其中，所述多个存储层中的每一层包括结合到行选择单元的行线。
13.如权利要求10所述的多层存储设备，其中，有源单元包括：
第一解码器，被构造为选择所述多个存储层中的第一存储层；
第二解码器，被构造为选择第一存储层的存储单元。
14.一种多层存储设备，包括：
有源电路单元；
存储部件，包括以交叉点阵列布置的多个堆叠的存储单元，所述多个堆叠的存储单元中的每一个包括下电极、上电极和存储节点，下电极连接到第一选择晶体管，上电极连接到第二选择晶体管，存储节点在下电极和上电极之间。
15.如权利要求14所述的多层存储设备，其中，第一选择晶体管和第二选择晶体管中的每一个是氧化物薄膜晶体管，并包括：
栅极，形成在下结构上；
栅极绝缘层，形成在下结构和栅极上；
沟道，形成在栅极绝缘层的一部分上，并包括Zn氧化物；
源极和漏极，形成在沟道的端部上。
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