CN101681910A - 具有次表面二极管的集成电路 - Google Patents

具有次表面二极管的集成电路 Download PDF

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CN101681910A
CN101681910A CN200880020977A CN200880020977A CN101681910A CN 101681910 A CN101681910 A CN 101681910A CN 200880020977 A CN200880020977 A CN 200880020977A CN 200880020977 A CN200880020977 A CN 200880020977A CN 101681910 A CN101681910 A CN 101681910A
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CN101681910B (zh
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M·D·丘奇
A·寇尼斯基
L·G·皮尔斯
M·R·杰恩
T·A·裘川
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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Abstract

一种集成电路包括并联的第一和第二二极管。第一二极管具有第一击穿电压，且具有在基片的表面处彼此毗邻的第一P型区和第一N型区，以形成横向二极管。第二二极管具有低于第一击穿电压的第二击穿电压，且具有在基片中彼此横向毗邻的第二P型区和第二N型区，以在表面以下形成横向二极管。第一和第二N型区交迭，而且第一和第二P型区电连接，藉此所述第一和第二二极管并联。

Description

具有次表面二极管的集成电路
背景和发明内容
本发明一般涉及集成电路，更具体地涉及集成电路中的一对并联二极管。
齐纳或雪崩二极管用于限制集成电路中的部件经受的电压。这些二极管是集成电路外部的分立部件，或与要保护的元件一起专门集成在集成电路中。分立二极管增加了部件和印刷电路板层面上的总成本。集成电路齐纳二极管通过增大管芯面积增加了成本。
某些电路寄生具有在快速切换事件期间引起大的电压尖脉冲的人为电感。尤其当晶体管漏到源的导通电阻被最小化时，电压尖脉冲频繁超过集成电路晶体管的击穿(电压)。根据器件的架构，重复的击穿事件导致热载流子电荷被捕获。横向MOS晶体管尤其易受影响。
本公开内容的集成电路包括并联连接的第一和第二二极管。第一二极管具有第一击穿电压，且具有在基片的表面处彼此毗邻的第一P型区和第一N型区，以形成横向二极管。第二二极管具有低于第一击穿电压的第二击穿电压，且具有在基片中彼此横向毗邻的第二P型区和第二N型区，以形成表面以下的横向二极管。第一和第二N型区交迭，而且第一和第二P型区电连接，藉此第一和第二二极管并联。
第二P型和N型区在基片表面以下具有最大杂质浓度。该基片可包括横向绝缘，例如表面中的沟槽，且第二二极管在沟槽以下。第一和第二P型区在基片中可被分隔开，而且通过基片之上的互连电连接。或者第一和第二P型区可交迭以形成电连接。第一和第二P型区可以是邻接表面处的第一N型区和表面以下的第二N型区的公用P型区。公用P型区和N型区在基板表面以下具有最大杂质浓度。
第一P型区可以是横向场效应晶体管的体区，而第一N型区是该场效应晶体管的漏区。该场效应晶体管可以是绝缘栅型场效应晶体管。
当结合附图考虑时，根据本公开内容的以下详细描述，本公开内容的这些和其它方面将变得显而易见。
附图简述
图1是现有技术的集成电路的截面图。
图2是根据本公开内容的第一实施例的包括一对并联二极管的集成电路的截面图。
图3是根据本公开内容的第二和第三实施例的包括一对并联二极管的集成电路的截面图。
图4A-4C分别是图1-3的器件在Vgs＝0伏时的TLP应激响应的曲线图。
图5A-5C分别是图1-3的器件在Vgs＝5伏时的TLP应激响应的曲线图。
图6是图1-3的器件的八个样本的重复TLP响应的表。
优选实施例的详细描述
图1示出了作为集成电路的示例的集成电路10，它包括现有技术的场效应晶体管FET 12，其中能使用本公开内容的次表面二极管。集成电路包括示出具有表面15的高压N型阱的基片14。场效应晶体管12包括在表面15中形成的P型体区16和P型体16中的P型触点18。在P型体16中形成N型区20作为源区。在表面15中形成N型漏区22，并通过基片14的表面区30将N型漏区22与P型体16分隔开。在某些集成电路中，P型区16和N型漏区22可交迭。在N型漏区22的表面15中形成了N型漏接触区24。通过薄栅绝缘或氧化层28将示为多晶区的栅极26与表面15分开。栅26从源区20横跨体区16和基片14的区30的毗邻部分延伸到漏区22上。该结构是横向场效应晶体管的已知示例。
该横截面表示单个场效应晶体管的多个漏区或触臂，或可表示多个并联的场效应晶体管。该场效应晶体管的击穿点在P型体区16与N型漏区22之间的基片14的区30中。在重复击穿事件之后，热载流子电荷被捕获到栅氧化物28中。这种电荷捕获使晶体管的参数随着时间变化。
如图2所示，集成电路10中可包括雪崩二极管40。通过插入雪崩二极管40，破坏了晶体管的周期性。雪崩二极管40包括毗邻N型阴极区44并与之相交的P型阳极区42。阴极区44与漏区22交迭。阳极区42包括基片14的表面15处的P+阳极接触区46。在此具体实施例中，阳极接触区46通过互连50与晶体管12的体16的P型触点18电连接。这将雪崩二极管40置于与体16和漏22形成的横向PN二极管并联。
图2中的示例示出阳极区42与阴极区44的交点处的绝缘材料的沟槽隔离区32。这将雪崩二极管40的击穿移到了基片14的表面区15之下。在沟槽区32的底部52处示出了该击穿区。还应当注意的是，将阳极区42和阴极区44形成为退化区，其中由虚线48表示的最大杂质浓度在基片14的表面15以下。这可通过离子注入以及随后由多个处理步骤引起的扩散来形成。
雪崩二极管40的击穿电压低于区域30处的晶体管的击穿电压。实际上，该结构是两个并联的二极管，其中之一具有低击穿电压和表面下的击穿路径。因此，击穿电流的大部分远离栅氧化物28。因此，减少了栅氧化物中捕获的电荷，所以晶体管漂移最小化。根据阳极区42和阴极区44的结构，雪崩二极管40的反向击穿电压一般将在12到25伏的范围内。还应当注意的是，可将P+阳极触点46嵌入多漏极条形设置中，或将P+阳极触点46制造成晶体管12的P+保护环(未示出)。
图3中示出了两个替代实施例。在图3的右侧，二极管40A的阳极区42A和阴极区44A分别与晶体管12A的体区16和漏区22交迭。这些交迭区在无附加金属互连的情况下建立了两个二极管的并联连接。基片14的区30具有较低的杂质浓度，从而与体区16形成较高的电压结。杂质浓度较高、结电压低的阳极和阴极区42A和44A相交，且具有在表面之下的击穿路径52。阳极区42A和阴极区44A是退化区，它们的最高杂质浓度在基片14的表面15之下的虚线48处。
在图3的左侧，退化区42B和44B与雪崩二极管40B的阳极和阴极区重合，而且不仅形成雪崩二极管40B的阳极和阴极区，而且形成晶体管12B的体区和漏区。至于图2中的实施例，52处的雪崩二极管击穿区在表面15之下，并从栅氧化物28传导出载流子。雪崩电流的大部分扫过漏极和源极体区端子。因为雪崩电流不与栅氧化物相互作用，所以减少了晶体管漂移。
利用已知的CMOS制造技术，集成电路的最大浓度将在离表面15约0.5到2微米处。利用作为已知标准CMOS工艺的一部分的N阱和P阱注入作为示例建立了图2和3的实施例。通过增加专用的漏极/阴极注入和/或体/阳极注入，能实现进一步的器件优化。
在图4到6中示出了与现有技术相比的各个实施例的响应。对照器件是现有技术图1的器件，实施例1是图2的器件的响应，以及实施例2是图3的晶体管12B和二极管40B的响应。图4A到4C和5A到5C分别示出了在0伏和5伏的栅到源电压下的TLP应激响应。
图6是所制造和测试的八个样本在每两秒100纳秒的100微安电流和0伏的栅到源电压下的重复TLP应激响应的表。实施例2的样本1的失效是不可重现的。
根据这些曲线图，可以看出本次表面雪崩二极管提供晶体管的改善性能和长寿命。
即使已经设计和展示了本结构用作场效应晶体管的保护器件，但该次表面雪崩二极管可用于其它二极管结构，以保护其它结构免受电压尖脉冲，尤其是重复的电压尖脉冲。
虽然已经具体描述和示出了本公开内容，但容易理解的是，这仅仅是以说明和示例而不是限制的方式进行的。本发明的范围仅受所附权利要求的术语限制。

Claims (10)

1.一种集成电路，包括：
具有表面的基片；
具有第一击穿电压的第一二极管，所述第一二极管具有在所述基片的所述表面处彼此毗邻的第一P型区和第一N型区以形成横向二极管；
具有低于所述第一击穿电压的第二击穿电压的第二二极管，所述第二二极管具有在所述基片中彼此横向毗邻的第二P型区和第二N型区以在所述表面以下形成横向二极管；以及
所述第一和第二N型区交迭，而且所述第一和第二P型区电连接，藉此所述第一和第二二极管并联。
2.如权利要求1所述的集成电路，其特征在于，所述第二P型和N型区在所述基片的所述表面以下具有最大杂质浓度。
3.如权利要求1所述的集成电路，其特征在于，所述基片包括在所述表面中的绝缘沟槽，而且所述第二二极管在所述沟槽之下。
4.如权利要求1所述的集成电路，其特征在于，所述第一和第二P型区在所述基片中被分隔开，而且通过所述基片之上的互连电连接。
5.如权利要求1所述的集成电路，其特征在于，所述第一和第二P型区交迭以形成电连接。
6.如权利要求1所述的集成电路，其特征在于，所述第一和第二P型区是邻接所述表面处的所述第一N型区和所述表面以下的所述第二N型区的公用P型区。
7.如权利要求6所述的集成电路，其特征在于，所述公用P型区和所述N型区在所述基片的所述表面以下具有最大杂质浓度。
8.如权利要求1所述的集成电路，其特征在于，所述第一P型区是横向场效应晶体管的体区，而所述第一N型区是所述场效应晶体管的漏区。
9.如权利要求8所述的集成电路，其特征在于，所述场效应晶体管是绝缘栅型场效应晶体管。
10.如权利要求1所述的集成电路，其特征在于，所述第一P和N型区与CMOS横向场效应晶体管的阱区结构相同。
CN2008800209772A 2007-06-21 2008-03-28 具有次表面二极管的集成电路 Expired - Fee Related CN101681910B (zh)

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US12/037,569 US7700977B2 (en) 2007-06-21 2008-02-26 Integrated circuit with a subsurface diode
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CN101681910B (zh) 2011-12-21
TW200901438A (en) 2009-01-01
EP2160764A1 (en) 2010-03-10
US20080315329A1 (en) 2008-12-25
US7700977B2 (en) 2010-04-20
KR20100031701A (ko) 2010-03-24
WO2008156888A1 (en) 2008-12-24

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