TW200901438A - Integrated circuit with a subsurface diode - Google Patents

Integrated circuit with a subsurface diode Download PDF

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Publication number
TW200901438A
TW200901438A TW097110951A TW97110951A TW200901438A TW 200901438 A TW200901438 A TW 200901438A TW 097110951 A TW097110951 A TW 097110951A TW 97110951 A TW97110951 A TW 97110951A TW 200901438 A TW200901438 A TW 200901438A
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type region
region
integrated circuit
diode
substrate
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TW097110951A
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Michael David Church
Alexander Kalnitsky
Lawrence George Pearce
Michael Ray Jayne
Thomas Andrew Jochum
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Intersil Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

200901438 九、發明說明： 【發明所屬之技術領域】 本揭示内容大體上係關於積體電路，且更特定山 係關於積體電路中之一對並聯二極體。 < 而5 ’ 【先前技術】 齊納二極體或雪崩二極體用以限制由積體電路中之名 件所經受之電壓。此等二極體為籍栌φ 濃 马積體電路外部的離散組 件，或與其待保護之元件一起特別整合至積體電路中。離 散：極體增加組件及印刷電路板層面下的總成本。積體電 路齊納二極體由於增加晶粒面積而增加成本。 某些寄生電路具有在快速切換事件期間導致較大電壓 尖峰之有意電感（intentional inductance)。電壓尖峰經常 超過積體電路電晶體的崩潰’當最小化電晶體汲極至源極 導通電阻時尤為如此。視裝置之架構而定，重複崩潰事件 導致熱載子電荷被截獲。橫向M〇s電晶體特別易受影響。 【發明内容】 本揭示内容之一種積體電路包括並聯連接之第一二極 體及第二二極體。第一二極體具有一第一崩潰電壓且具有 在基板之表面處彼此鄰近以形成橫向二極體的第一 p型區 域及第一N型區域。第二二極體具有一小於第一崩潰電壓 之第朋/貝電壓’且具有在基板中彼此橫向鄰近以在表面 下开/成仏向—極體之第二p型區域及第二N型區域。第— 7 200901438 N型區域與第二N型區域重疊，且第一 p型區域與第二p 型區域電連接，藉此第一二極體與第二二極體並聯。 第一P型區域及N型區域在基板之表面下具有一最大 雜貝/辰度。基板可包括一橫向絕緣（例如，表面中之溝槽）， 且第二二極體在該溝槽下。第一 p型區域與第二p型區域 可在基板中隔開且由基板上之互連電連接。第一 p型區域 與第二P型區域或者可重疊以形成電連接。第一 p型區域 及第二P型區域可為鄰接在表面處之第一 N型區域與在表 面下之第二N型區域的共同P型區域。共同卩型區域及n 型區域在基板之表面下具有一最大雜質濃度。
第一 P型區域可為橫向場效電晶體之本體，且第—N 型區域為場效電晶體的汲極區域。場效電晶體可為絕緣閘 場效電晶體。 ¥ 本揭示内容的此等及其他態樣將自當結合隨附圖式所 考慮時之本揭示案之以下實施方式變得顯而易見。 【實施方式】 圖1說明作為可使用本揭示案之次表面二極體之 電路之實例的包括先前技術之場效電晶體FET 12之積— 電路10。積體電路包括一展示為具有一表面15之高壓: 型井的基板14。場效電晶體12包括一形成於表面15中 p型本體區域16,及一在P型本體16内之p型接觸u N型區域20形成於P本體16中作為源極區域。n型及^ 區域22形成於表δ 15中且藉由基板14的表面區域心 8 200901438 P本體16隔關。+甘 、、 汗’在某些積體電路中，P型區域16與>1型 >及極區域22可舌晶 且。N型汲極接觸區域24形成於N型汲 極區域22之砉而“丄 中。展不為多晶區域之閘極26藉由 二；絕緣或氧化層28與表面15分離。閘極26自源極 二伸跨越本體區域16及基板Η之區域3G之鄰近 β分且至汲極區域 — 上。該、、、α構為橫向場效電晶體之已 知貫例。 。橫截面表示單-場效電晶體之多沒極或指狀結構，或 ::複數個並聯場效電晶體。場效電晶體之崩潰點處於 :反Μ之在Ρ本體區域“與㈣極區域μ之間的區域川 。熱載子電荷在重複崩潰事件後被截獲於閘氧化物Μ 中。此電荷截獲隨時間改變電晶體之參數。 雪崩二極體4G可包括於如圖2中所說明之積體電路1〇 ^電曰曰體之週期性由於雪崩二極體40之插入而受到破 二。雪崩二極體40包括一鄰近Ν型陰極區域44且與其相 又之ρ型陽極區域42。陰極區域44重疊汲極區域22。陽 極區域42包括在基板14之表面15處之一 ρ +陽極接觸區 域46。在此特別實施例中，陽極接觸區域柄藉由互連％ 與電晶體12之本體16的ρ接觸18電連接。此並聯於由 本體16及汲極22所形成之橫向ρΝ二極體來置放雪崩二 極體40。 圖2中之實例展示在陽極區域42與陰極區域44之相 交處之絕緣材料的溝槽隔離區域32。此區域將雪崩二極體 之崩潰移動至基板14之表面區域15下。該崩溃區域說 9 200901438 明於溝槽區域32之底部處的52處。應亦注意，陽極區域 42及陰極區域44形成為逆行區域，其中最大雜質濃度（由 虛線48所說明）在基板14之表面15下。此可由離子植 入與由各種處理步驟導致之後續擴散形成。
雪崩二極體40之崩潰電壓小於在區域3()處之電晶體 之崩潰電塵。實際上，該結構為兩個並聯二極體，其中該 等二極體中之一者具有一低崩潰電壓及一次表面崩潰路 徑。因此’大部分崩潰電流遠離閘氧化物28。因此，閘氧 化物中之被截獲電荷減少，因此電晶體漂移最小。雪崩二 極體40之反向崩潰電壓視陽極區域U及陰極區域44之 結構而將通常在12伏特至25伏特的範圍内。應亦注意， P +陽極接觸46可肷入至多汲極條帶配置中或可製造成電 晶體12(圖中未示）之p+保護環。 圖3中展不兩個替代實施例。在圖3之右側中，二極 體40A之陽極區域42A及陰極區域44A分別與電晶體12A 之本體區域16及没極區域22重疊。此等重疊區域在無額 外金屬互連之情況下產生兩個二極體之並聯連接。基板14 之區域30具有一較低雜質濃度，從而形成與本體區域16 之較南電壓接面。較而雜質漢度、低接面電壓陽極與陰極 區域42A與44A相父且在表面下具有一崩潰路徑52。陽 極區域42A及陰極區域44A為逆行區域，該等逆行區域在 基板14之表面15下於虛線48處具有其最高雜質濃度。 在圖3之左側上’逆行區域42B及44B相符合，且不 僅形成雪崩二極體40B之陽極及陰極區域而且形成電晶體 10 200901438 12B的本體及汲極區域。如同圖2中之實施例一樣，在52 處之雪崩二極體崩潰在表面15下且將載子導離閘氧化物 28大°卩分雪朋電流經由没極及源極本體端子得以清除。 因為雪崩電流並不對閘氧化物有影響，所以電晶體漂移得 以減少。 使用已知CMOS製造技術，積體電路之最大濃度將在 表面15約〇.5微米至2微米處。已使用NWELL及PWELL 植入肜成圖2及圖3之實施例，NWELL及PWELL植入作 為貫例為已知標準CM〇s製程的部分。可藉由添加專用汲 極/陰極植入及/或本體/陽極植入來達成進一步裝置最佳 化。
圖4至圖6中說明相較於先前技術之各種實施例的回 應？制裝置為先前技術圖！之控制裝置，實施例【為圖 2 ^貫施例，且實施例2為3之電晶體12B及二極體_ 的貫施例。圖4A至4C及5A至5C分別展示在零伏特及 、特之閘極至源極電壓下之Tlp應力回應。 T 6為針對在每兩秒之每1〇〇奈秒1〇〇微安的電流及 特之閘極至源極電壓下之重i TLp應力回應所建置及 再二八個樣本的表格。實施例2之樣本1之失敗為不可 此荨曲線圖，可見本次表 駔捉供電晶體 之改良效能及使用壽命 即使本結構已經設計並展示用作場效電晶體之保 但是次表面雪崩二極體亦可用於其他二極體結構以： 11 200901438 護其他結構免於電塵尖峰且特定而言免於重複電壓尖峰。 儘管已詳細描述並說明了本揭示内容，但將清楚理解 w係、僅作為說明及實例料行且將並*料限制來實 抛。本揭不内容之範疇將僅由隨附申請專利範圍之項來限 制。 【圖式簡單說明】 圖1為先前技術之積體電路的橫截面圖。 圖2為根據本揭示案之第一實施例之包括一對並聯二 極體之積體電路的橫截面圖。 圖3為根據本揭示案之第二實施例及第三實施例之包 括一對並聯二極體之積體電路的横截面圖。 圖4A-4C分別為圖1_3之裝置之在Vgs=0伏特下之 TLP應力回應的曲線圖。 圖5A-5C分別為圖1_3之裝置之在Vgs=5伏特下之 TLP應力回應的曲線圖。 圖6為圖1-3之裝置之八個樣本之重複TLP回應的表 格0 【主 要元件符號說明】 10 ： 積體電路 12 ： 3暴效電晶體 12A :電晶體 12B :電晶體 12 200901438 14 :基板 15 :表面 1 6 : P型本體區域 1 8 : P型接觸件 20 : N型區域 22 : N型汲極區域 24 : N型汲極接觸區域 26 :閘極 ^ 28 :薄閘極絕緣/閘氧化物 3 0 :表面區域 32 :溝槽隔離區域 40 :雪崩二極體 40A :二極體 42 : P型陽極區域 42A :陽極區域 42B :逆行區域 44 : N型陰極區域 44A :陰極區域 44B :逆行區域 46 : P+陽極接觸區域 48 :虛線 5 0 :互連 52 :崩潰區域 13

Claims (1)

  1. 200901438 十、申請專利範固： l一種積體電路，其包含： 一基板，其具有一表面； 7第—二極體’其具有U潰電^具有在該基 板之該表面處彼此鄰近以形成一橫向二極體的第一 P 域及第一 N型區域； …一第二二極體’其具有-小於該第-崩潰電壓之第二
    朋〉貝電壓，且具有在該基板中彼此橫向鄰近以在該表面下 形成一橫向二極體之-第二P型區域及-第二N型區域； 及 該第- N型區域與該第二N型區域重疊，且該第一 p 型區域與該第二p型區域電 ， 逆按精此該第一二極體與該 第二二極體並聯。 2·如申呀專利範圍第1項之積體電路，其中該第二p 型區域及該第=N型區域在該基板之該表面下 雜質濃度。 ，、π取八 3.如申請專利範圍"項之積體電路，其中該基板包 括在該表面中之-絕緣溝槽，且該第二二極體在該溝槽 下。 4.如申請專利範圍帛1項之積體電路，纟中該第—P 型區域與該第二P剞區诚 i (_域在g亥基板中隔開且由該基板上之 互連電連接。 如申明專利範圍第i項之積體電路，其中該第一 P 型區域與該第二p型區域重疊以形成該電連接。 14 200901438 6:如申請專利範圍帛1項之積體電路，其中該第一 P 型區域及該第二P型區域為鄰接在該表面處之該第-N型 區亥表面下之該第二N型區域的一共同p型區域。 7. 如申請專利範圍帛6項之積體電路，《中該共同p 型區域及該N型區域在該基板之該表面下具有一最大雜質 濃度。 8. 如申請專利範圍第丨項之積體電路，其中該第一 p 广 型區域為一橫向場效電晶體之一本體，且該第一 N型區域 、 為該場效電晶體的一汲極區域。 9. 如申請專利範圍第8項之積體電路，其中該場效電 晶體為一絕緣閘場效電晶體。 10. 如申請專利範圍第1項之積體電路，其中該第一 p 型區域及該第一 N型區域為與CMOS橫向場效電晶體之井 區域相同的結構。 Η一、圈式： 如次頁 15
TW097110951A 2007-06-21 2008-03-27 Integrated circuit with a subsurface diode TW200901438A (en)

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US20110121387A1 (en) * 2009-11-23 2011-05-26 Francois Hebert Integrated guarded schottky diode compatible with trench-gate dmos, structure and method
US20110156682A1 (en) * 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US20110156810A1 (en) * 2009-12-30 2011-06-30 Intersil Americas Inc. Integrated dmos and schottky
US8492225B2 (en) * 2009-12-30 2013-07-23 Intersil Americas Inc. Integrated trench guarded schottky diode compatible with powerdie, structure and method
JP2014056989A (ja) 2012-09-13 2014-03-27 Toshiba Corp 半導体記憶装置
CN106449634B (zh) 2016-09-23 2019-06-14 矽力杰半导体技术(杭州)有限公司 瞬态电压抑制器及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6377155A (ja) 1986-09-19 1988-04-07 Fujitsu Ltd オ−プンドレイン出力回路
US4736271A (en) 1987-06-23 1988-04-05 Signetics Corporation Protection device utilizing one or more subsurface diodes and associated method of manufacture
FR2684240B1 (fr) 1991-11-21 1994-02-18 Sgs Thomson Microelectronics Sa Transistor mos a zener de protection integree.
FR2688942A1 (fr) * 1992-03-20 1993-09-24 Sgs Thomson Microelectronics Diode a avalanche enterree.
JP3173268B2 (ja) 1994-01-06 2001-06-04 富士電機株式会社 Ｍｉｓ電界効果トランジスタを備えた半導体装置
SE512661C2 (sv) * 1996-11-13 2000-04-17 Ericsson Telefon Ab L M Lateral bipolär hybridtransistor med fälteffektmod och förfarande vid densamma
JP3090081B2 (ja) 1997-03-12 2000-09-18 日本電気株式会社 半導体装置
GB9921071D0 (en) * 1999-09-08 1999-11-10 Univ Montfort Insulated base transistor
GB9921068D0 (en) * 1999-09-08 1999-11-10 Univ Montfort Bipolar mosfet device
US7056761B1 (en) * 2003-03-14 2006-06-06 National Semiconductor Corporation Avalanche diode with breakdown voltage controlled by gate length
DE102004026100B4 (de) * 2004-05-25 2007-10-25 Infineon Technologies Ag ESD-Schutzstrukturen für Halbleiterbauelemente
TWI233688B (en) * 2004-08-30 2005-06-01 Ind Tech Res Inst Diode structure with low substrate leakage current and applications thereof
US7250668B2 (en) 2005-01-20 2007-07-31 Diodes, Inc. Integrated circuit including power diode
JP4927340B2 (ja) 2005-02-24 2012-05-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP4785113B2 (ja) 2005-02-24 2011-10-05 オンセミコンダクター・トレーディング・リミテッド 半導体装置

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EP2160764A1 (en) 2010-03-10
CN101681910A (zh) 2010-03-24
US7700977B2 (en) 2010-04-20
CN101681910B (zh) 2011-12-21
KR20100031701A (ko) 2010-03-24
WO2008156888A1 (en) 2008-12-24
US20080315329A1 (en) 2008-12-25

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