CN101674093A - Two-stage realization method of convolutional interleave and device thereof - Google Patents
Two-stage realization method of convolutional interleave and device thereof Download PDFInfo
- Publication number
- CN101674093A CN101674093A CN 200910093770 CN200910093770A CN101674093A CN 101674093 A CN101674093 A CN 101674093A CN 200910093770 CN200910093770 CN 200910093770 CN 200910093770 A CN200910093770 A CN 200910093770A CN 101674093 A CN101674093 A CN 101674093A
- Authority
- CN
- China
- Prior art keywords
- branch road
- order
- level
- address
- interweaves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention relates to a digital communication system, in particular to a two-stage realization method of convolutional interleave and a device thereof. The method is realized by the following steps: dividing the traditional convolutional interleave with the delay of a circuit branch i being i multiplied by M into first stage convolutional interleave with the delay of the circuit branch i beingmod (i, N) multiplied by M and second stage convolutional interleave with the delay of the circuit branch i being (i minus mod (i, N)) multiplied by M, respectively converting the two stages of interleave into a standard convolutional interleaving form, and conducting the read and write of corresponding address sequence through an on-chip memory of the first stage interleave and an off-chip memoryof the second stage interleave. Under the situation of ensuring a small scale of an on-chip register, the method and the device realize a great amount of storage space by using the off-chip memory, decrease the cost for realizing chips, improve the read-write efficiency of the off-chip memory and are widely applicable to the convolutional interleave and deinterleave of digital communication systems.
Description
Technical field
The present invention relates to digital communication system, relate in particular to convolutional interleave.
Background technology
In digital communication system, data are transmitted in channel and are tended to be subjected to burst noise to disturb, thereby produce a large amount of error codes continuously.In order to make the error burst discretization, improve the chnnel coding error correcting capability, can in transmitter, use the relative position of interleaver usually, and in receiver, use corresponding deinterleaver to come the restore data order with the change data.Convolutional interleave is the most frequently used deinterleaving method, and the convolutional interleave method is referring to Fig. 1, and Fig. 1 is the convolutional interleave schematic diagram.Wherein, B represents weaving width, and M represents interleave depth, and finishing interweaves, and to need the data in buffer number be B (B-1) M/2.Convolution de-interleaving is the inverse process of convolutional interleave, and convolution de-interleaving is referring to Fig. 2, and Fig. 2 is the convolution de-interleaving schematic diagram.Deinterleaving and to interweave be comparatively speaking, its difference only is the delay difference of each branch road, finishing deinterleaving needs the data in buffer number also to be B (B-1) M/2.
In the byte-interleaved of European digital video-frequency broadcast standard DVB, weaving width B=12, interleave depth M=17.In the symbol interleaving of China Digital TV terrestrial broadcasting standard DTMB, weaving width B=52, interleave depth M=240 or M=720.When weaving width and the degree of depth are big, realize that the memory cell scale that interweaves required is also very big, be difficult to be integrated in chip internal, must use external memory storage, as SDRAM and DDR etc.But need extra clock to control because chip external memory sequential such as SDRAM require every initiation once to read and write, if only read and write data at every turn, read-write efficiency is too low, thereby can't satisfy the real time data processing requirement.
A kind of denomination of invention is to utilize external memory storage to realize the Chinese patent of the method and apparatus publication number of convolutional interleave/deinterleaving for CN101237240A, has proposed a kind of chip external memory that utilizes and has realized convolutional interleave reconciliation interweaving method.This method is read and write chip external memory by interface after by buffer in the sheet data being carried out buffer memory more in batches, has improved the read-write efficiency of chip external memory.Yet this method is only applicable in the bigger convolutional interleave scheme of interleave depth, when interleave depth is very little, will become very little by the quantity that reads and writes data of the batch behind the buffer memory in the sheet, and this method is with inapplicable.
Summary of the invention
The invention provides a kind of convolutional interleave two-stage realization method and device thereof that can overcome the above problems.
In first aspect, the invention provides a kind of deinterleaving method, this method satisfies B=KN (B, N, K are positive integer) and i branch road with weaving width B and postpones that the first order interweaves and the second level interweaves for interweaving of i * M is divided into.This method at first will interweave, and (i, N) * M, (first order of 0≤i≤KN-1) interweaves and obtains the first order interleaved data stream input traffic, and carries out the implementing reading and writing of appropriate address order by the on-chip memory that this first order interweaves for mod through postponing.And then with this first order interleaved data stream through postponing for (i-mod (i, N)) * M, (second level of 0≤i≤KN-1) interweaves and obtains interweaving output stream, and carries out the implementing reading and writing of appropriate address order by the chip external memory that this second level interweaves.
In second aspect, the invention provides a kind of interleaver, this interleaver weaving width B satisfies B=KN (B, N, K are positive integer) and this interleaver comprises first order interleaver and second level interleaver.
This first order interleaver comprises the first read/write address generation unit, and this first read/write address generation unit is used to produce the read/write address of on-chip memory, and the read/write address of this on-chip memory is A
N+1=(A
n+ nKM) modN
AWherein, n be this first order interleaving data correspondence the branch road sequence number, A
nBe n branch road reading and writing data address, N
ABe the required memory address sum of on-chip memory.
This second level interleaver comprises second reading write address generation unit, and this second reading write address generation unit is used to produce the read-write initial address of chip external memory, and the read-write initial address of this chip external memory is A
M+1=Lmod (A
m/ L+mNM, N
B/ L).Wherein, m be this second level interleaving data piece correspondence the branch road sequence number, A
mBe this m branch road data block read-write initial address, N
BBe the required memory address sum of chip external memory, L is that the second level, equivalence back interlace assignment is given the address space of each data block.
In one embodiment of the invention, this first order on-chip memory address sum N that interweaves
AFor
In another embodiment of the present invention, this second level chip external memory address sum N that interweaves
BFor
The present invention is the circuit-switched data with same delay by the first order will the have different branch road data conversion that postpone that interweave, thereby the multiple branch circuit data are merged into one circuit-switched data, and with this circuit-switched data as the second level input that interweaves, read and write in batches again.The present invention has improved the chip external memory read-write efficiency, has reduced the requirement to chip external memory read-write clock frequency, and buffer small scale in the sheet, has reduced chip and has realized cost.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:
Fig. 1 is the convolutional interleave schematic diagram;
Fig. 2 is the convolution de-interleaving schematic diagram;
Fig. 3 is that the convolutional interleave classification of present embodiment realizes schematic diagram;
Fig. 4 is the first order convolutional interleave equivalenceization schematic diagram of present embodiment;
Fig. 5 is the first order interleaver circuitry structure chart of present embodiment;
Fig. 6 is the second level convolutional interleave equivalenceization schematic diagram of present embodiment;
Fig. 7 is the second level interleaver circuitry structure chart of present embodiment.
Embodiment
The weaving width of supposing convolutional interleave is B, and interleave depth is M, and satisfies B=KN, and wherein B, K, N are positive integer.
Fig. 3 is that the convolutional interleave classification of present embodiment realizes schematic diagram.Fig. 3 is cut apart Fig. 1 convolutional interleave, thus the two-stage convolutional interleave that obtains.
As shown in Figure 1, the delay of traditional convolutional interleave i branch road is i * M, and the delay of (as shown in Figure 3) the i branch road of the convolutional interleave after the classification in the first order interweaves is that (i, N) * M, the delay in the second level interweaves is (i-mod (i, N)) * M to mod.
Particularly, the present invention with width be B i branch road postpone for i * M be the degree of depth be M (as shown in Figure 1) interleaved data stream through delay for mod (i, N) * M, (first order of 0≤i≤KN-1) interweaves, and obtains first order interleaved data stream (as Fig. 3 left side); And then with this first order interleaved data stream through postponing for (i-mod (i, N)) * M, (second level of 0≤i≤KN-1) interweaves the output stream that obtains interweaving (as Fig. 3 right side).Just, to postpone convolutional interleave for i * M is divided into and postpones to be mod (i, N) * first order convolutional interleave of M and postpone to be (i-mod (i, N)) * second level convolutional interleave of M, and realize by the read-write of carrying out the appropriate address order at first order convolutional interleave memory and second level convolutional interleave memory respectively.
Among Fig. 3, the first order being interweaved all postpone additions, is KN (N-1) M/2 thereby obtain the required memory size of first order interleaver; The second level interweaved, and all postpone additions, are K (K-1) N thereby obtain the required memory size of second level interleaver
2M/2, second level memory size with the ratio of first order memory size is
Because N approximates N-1, according to formula
As can be known, the big more second level of K memory size is big more with the ratio of first order memory size.Therefore can be by magnitude relationship between configuration K control second level memory and the first order memory, realize that with the small-scale on-chip memory first order interweaves, realize that with large-scale chip external memory the second level interweaves, thereby solve the problem that chip is realized cost and chip external memory read-write efficiency.
Fig. 4 is the first order convolutional interleave equivalenceization schematic diagram of present embodiment, in this first order convolutional interleave, to have the same delay branch road merges, thereby with width is that KN and i branch road postpone to be mod (i, N) * M, (first order of 0≤i≤KN-1) interweaves, and to be converted into width be that N i branch road postpones to be iKM, and (0≤i≤N) is that the degree of depth is the standard convolutional interleave form of KM.
Concrete first order convolutional interleave equivalent method is, is 0 the 0th branch road, N branch road with delay ... the equivalence of K (N-1) branch road is that a delay is 0 the 0th branch road; The 1st branch road, the N+1 branch road of M will be postponed to be ... the equivalence of K (N-1)+1 branch road is that a delay is the 1st branch road of KM; N-1 branch road, 2N-1 branch road, the equivalence of KN-1 branch road that will postpone for (N-1) M are the N-1 branch road of a delay for (N-1) KM.
Fig. 5 is the first order interleaver circuitry structure chart of present embodiment, and this first order interleaver comprises the first branch road counter 510, the first read/write address generation unit 520, on-chip memory 530.
The first branch road counter 510 be its count value of mould N cycle counter from 0 to N-1, and this first branch road counter 510 is used for the branch road sequence number of this first order interleaver is counted judging branch road under this first order interleaver input data, and should affiliated branch road sequence number be sent to the first read/write address generation unit 520.
The first read/write address generation unit 520 produces the read/write address of on-chip memory according to the count value of the first branch road counter 510, and this read/write address is sent to on-chip memory 530.
Particularly, suppose that n branch road data write address is A
n, then n+1 branch road data write address is
A
n+1＝(A
n+nKM)modN
A (1)
On-chip memory 530 is used for buffer memory first order interleaving data.The on-chip memory of present embodiment adopts whole loop shifting, and promptly the memory address space of each branch road input data in on-chip memory 530 is unfixing, but in whole cyclic shift, the data of every branch road are all read according to the read signal of next branch road.This method need increase the memory space of 1 data so that realize whole cyclic shift.Therefore actual required on-chip memory address adds up to,
By formula (2) as can be known, under weaving width B and the constant situation of interleave depth M, sheet storage internal size is only relevant with N.The big more then on-chip memory of N scale is big more; Simultaneously the second level annexable branch road that interweaves is many more, and the present embodiment second level chip external memory that interweaves adopts reading/writing method in batches, so the second level read-write efficiency that interweaves is high more.Otherwise in like manner.Therefore can between on-chip memory scale and chip external memory read-write efficiency, trade off according to actual conditions and choose a suitable N value.
Fig. 6 is the second level convolutional interleave equivalenceization schematic diagram of present embodiment, in this second level convolutional interleave, postponing identical branch road equivalence with every adjacent N is that a branch road is handled, thereby with width is that KN i branch road postpones to be (i-mod (i, N)) * M, (it is that K i branch road postpones to be iNM that the second level convolutional interleave of 0≤i≤KN-1) is converted into width, and (0≤i≤K) is that the degree of depth is the standard intertexture form of NM.At this moment, an adjacent N circuit-switched data has changed into a data block before the equivalence.
Concrete second level convolutional interleave equivalent method is, with the 0th branch road, the 1st branch road ... the equivalence of N-1 branch road is the 0th branch road; With N branch road, N+1 branch road ... the equivalence of 2N-1 branch road is the 1st branch road; With K (N-1) branch road, K (N-1)+1 branch road ... the equivalence of KN-1 branch road is the K-1 branch road.
Fig. 7 is the second level interleaver circuitry structure chart of present embodiment, and this second level interleaver comprises the second branch road counter 710, second reading write address generation unit 720, interface controller 730, chip external memory 740.
The second branch road counter 710 be its count value of mould K cycle counter from 0 to K-1, and this second branch road counter 710 is used for the branch road sequence number of this second level interleaver is counted judging branch road under this second branch road counter input block, and should under the branch road sequence number be sent to second reading write address generation unit 720.
Second reading write address generation unit 720 produces the read-write initial address of chip external memory according to the count value of the second branch road counter 710, and is sent to this external memory 740 of sheet by interface controller 730.
Particularly, the read-write initial address of supposing m branch road data block is A
m, then the read-write initial address of m+1 branch road data block is,
A
m+1＝L·mod(A
m/L+mNM，N
C) (3)
Wherein,
Interface controller 730 is used for signal and chip external memory in the brace, and requires generation the corresponding interface signal to read and write with control data according to the sequential of chip external memory.
Chip external memory 740 is used for buffer memory second level interleaving data.The chip external memory 740 of present embodiment adopts whole loop shifting, and its actual required address adds up to,
Wherein, L be distribute to the second level, equivalence back interweave in the address space of each data block.
Need to prove that de-interweaving method and deinterleaving method are identical, the deinterleaver hardware architecture is also identical with the interleaver hardware configuration, therefore no longer de-interweaving method of the present invention and corresponding deinterleaver is given unnecessary details herein.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (13)
1. deinterleaving method, the weaving width B of this method satisfy B=KN (B, N, K are positive integer) and the i branch road postpones to be i * M, comprise,
With described interleaved data stream through the i branch road postpone for mod (i, N) * M, (first order of 0≤i≤KN-1) interweaves and obtains first order interleaved data stream, and carries out the implementing reading and writing of appropriate address order by the on-chip memory that this first order interweaves; It is to be that B i branch road postpones to interweave for being divided into the first order of two-stage in interweaving interweaving of i * M with width that the wherein said first order interweaves;
And then this first order interleaved data stream postponed to be (i-mod (i through the i branch road, N)) * M, (second level of 0≤i≤KN-1) interweaves and obtains the output stream that interweaves, and carries out the implementing reading and writing of appropriate address order by the chip external memory that this second level interweaves; It is to be that B i branch road postpones to interweave for being divided into the second level of two-stage in interweaving interweaving of i * M with width that the wherein said second level interweaves.
2. a kind of deinterleaving method as claimed in claim 1, it is characterized in that, comprise with described width be KN and i branch road postpone for mod (i, N) * M, (first order of 0≤i≤KN-1) interweaves, and to be converted into width be that N i branch road postpones to be iKM, and (0≤i≤N) interweaves.
3. a kind of deinterleaving method as claimed in claim 1, it is characterized in that, comprise with described width being that KN and i branch road postpone to be (i-mod (i, N)) * M, (second level of 0≤i≤KN-1) interweaves, and to be converted into width be that K i branch road postpones to be iNM, and (0≤i≤K) interweaves.
4. a kind of deinterleaving method as claimed in claim 1 is characterized in that, the described first order on-chip memory read/write address that interweaves is,
A
n+1＝(A
n+nKM)mod?N
A
Wherein, n is the branch road sequence number of this first order interleaving data correspondence, A
nBe n branch road reading and writing data address, N
ABe the required memory address sum of on-chip memory.
5. a kind of deinterleaving method as claimed in claim 1 is characterized in that, the described second level chip external memory read-write initial address that interweaves is,
A
m+1＝L·mod(A
m/L+mNM，N
B/L)
Wherein, m is the branch road sequence number of this second level interleaving data piece correspondence, A
mBe m branch road data block read-write initial address, N
BBe the required memory address sum of chip external memory, L is that the second level, equivalence back interlace assignment is given the address space of each data block.
6. a kind of deinterleaving method as claimed in claim 1 is characterized in that, the described first order on-chip memory address sum N that interweaves
AFor
7. a kind of deinterleaving method as claimed in claim 1 is characterized in that, the described second level chip external memory address sum N that interweaves
BFor
8. interleaver, the weaving width B of this interleaver satisfy B=KN (B, N, K are positive integer) and the i branch road postpones to be i * M, it is characterized in that, comprises first order interleaver and second level interleaver;
Described first order interleaver comprises the first read/write address generation unit, and this first read/write address generation unit is used to produce the read/write address of on-chip memory, and the read/write address of this on-chip memory is,
A
n+1＝(A
n+nKM)mod?N
A
Wherein, n is the branch road sequence number of this first order interleaving data correspondence, A
nBe n branch road reading and writing data address, N
ABe the required memory address sum of on-chip memory;
Described second level interleaver comprises second reading write address generation unit, and this second reading write address generation unit is used to produce the read-write initial address of chip external memory, and the read-write initial address of this chip external memory is,
A
m+1＝L·mod(A
m/L+mNM，N
B/L)
Wherein, m is the branch road sequence number of this second level interleaving data piece correspondence, A
mBe this m branch road data block read-write initial address, N
BBe the required memory address sum of chip external memory, L is that the second level, equivalence back interlace assignment is given the address space of each data block.
9. a kind of interleaver as claimed in claim 8, it is characterized in that, described first order interleaver comprises the first branch road counter, and this first branch road counter is a count value from 0 to N-1 mould N cycle counter, is used for the branch road sequence number of this first order interleaver is counted.
10. a kind of interleaver as claimed in claim 8 is characterized in that, described on-chip memory is used for buffer memory first order interleaving data, and this on-chip memory address sum N
AFor
11. a kind of interleaver as claimed in claim 8, it is characterized in that, described second level interleaver comprises the second branch road counter, and this second branch road counter is a count value from 0 to K-1 mould K cycle counter, is used for the branch road sequence number of this second level interleaver is counted.
12. a kind of interleaver as claimed in claim 8 is characterized in that, described second level interleaver comprises interface controller, is used for signal and chip external memory in the brace.
13. a kind of interleaver as claimed in claim 8 is characterized in that, described chip external memory is used for buffer memory second level interleaving data, and this chip external memory address sum N
BFor
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910093770 CN101674093B (en) | 2009-09-28 | 2009-09-28 | Two-stage realization method of convolutional interleave and device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910093770 CN101674093B (en) | 2009-09-28 | 2009-09-28 | Two-stage realization method of convolutional interleave and device thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101674093A true CN101674093A (en) | 2010-03-17 |
| CN101674093B CN101674093B (en) | 2013-05-01 |
Family
ID=42021121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910093770 Expired - Fee Related CN101674093B (en) | 2009-09-28 | 2009-09-28 | Two-stage realization method of convolutional interleave and device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101674093B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103209046A (en) * | 2012-01-13 | 2013-07-17 | 上海华虹集成电路有限责任公司 | China mobile multimedia broadcasting (CMMB) bit de-interleaving device and method |
| CN104993837A (en) * | 2015-07-24 | 2015-10-21 | 丽水博远科技有限公司 | Convolutional interleaving method and convolutional interleaver |
| CN105099599A (en) * | 2014-04-16 | 2015-11-25 | 澜起科技（上海）有限公司 | Interleaving method, de-interleaving method and corresponding devices |
| CN103916140B (en) * | 2014-04-18 | 2017-03-22 | 上海高清数字科技产业有限公司 | Method and device for achieving convolution interleave/de-interleave |
| CN110637297A (en) * | 2017-04-27 | 2019-12-31 | 苹果公司 | Convolution engine with per-channel processing of interleaved channel data |
| CN111628787A (en) * | 2020-05-25 | 2020-09-04 | 武汉高德红外股份有限公司 | Method and system for realizing convolution interleaving and de-interleaving FPGA (field programmable Gate array) without redundant data |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101237240B (en) * | 2008-02-26 | 2011-07-20 | 北京海尔集成电路设计有限公司 | A method and device for realizing cirrocumulus interweaving/de-interweaving based on external memory |
-
2009
- 2009-09-28 CN CN 200910093770 patent/CN101674093B/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103209046A (en) * | 2012-01-13 | 2013-07-17 | 上海华虹集成电路有限责任公司 | China mobile multimedia broadcasting (CMMB) bit de-interleaving device and method |
| CN103209046B (en) * | 2012-01-13 | 2017-10-31 | 上海华虹集成电路有限责任公司 | CMMB bytes de-interleaving apparatus and method |
| CN105099599A (en) * | 2014-04-16 | 2015-11-25 | 澜起科技（上海）有限公司 | Interleaving method, de-interleaving method and corresponding devices |
| CN105099599B (en) * | 2014-04-16 | 2019-12-27 | 上海澜至半导体有限公司 | Interleaving and deinterleaving method and corresponding device |
| CN103916140B (en) * | 2014-04-18 | 2017-03-22 | 上海高清数字科技产业有限公司 | Method and device for achieving convolution interleave/de-interleave |
| CN104993837A (en) * | 2015-07-24 | 2015-10-21 | 丽水博远科技有限公司 | Convolutional interleaving method and convolutional interleaver |
| CN104993837B (en) * | 2015-07-24 | 2018-08-03 | 丽水博远科技有限公司 | A kind of convolutional interleave method and convolutional deinterleaver |
| CN110637297A (en) * | 2017-04-27 | 2019-12-31 | 苹果公司 | Convolution engine with per-channel processing of interleaved channel data |
| CN111628787A (en) * | 2020-05-25 | 2020-09-04 | 武汉高德红外股份有限公司 | Method and system for realizing convolution interleaving and de-interleaving FPGA (field programmable Gate array) without redundant data |
| CN111628787B (en) * | 2020-05-25 | 2022-03-22 | 武汉高德红外股份有限公司 | Method and system for realizing convolution interleaving and de-interleaving FPGA (field programmable Gate array) without redundant data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101674093B (en) | 2013-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101674093B (en) | Two-stage realization method of convolutional interleave and device thereof | |
| CN1104778C (en) | Convolutional interieaver and method for generating address | |
| CN101237240B (en) | A method and device for realizing cirrocumulus interweaving/de-interweaving based on external memory | |
| CN101257313B (en) | Deconvolution interweave machine and method realized based on FPGA | |
| CN101489135B (en) | Encoder convenient for LDPC long code implementation on FPGA and encoding method | |
| CA3133553A1 (en) | Receiving apparatus using low-density parity check code and bit deinterleaving and receiving method thereof | |
| CN102412850A (en) | Turbo code parallel interleaver and parallel interleaving method thereof | |
| TWI569587B (en) | Convolutional de-interleaver | |
| CN101969310B (en) | QPP (Quadratic Permutation Polynomial) inner interleaver of Turbo code parallel decoder and interleaving method thereof | |
| CN101662336B (en) | Configurable interleave and deinterleave method and device thereof | |
| CN104601180B (en) | Method and device for encoding two-dimensional product codes on basis of extended hamming codes | |
| CN104333435A (en) | Iteration de-mapping decoding device | |
| CN104993837A (en) | Convolutional interleaving method and convolutional interleaver | |
| CN101577556A (en) | Method for realizing rectangular interweaving | |
| CN101404555B (en) | Convolution interleaving/de-interleaving method in digital transmission | |
| CN1309175C (en) | Convolution interleaving and de-interleaving method in digital transmission | |
| US20070277064A1 (en) | Reconfigurable convolutional interleaver/deinterleaver using minimum amount of memory and an address generator | |
| US20040181556A1 (en) | Deinterleaving apparatus and method for a digital communication system | |
| CN111030780B (en) | Configurable parallel bit grouping interleaver and interleaving method | |
| CN100568382C (en) | Push-up storage | |
| CN102437896B (en) | Bit interleaving and constellation mapping method and apparatus thereof | |
| CN103905066B (en) | Turbo code code translator and method | |
| CN102118219B (en) | Serial processing method and serial processing device for rate matching | |
| CN105450333A (en) | Interleaving mapping method and de-interleaving de-mapping method for LDPC code words | |
| CN102006087B (en) | Convolutional interleaving method and device based on static random access memory (SRAM) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130501 Termination date: 20180928 |